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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __amd64_ASM_H__ |
29 | #ifndef __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
31 | 31 | ||
32 | #include <arch/pm.h> |
32 | #include <arch/pm.h> |
33 | #include <arch/types.h> |
33 | #include <arch/types.h> |
34 | #include <config.h> |
34 | #include <config.h> |
35 | 35 | ||
36 | extern void asm_delay_loop(__u32 t); |
36 | extern void asm_delay_loop(__u32 t); |
37 | extern void asm_fake_loop(__u32 t); |
37 | extern void asm_fake_loop(__u32 t); |
38 | 38 | ||
39 | /** Return base address of current stack. |
39 | /** Return base address of current stack. |
40 | * |
40 | * |
41 | * Return the base address of the current stack. |
41 | * Return the base address of the current stack. |
42 | * The stack is assumed to be STACK_SIZE bytes long. |
42 | * The stack is assumed to be STACK_SIZE bytes long. |
43 | * The stack must start on page boundary. |
43 | * The stack must start on page boundary. |
44 | */ |
44 | */ |
45 | static inline __address get_stack_base(void) |
45 | static inline __address get_stack_base(void) |
46 | { |
46 | { |
47 | __address v; |
47 | __address v; |
48 | 48 | ||
49 | __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1))); |
49 | __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1))); |
50 | 50 | ||
51 | return v; |
51 | return v; |
52 | } |
52 | } |
53 | 53 | ||
54 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
54 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
55 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
55 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
56 | 56 | ||
57 | 57 | ||
58 | /** Byte from port |
58 | /** Byte from port |
59 | * |
59 | * |
60 | * Get byte from port |
60 | * Get byte from port |
61 | * |
61 | * |
62 | * @param port Port to read from |
62 | * @param port Port to read from |
63 | * @return Value read |
63 | * @return Value read |
64 | */ |
64 | */ |
65 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
65 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
66 | 66 | ||
67 | /** Byte to port |
67 | /** Byte to port |
68 | * |
68 | * |
69 | * Output byte to port |
69 | * Output byte to port |
70 | * |
70 | * |
71 | * @param port Port to write to |
71 | * @param port Port to write to |
72 | * @param val Value to write |
72 | * @param val Value to write |
73 | */ |
73 | */ |
74 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
74 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
75 | 75 | ||
76 | /** Swap Hidden part of GS register with visible one */ |
76 | /** Swap Hidden part of GS register with visible one */ |
77 | static inline void swapgs(void) { __asm__ volatile("swapgs"); } |
77 | static inline void swapgs(void) { __asm__ volatile("swapgs"); } |
78 | 78 | ||
79 | /** Enable interrupts. |
79 | /** Enable interrupts. |
80 | * |
80 | * |
81 | * Enable interrupts and return previous |
81 | * Enable interrupts and return previous |
82 | * value of EFLAGS. |
82 | * value of EFLAGS. |
83 | * |
83 | * |
84 | * @return Old interrupt priority level. |
84 | * @return Old interrupt priority level. |
85 | */ |
85 | */ |
86 | static inline ipl_t interrupts_enable(void) { |
86 | static inline ipl_t interrupts_enable(void) { |
87 | ipl_t v; |
87 | ipl_t v; |
88 | __asm__ volatile ( |
88 | __asm__ volatile ( |
89 | "pushfq\n" |
89 | "pushfq\n" |
90 | "popq %0\n" |
90 | "popq %0\n" |
91 | "sti\n" |
91 | "sti\n" |
92 | : "=r" (v) |
92 | : "=r" (v) |
93 | ); |
93 | ); |
94 | return v; |
94 | return v; |
95 | } |
95 | } |
96 | 96 | ||
97 | /** Disable interrupts. |
97 | /** Disable interrupts. |
98 | * |
98 | * |
99 | * Disable interrupts and return previous |
99 | * Disable interrupts and return previous |
100 | * value of EFLAGS. |
100 | * value of EFLAGS. |
101 | * |
101 | * |
102 | * @return Old interrupt priority level. |
102 | * @return Old interrupt priority level. |
103 | */ |
103 | */ |
104 | static inline ipl_t interrupts_disable(void) { |
104 | static inline ipl_t interrupts_disable(void) { |
105 | ipl_t v; |
105 | ipl_t v; |
106 | __asm__ volatile ( |
106 | __asm__ volatile ( |
107 | "pushfq\n" |
107 | "pushfq\n" |
108 | "popq %0\n" |
108 | "popq %0\n" |
109 | "cli\n" |
109 | "cli\n" |
110 | : "=r" (v) |
110 | : "=r" (v) |
111 | ); |
111 | ); |
112 | return v; |
112 | return v; |
113 | } |
113 | } |
114 | 114 | ||
115 | /** Restore interrupt priority level. |
115 | /** Restore interrupt priority level. |
116 | * |
116 | * |
117 | * Restore EFLAGS. |
117 | * Restore EFLAGS. |
118 | * |
118 | * |
119 | * @param ipl Saved interrupt priority level. |
119 | * @param ipl Saved interrupt priority level. |
120 | */ |
120 | */ |
121 | static inline void interrupts_restore(ipl_t ipl) { |
121 | static inline void interrupts_restore(ipl_t ipl) { |
122 | __asm__ volatile ( |
122 | __asm__ volatile ( |
123 | "pushq %0\n" |
123 | "pushq %0\n" |
124 | "popfq\n" |
124 | "popfq\n" |
125 | : : "r" (ipl) |
125 | : : "r" (ipl) |
126 | ); |
126 | ); |
127 | } |
127 | } |
128 | 128 | ||
129 | /** Return interrupt priority level. |
129 | /** Return interrupt priority level. |
130 | * |
130 | * |
131 | * Return EFLAFS. |
131 | * Return EFLAFS. |
132 | * |
132 | * |
133 | * @return Current interrupt priority level. |
133 | * @return Current interrupt priority level. |
134 | */ |
134 | */ |
135 | static inline ipl_t interrupts_read(void) { |
135 | static inline ipl_t interrupts_read(void) { |
136 | ipl_t v; |
136 | ipl_t v; |
137 | __asm__ volatile ( |
137 | __asm__ volatile ( |
138 | "pushfq\n" |
138 | "pushfq\n" |
139 | "popq %0\n" |
139 | "popq %0\n" |
140 | : "=r" (v) |
140 | : "=r" (v) |
141 | ); |
141 | ); |
142 | return v; |
142 | return v; |
143 | } |
143 | } |
144 | 144 | ||
145 | /** Write to MSR */ |
145 | /** Write to MSR */ |
146 | static inline void write_msr(__u32 msr, __u64 value) |
146 | static inline void write_msr(__u32 msr, __u64 value) |
147 | { |
147 | { |
148 | __asm__ volatile ( |
148 | __asm__ volatile ( |
149 | "wrmsr;" : : "c" (msr), |
149 | "wrmsr;" : : "c" (msr), |
150 | "a" ((__u32)(value)), |
150 | "a" ((__u32)(value)), |
151 | "d" ((__u32)(value >> 32)) |
151 | "d" ((__u32)(value >> 32)) |
152 | ); |
152 | ); |
153 | } |
153 | } |
154 | 154 | ||
155 | static inline __native read_msr(__u32 msr) |
155 | static inline __native read_msr(__u32 msr) |
156 | { |
156 | { |
157 | __u32 ax, dx; |
157 | __u32 ax, dx; |
158 | 158 | ||
159 | __asm__ volatile ( |
159 | __asm__ volatile ( |
160 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
160 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
161 | ); |
161 | ); |
162 | return ((__u64)dx << 32) | ax; |
162 | return ((__u64)dx << 32) | ax; |
163 | } |
163 | } |
164 | 164 | ||
165 | 165 | ||
166 | /** Enable local APIC |
166 | /** Enable local APIC |
167 | * |
167 | * |
168 | * Enable local APIC in MSR. |
168 | * Enable local APIC in MSR. |
169 | */ |
169 | */ |
170 | static inline void enable_l_apic_in_msr() |
170 | static inline void enable_l_apic_in_msr() |
171 | { |
171 | { |
172 | __asm__ volatile ( |
172 | __asm__ volatile ( |
173 | "movl $0x1b, %%ecx\n" |
173 | "movl $0x1b, %%ecx\n" |
174 | "rdmsr\n" |
174 | "rdmsr\n" |
175 | "orl $(1<<11),%%eax\n" |
175 | "orl $(1<<11),%%eax\n" |
176 | "orl $(0xfee00000),%%eax\n" |
176 | "orl $(0xfee00000),%%eax\n" |
177 | "wrmsr\n" |
177 | "wrmsr\n" |
178 | : |
178 | : |
179 | : |
179 | : |
180 | :"%eax","%ecx","%edx" |
180 | :"%eax","%ecx","%edx" |
181 | ); |
181 | ); |
182 | } |
182 | } |
183 | 183 | ||
184 | static inline __address * get_ip() |
184 | static inline __address * get_ip() |
185 | { |
185 | { |
186 | __address *ip; |
186 | __address *ip; |
187 | 187 | ||
188 | __asm__ volatile ( |
188 | __asm__ volatile ( |
189 | "mov %%rip, %0" |
189 | "mov %%rip, %0" |
190 | : "=r" (ip) |
190 | : "=r" (ip) |
191 | ); |
191 | ); |
192 | return ip; |
192 | return ip; |
193 | } |
193 | } |
194 | 194 | ||
195 | /** Invalidate TLB Entry. |
195 | /** Invalidate TLB Entry. |
196 | * |
196 | * |
197 | * @param addr Address on a page whose TLB entry is to be invalidated. |
197 | * @param addr Address on a page whose TLB entry is to be invalidated. |
198 | */ |
198 | */ |
199 | static inline void invlpg(__address addr) |
199 | static inline void invlpg(__address addr) |
200 | { |
200 | { |
201 | __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr))); |
201 | __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr))); |
202 | } |
202 | } |
203 | 203 | ||
204 | /** Load GDTR register from memory. |
204 | /** Load GDTR register from memory. |
205 | * |
205 | * |
206 | * @param gdtr_reg Address of memory from where to load GDTR. |
206 | * @param gdtr_reg Address of memory from where to load GDTR. |
207 | */ |
207 | */ |
208 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
208 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
209 | { |
209 | { |
210 | __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg)); |
210 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
211 | } |
211 | } |
212 | 212 | ||
213 | /** Store GDTR register to memory. |
213 | /** Store GDTR register to memory. |
214 | * |
214 | * |
215 | * @param gdtr_reg Address of memory to where to load GDTR. |
215 | * @param gdtr_reg Address of memory to where to load GDTR. |
216 | */ |
216 | */ |
217 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
217 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
218 | { |
218 | { |
219 | __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg)); |
219 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
220 | } |
220 | } |
221 | 221 | ||
222 | /** Load IDTR register from memory. |
222 | /** Load IDTR register from memory. |
223 | * |
223 | * |
224 | * @param idtr_reg Address of memory from where to load IDTR. |
224 | * @param idtr_reg Address of memory from where to load IDTR. |
225 | */ |
225 | */ |
226 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
226 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
227 | { |
227 | { |
228 | __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg)); |
228 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
229 | } |
229 | } |
230 | 230 | ||
231 | /** Load TR from descriptor table. |
231 | /** Load TR from descriptor table. |
232 | * |
232 | * |
233 | * @param sel Selector specifying descriptor of TSS segment. |
233 | * @param sel Selector specifying descriptor of TSS segment. |
234 | */ |
234 | */ |
235 | static inline void tr_load(__u16 sel) |
235 | static inline void tr_load(__u16 sel) |
236 | { |
236 | { |
237 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
237 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
238 | } |
238 | } |
239 | 239 | ||
240 | #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
240 | #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
241 | { \ |
241 | { \ |
242 | __native res; \ |
242 | __native res; \ |
243 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
243 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
244 | return res; \ |
244 | return res; \ |
245 | } |
245 | } |
246 | 246 | ||
247 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
247 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
248 | { \ |
248 | { \ |
249 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
249 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
250 | } |
250 | } |
251 | 251 | ||
252 | GEN_READ_REG(cr0); |
252 | GEN_READ_REG(cr0); |
253 | GEN_READ_REG(cr2); |
253 | GEN_READ_REG(cr2); |
254 | GEN_READ_REG(cr3); |
254 | GEN_READ_REG(cr3); |
255 | GEN_WRITE_REG(cr3); |
255 | GEN_WRITE_REG(cr3); |
256 | 256 | ||
257 | GEN_READ_REG(dr0); |
257 | GEN_READ_REG(dr0); |
258 | GEN_READ_REG(dr1); |
258 | GEN_READ_REG(dr1); |
259 | GEN_READ_REG(dr2); |
259 | GEN_READ_REG(dr2); |
260 | GEN_READ_REG(dr3); |
260 | GEN_READ_REG(dr3); |
261 | GEN_READ_REG(dr6); |
261 | GEN_READ_REG(dr6); |
262 | GEN_READ_REG(dr7); |
262 | GEN_READ_REG(dr7); |
263 | 263 | ||
264 | GEN_WRITE_REG(dr0); |
264 | GEN_WRITE_REG(dr0); |
265 | GEN_WRITE_REG(dr1); |
265 | GEN_WRITE_REG(dr1); |
266 | GEN_WRITE_REG(dr2); |
266 | GEN_WRITE_REG(dr2); |
267 | GEN_WRITE_REG(dr3); |
267 | GEN_WRITE_REG(dr3); |
268 | GEN_WRITE_REG(dr6); |
268 | GEN_WRITE_REG(dr6); |
269 | GEN_WRITE_REG(dr7); |
269 | GEN_WRITE_REG(dr7); |
270 | 270 | ||
271 | 271 | ||
272 | extern size_t interrupt_handler_size; |
272 | extern size_t interrupt_handler_size; |
273 | extern void interrupt_handlers(void); |
273 | extern void interrupt_handlers(void); |
274 | 274 | ||
275 | #endif |
275 | #endif |
276 | 276 |