WebSVN – HelenOS – Diff – /tags/0.4.1/boot/arch/mips32/loader/boot.S


#
# Copyright (c) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include "regname.h"
#include "main.h"
 
.set noat
.set noreorder
.set nomacro
 
.section BOOTSTRAP
 
.global start
start:
	
	/* Setup CPU map (on msim this code
	   is executed in parallel on all CPUs,
	   but it not an issue) */
	la $a0, CPUMAP
	
	sw $zero, 0($a0)
	sw $zero, 4($a0)
	sw $zero, 8($a0)
	sw $zero, 12($a0)
	
	sw $zero, 16($a0)
	sw $zero, 20($a0)
	sw $zero, 24($a0)
	sw $zero, 28($a0)
	
	sw $zero, 32($a0)
	sw $zero, 36($a0)
	sw $zero, 40($a0)
	sw $zero, 44($a0)
	
	sw $zero, 48($a0)
	sw $zero, 52($a0)
	sw $zero, 56($a0)
	sw $zero, 60($a0)
	
	sw $zero, 64($a0)
	sw $zero, 68($a0)
	sw $zero, 72($a0)
	sw $zero, 76($a0)
	
	sw $zero, 80($a0)
	sw $zero, 84($a0)
	sw $zero, 88($a0)
	sw $zero, 92($a0)
	
	sw $zero, 96($a0)
	sw $zero, 100($a0)
	sw $zero, 104($a0)
	sw $zero, 108($a0)
	
	sw $zero, 112($a0)
	sw $zero, 116($a0)
	sw $zero, 120($a0)
	sw $zero, 124($a0)
	
	lui $a1, 1
	
#ifdef MACHINE_msim
	
	/* Read dorder value */
	la $k0, MSIM_DORDER_ADDRESS
	lw $k1, ($k0)
	
	/* If we are not running on BSP
	   then end in an infinite loop  */
	beq $k1, $zero, bsp
	nop
	
	/* Record CPU presence */
	sll $a2, $k1, 2
	addu $a2, $a2, $a0
	sw $a1, ($a2)
	
	loop:
		j loop
		nop
	
#endif
	
	bsp:
		/* Record CPU presence */
		sw $a1, ($a0)
		
		/* Setup initial stack */
		la $sp, INITIAL_STACK
		
		j bootstrap
		nop
 

Rev 3922	Rev 4687
1	#	1	#
2	# Copyright (c) 2006 Martin Decky	2	# Copyright (c) 2006 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include "regname.h"	29	#include "regname.h"
30	#include "main.h"	30	#include "main.h"
31		31
32	.set noat	32	.set noat
33	.set noreorder	33	.set noreorder
34	.set nomacro	34	.set nomacro
35		35
36	.section BOOTSTRAP	36	.section BOOTSTRAP
37		37
38	.global start	38	.global start
39	start:	39	start:
40		40
41	/* Setup CPU map (on msim this code	41	/* Setup CPU map (on msim this code
42	is executed in parallel on all CPUs,	42	is executed in parallel on all CPUs,
43	but it not an issue) */	43	but it not an issue) */
44	la $a0, CPUMAP	44	la $a0, CPUMAP
45		45
46	sw $zero, 0($a0)	46	sw $zero, 0($a0)
47	sw $zero, 4($a0)	47	sw $zero, 4($a0)
48	sw $zero, 8($a0)	48	sw $zero, 8($a0)
49	sw $zero, 12($a0)	49	sw $zero, 12($a0)
50		50
51	sw $zero, 16($a0)	51	sw $zero, 16($a0)
52	sw $zero, 20($a0)	52	sw $zero, 20($a0)
53	sw $zero, 24($a0)	53	sw $zero, 24($a0)
54	sw $zero, 28($a0)	54	sw $zero, 28($a0)
55		55
56	sw $zero, 32($a0)	56	sw $zero, 32($a0)
57	sw $zero, 36($a0)	57	sw $zero, 36($a0)
58	sw $zero, 40($a0)	58	sw $zero, 40($a0)
59	sw $zero, 44($a0)	59	sw $zero, 44($a0)
60		60
61	sw $zero, 48($a0)	61	sw $zero, 48($a0)
62	sw $zero, 52($a0)	62	sw $zero, 52($a0)
63	sw $zero, 56($a0)	63	sw $zero, 56($a0)
64	sw $zero, 60($a0)	64	sw $zero, 60($a0)
65		65
66	sw $zero, 64($a0)	66	sw $zero, 64($a0)
67	sw $zero, 68($a0)	67	sw $zero, 68($a0)
68	sw $zero, 72($a0)	68	sw $zero, 72($a0)
69	sw $zero, 76($a0)	69	sw $zero, 76($a0)
70		70
71	sw $zero, 80($a0)	71	sw $zero, 80($a0)
72	sw $zero, 84($a0)	72	sw $zero, 84($a0)
73	sw $zero, 88($a0)	73	sw $zero, 88($a0)
74	sw $zero, 92($a0)	74	sw $zero, 92($a0)
75		75
76	sw $zero, 96($a0)	76	sw $zero, 96($a0)
77	sw $zero, 100($a0)	77	sw $zero, 100($a0)
78	sw $zero, 104($a0)	78	sw $zero, 104($a0)
79	sw $zero, 108($a0)	79	sw $zero, 108($a0)
80		80
81	sw $zero, 112($a0)	81	sw $zero, 112($a0)
82	sw $zero, 116($a0)	82	sw $zero, 116($a0)
83	sw $zero, 120($a0)	83	sw $zero, 120($a0)
84	sw $zero, 124($a0)	84	sw $zero, 124($a0)
85		85
86	lui $a1, 1	86	lui $a1, 1
87		87
88	#ifdef MACHINE_msim	88	#ifdef MACHINE_msim
89		89
90	/* Read dorder value */	90	/* Read dorder value */
91	la $k0, MSIM_DORDER_ADDRESS	91	la $k0, MSIM_DORDER_ADDRESS
92	lw $k1, ($k0)	92	lw $k1, ($k0)
93		93
94	/* If we are not running on BSP	94	/* If we are not running on BSP
95	then end in an infinite loop */	95	then end in an infinite loop */
96	beq $k1, $zero, bsp	96	beq $k1, $zero, bsp
97	nop	97	nop
98		98
99	/* Record CPU presence */	99	/* Record CPU presence */
100	sll $a2, $k1, 2	100	sll $a2, $k1, 2
101	addu $a2, $a2, $a0	101	addu $a2, $a2, $a0
102	sw $a1, ($a2)	102	sw $a1, ($a2)
103		103
104	loop:	104	loop:
105	j loop	105	j loop
106	nop	106	nop
107		107
108	#endif	108	#endif
109		109
110	bsp:	110	bsp:
111	/* Record CPU presence */	111	/* Record CPU presence */
112	sw $a1, ($a0)	112	sw $a1, ($a0)
113		113
114	/* Setup initial stack */	114	/* Setup initial stack */
115	la $sp, INITIAL_STACK	115	la $sp, INITIAL_STACK
116		116
117	j bootstrap	117	j bootstrap
118	nop	118	nop
119		119

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(root)/tags/0.4.1/boot/arch/mips32/loader/boot.S – Rev 3922 → 4687