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1
/*
1
/*
2
 * Copyright (c) 2007 Petr Stepan
2
 * Copyright (c) 2007 Petr Stepan
3
 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
/** @addtogroup arm32
29
/** @addtogroup arm32
30
 * @{
30
 * @{
31
 */
31
 */
32
/** @file
32
/** @file
33
 *  @brief Exception handlers and exception initialization routines.
33
 *  @brief Exception handlers and exception initialization routines.
34
 */
34
 */
35
 
35
 
36
#include <arch/exception.h>
36
#include <arch/exception.h>
37
#include <arch/debug/print.h>
37
#include <arch/debug/print.h>
38
#include <arch/memstr.h>
38
#include <arch/memstr.h>
39
#include <arch/regutils.h>
39
#include <arch/regutils.h>
40
#include <interrupt.h>
40
#include <interrupt.h>
41
#include <arch/machine.h>
41
#include <arch/machine.h>
42
#include <arch/mm/page_fault.h>
42
#include <arch/mm/page_fault.h>
43
#include <arch/barrier.h>
43
#include <arch/barrier.h>
44
#include <print.h>
44
#include <print.h>
45
#include <syscall/syscall.h>
45
#include <syscall/syscall.h>
46
 
46
 
47
/** Offset used in calculation of exception handler's relative address.
47
/** Offset used in calculation of exception handler's relative address.
48
 *
48
 *
49
 * @see install_handler()
49
 * @see install_handler()
50
 */
50
 */
51
#define PREFETCH_OFFSET      0x8
51
#define PREFETCH_OFFSET      0x8
52
 
52
 
53
/** LDR instruction's code */
53
/** LDR instruction's code */
54
#define LDR_OPCODE           0xe59ff000
54
#define LDR_OPCODE           0xe59ff000
55
 
55
 
56
/** Number of exception vectors. */
56
/** Number of exception vectors. */
57
#define EXC_VECTORS          8
57
#define EXC_VECTORS          8
58
 
58
 
59
/** Size of memory block occupied by exception vectors. */
59
/** Size of memory block occupied by exception vectors. */
60
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
60
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
61
 
61
 
62
/** Switches to kernel stack and saves all registers there.
62
/** Switches to kernel stack and saves all registers there.
63
 *
63
 *
64
 * Temporary exception stack is used to save a few registers
64
 * Temporary exception stack is used to save a few registers
65
 * before stack switch takes place.
65
 * before stack switch takes place.
66
 */
66
 */
67
inline static void setup_stack_and_save_regs()
67
inline static void setup_stack_and_save_regs()
68
{
68
{
69
    asm volatile(
69
    asm volatile(
70
        "ldr r13, =exc_stack        \n"
70
        "ldr r13, =exc_stack        \n"
71
        "stmfd r13!, {r0}       \n"
71
        "stmfd r13!, {r0}       \n"
72
        "mrs r0, spsr           \n"
72
        "mrs r0, spsr           \n"
73
        "and r0, r0, #0x1f      \n"
73
        "and r0, r0, #0x1f      \n"
74
        "cmp r0, #0x10          \n"
74
        "cmp r0, #0x10          \n"
75
        "bne 1f             \n"
75
        "bne 1f             \n"
76
 
76
 
77
        /* prev mode was usermode */
77
        /* prev mode was usermode */
78
        "ldmfd r13!, {r0}       \n"
78
        "ldmfd r13!, {r0}       \n"
79
        "ldr r13, =supervisor_sp    \n"
79
        "ldr r13, =supervisor_sp    \n"
80
        "ldr r13, [r13]         \n"
80
        "ldr r13, [r13]         \n"
81
        "stmfd r13!, {lr}       \n"
81
        "stmfd r13!, {lr}       \n"
82
        "stmfd r13!, {r0-r12}       \n"
82
        "stmfd r13!, {r0-r12}       \n"
83
        "stmfd r13!, {r13, lr}^     \n"
83
        "stmfd r13!, {r13, lr}^     \n"
84
        "mrs r0, spsr           \n"
84
        "mrs r0, spsr           \n"
85
        "stmfd r13!, {r0}       \n"
85
        "stmfd r13!, {r0}       \n"
86
        "b 2f               \n"
86
        "b 2f               \n"
87
 
87
 
88
        /* mode was not usermode */
88
        /* mode was not usermode */
89
    "1:\n"
89
    "1:\n"
90
        "stmfd r13!, {r1, r2, r3}   \n"
90
        "stmfd r13!, {r1, r2, r3}   \n"
91
        "mrs r1, cpsr           \n"
91
        "mrs r1, cpsr           \n"
92
        "mov r2, lr         \n"
92
        "mov r2, lr         \n"
93
        "bic r1, r1, #0x1f      \n"
93
        "bic r1, r1, #0x1f      \n"
94
        "orr r1, r1, r0         \n"
94
        "orr r1, r1, r0         \n"
95
        "mrs r0, cpsr           \n"
95
        "mrs r0, cpsr           \n"
96
        "msr cpsr_c, r1         \n"
96
        "msr cpsr_c, r1         \n"
97
 
97
 
98
        "mov r3, r13            \n"
98
        "mov r3, r13            \n"
99
        "stmfd r13!, {r2}       \n"
99
        "stmfd r13!, {r2}       \n"
100
        "mov r2, lr         \n"
100
        "mov r2, lr         \n"
101
        "stmfd r13!, {r4-r12}       \n"
101
        "stmfd r13!, {r4-r12}       \n"
102
        "mov r1, r13            \n"
102
        "mov r1, r13            \n"
103
        /* the following two lines are for debugging */
103
        /* the following two lines are for debugging */
104
        "mov sp, #0         \n"
104
        "mov sp, #0         \n"
105
        "mov lr, #0         \n"
105
        "mov lr, #0         \n"
106
        "msr cpsr_c, r0         \n"
106
        "msr cpsr_c, r0         \n"
107
 
107
 
108
        "ldmfd r13!, {r4, r5, r6, r7}   \n"
108
        "ldmfd r13!, {r4, r5, r6, r7}   \n"
109
        "stmfd r1!, {r4, r5, r6}    \n"
109
        "stmfd r1!, {r4, r5, r6}    \n"
110
        "stmfd r1!, {r7}        \n"
110
        "stmfd r1!, {r7}        \n"
111
        "stmfd r1!, {r2}        \n"
111
        "stmfd r1!, {r2}        \n"
112
        "stmfd r1!, {r3}        \n"
112
        "stmfd r1!, {r3}        \n"
113
        "mrs r0, spsr           \n"
113
        "mrs r0, spsr           \n"
114
        "stmfd r1!, {r0}        \n"
114
        "stmfd r1!, {r0}        \n"
115
        "mov r13, r1            \n"
115
        "mov r13, r1            \n"
116
    "2:\n"
116
    "2:\n"
117
    );
117
    );
118
}
118
}
119
 
119
 
120
/** Returns from exception mode.
120
/** Returns from exception mode.
121
 *
121
 *
122
 * Previously saved state of registers (including control register)
122
 * Previously saved state of registers (including control register)
123
 * is restored from the stack.
123
 * is restored from the stack.
124
 */
124
 */
125
inline static void load_regs()
125
inline static void load_regs()
126
{
126
{
127
    asm volatile(
127
    asm volatile(
128
        "ldmfd r13!, {r0}       \n"
128
        "ldmfd r13!, {r0}       \n"
129
        "msr spsr, r0           \n"
129
        "msr spsr, r0           \n"
130
        "and r0, r0, #0x1f      \n"
130
        "and r0, r0, #0x1f      \n"
131
        "cmp r0, #0x10          \n"
131
        "cmp r0, #0x10          \n"
132
        "bne 1f             \n"
132
        "bne 1f             \n"
133
 
133
 
134
        /* return to user mode */
134
        /* return to user mode */
135
        "ldmfd r13!, {r13, lr}^     \n"
135
        "ldmfd r13!, {r13, lr}^     \n"
136
        "b 2f               \n"
136
        "b 2f               \n"
137
 
137
 
138
        /* return to non-user mode */
138
        /* return to non-user mode */
139
    "1:\n"
139
    "1:\n"
140
        "ldmfd r13!, {r1, r2}       \n"
140
        "ldmfd r13!, {r1, r2}       \n"
141
        "mrs r3, cpsr           \n"
141
        "mrs r3, cpsr           \n"
142
        "bic r3, r3, #0x1f      \n"
142
        "bic r3, r3, #0x1f      \n"
143
        "orr r3, r3, r0         \n"
143
        "orr r3, r3, r0         \n"
144
        "mrs r0, cpsr           \n"
144
        "mrs r0, cpsr           \n"
145
        "msr cpsr_c, r3         \n"
145
        "msr cpsr_c, r3         \n"
146
 
146
 
147
        "mov r13, r1            \n"
147
        "mov r13, r1            \n"
148
        "mov lr, r2         \n"
148
        "mov lr, r2         \n"
149
        "msr cpsr_c, r0         \n"
149
        "msr cpsr_c, r0         \n"
150
 
150
 
151
        /* actual return */
151
        /* actual return */
152
    "2:\n"
152
    "2:\n"
153
        "ldmfd r13, {r0-r12, pc}^\n"
153
        "ldmfd r13, {r0-r12, pc}^\n"
154
    );
154
    );
155
}
155
}
156
 
156
 
157
 
157
 
158
/** Switch CPU to mode in which interrupts are serviced (currently it
158
/** Switch CPU to mode in which interrupts are serviced (currently it
159
 * is Undefined mode).
159
 * is Undefined mode).
160
 *
160
 *
161
 * The default mode for interrupt servicing (Interrupt Mode)
161
 * The default mode for interrupt servicing (Interrupt Mode)
162
 * can not be used because of nested interrupts (which can occur
162
 * can not be used because of nested interrupts (which can occur
163
 * because interrupts are enabled in higher levels of interrupt handler).
163
 * because interrupts are enabled in higher levels of interrupt handler).
164
 */
164
 */
165
inline static void switch_to_irq_servicing_mode()
165
inline static void switch_to_irq_servicing_mode()
166
{
166
{
167
    /* switch to Undefined mode */
167
    /* switch to Undefined mode */
168
    asm volatile(
168
    asm volatile(
169
        /* save regs used during switching */
169
        /* save regs used during switching */
170
        "stmfd sp!, {r0-r3}     \n"
170
        "stmfd sp!, {r0-r3}     \n"
171
 
171
 
172
        /* save stack pointer and link register to r1, r2 */
172
        /* save stack pointer and link register to r1, r2 */
173
        "mov r1, sp         \n"
173
        "mov r1, sp         \n"
174
        "mov r2, lr         \n"
174
        "mov r2, lr         \n"
175
 
175
 
176
        /* mode switch */
176
        /* mode switch */
177
        "mrs r0, cpsr           \n"
177
        "mrs r0, cpsr           \n"
178
        "bic r0, r0, #0x1f      \n"
178
        "bic r0, r0, #0x1f      \n"
179
        "orr r0, r0, #0x1b      \n"
179
        "orr r0, r0, #0x1b      \n"
180
        "msr cpsr_c, r0         \n"
180
        "msr cpsr_c, r0         \n"
181
 
181
 
182
        /* restore saved sp and lr */
182
        /* restore saved sp and lr */
183
        "mov sp, r1         \n"
183
        "mov sp, r1         \n"
184
        "mov lr, r2         \n"
184
        "mov lr, r2         \n"
185
 
185
 
186
        /* restore original regs */
186
        /* restore original regs */
187
        "ldmfd sp!, {r0-r3}     \n"
187
        "ldmfd sp!, {r0-r3}     \n"
188
    );
188
    );
189
}
189
}
190
 
190
 
191
/** Calls exception dispatch routine. */
191
/** Calls exception dispatch routine. */
192
#define CALL_EXC_DISPATCH(exception)        \
192
#define CALL_EXC_DISPATCH(exception)        \
193
    asm("mov r0, %0" : : "i" (exception));  \
193
    asm("mov r0, %0" : : "i" (exception));  \
194
    asm("mov r1, r13");         \
194
    asm("mov r1, r13");         \
195
    asm("bl exc_dispatch");     
195
    asm("bl exc_dispatch");     
196
 
196
 
197
/** General exception handler.
197
/** General exception handler.
198
 *
198
 *
199
 *  Stores registers, dispatches the exception,
199
 *  Stores registers, dispatches the exception,
200
 *  and finally restores registers and returns from exception processing.
200
 *  and finally restores registers and returns from exception processing.
201
 *
201
 *
202
 *  @param exception Exception number.
202
 *  @param exception Exception number.
203
 */
203
 */
204
#define PROCESS_EXCEPTION(exception)        \
204
#define PROCESS_EXCEPTION(exception)        \
205
    setup_stack_and_save_regs();        \
205
    setup_stack_and_save_regs();        \
206
    CALL_EXC_DISPATCH(exception)        \
206
    CALL_EXC_DISPATCH(exception)        \
207
    load_regs();
207
    load_regs();
208
 
208
 
209
/** Updates specified exception vector to jump to given handler.
209
/** Updates specified exception vector to jump to given handler.
210
 *
210
 *
211
 *  Addresses of handlers are stored in memory following exception vectors.
211
 *  Addresses of handlers are stored in memory following exception vectors.
212
 */
212
 */
213
static void install_handler(unsigned handler_addr, unsigned *vector)
213
static void install_handler(unsigned handler_addr, unsigned *vector)
214
{
214
{
215
    /* relative address (related to exc. vector) of the word
215
    /* relative address (related to exc. vector) of the word
216
     * where handler's address is stored
216
     * where handler's address is stored
217
    */
217
    */
218
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
218
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
219
        PREFETCH_OFFSET;
219
        PREFETCH_OFFSET;
220
   
220
   
221
    /* make it LDR instruction and store at exception vector */
221
    /* make it LDR instruction and store at exception vector */
222
    *vector = handler_address_ptr | LDR_OPCODE;
222
    *vector = handler_address_ptr | LDR_OPCODE;
223
    smc_coherence(*vector);
223
    smc_coherence(*vector);
224
   
224
   
225
    /* store handler's address */
225
    /* store handler's address */
226
    *(vector + EXC_VECTORS) = handler_addr;
226
    *(vector + EXC_VECTORS) = handler_addr;
227
 
227
 
228
}
228
}
229
 
229
 
230
/** Low-level Reset Exception handler. */
230
/** Low-level Reset Exception handler. */
231
static void reset_exception_entry(void)
231
static void reset_exception_entry(void)
232
{
232
{
233
    PROCESS_EXCEPTION(EXC_RESET);
233
    PROCESS_EXCEPTION(EXC_RESET);
234
}
234
}
235
 
235
 
236
/** Low-level Software Interrupt Exception handler. */
236
/** Low-level Software Interrupt Exception handler. */
237
static void swi_exception_entry(void)
237
static void swi_exception_entry(void)
238
{
238
{
239
    PROCESS_EXCEPTION(EXC_SWI);
239
    PROCESS_EXCEPTION(EXC_SWI);
240
}
240
}
241
 
241
 
242
/** Low-level Undefined Instruction Exception handler. */
242
/** Low-level Undefined Instruction Exception handler. */
243
static void undef_instr_exception_entry(void)
243
static void undef_instr_exception_entry(void)
244
{
244
{
245
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
245
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
246
}
246
}
247
 
247
 
248
/** Low-level Fast Interrupt Exception handler. */
248
/** Low-level Fast Interrupt Exception handler. */
249
static void fiq_exception_entry(void)
249
static void fiq_exception_entry(void)
250
{
250
{
251
    PROCESS_EXCEPTION(EXC_FIQ);
251
    PROCESS_EXCEPTION(EXC_FIQ);
252
}
252
}
253
 
253
 
254
/** Low-level Prefetch Abort Exception handler. */
254
/** Low-level Prefetch Abort Exception handler. */
255
static void prefetch_abort_exception_entry(void)
255
static void prefetch_abort_exception_entry(void)
256
{
256
{
257
    asm("sub lr, lr, #4");
257
    asm("sub lr, lr, #4");
258
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
258
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
259
}
259
}
260
 
260
 
261
/** Low-level Data Abort Exception handler. */
261
/** Low-level Data Abort Exception handler. */
262
static void data_abort_exception_entry(void)
262
static void data_abort_exception_entry(void)
263
{
263
{
264
    asm("sub lr, lr, #8");
264
    asm("sub lr, lr, #8");
265
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
265
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
266
}
266
}
267
 
267
 
268
/** Low-level Interrupt Exception handler.
268
/** Low-level Interrupt Exception handler.
269
 *
269
 *
270
 * CPU is switched to Undefined mode before further interrupt processing
270
 * CPU is switched to Undefined mode before further interrupt processing
271
 * because of possible occurence of nested interrupt exception, which
271
 * because of possible occurence of nested interrupt exception, which
272
 * would overwrite (and thus spoil) stack pointer.
272
 * would overwrite (and thus spoil) stack pointer.
273
 */
273
 */
274
static void irq_exception_entry(void)
274
static void irq_exception_entry(void)
275
{
275
{
276
    asm("sub lr, lr, #4");
276
    asm("sub lr, lr, #4");
277
    setup_stack_and_save_regs();
277
    setup_stack_and_save_regs();
278
   
278
   
279
    switch_to_irq_servicing_mode();
279
    switch_to_irq_servicing_mode();
280
   
280
   
281
    CALL_EXC_DISPATCH(EXC_IRQ)
281
    CALL_EXC_DISPATCH(EXC_IRQ)
282
 
282
 
283
    load_regs();
283
    load_regs();
284
}
284
}
285
 
285
 
286
/** Software Interrupt handler.
286
/** Software Interrupt handler.
287
 *
287
 *
288
 * Dispatches the syscall.
288
 * Dispatches the syscall.
289
 */
289
 */
290
static void swi_exception(int exc_no, istate_t *istate)
290
static void swi_exception(int exc_no, istate_t *istate)
291
{
291
{
292
    istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
292
    istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
293
        istate->r3, istate->r4, istate->r5, istate->r6);
293
        istate->r3, istate->r4, istate->r5, istate->r6);
294
}
294
}
295
 
295
 
296
/** Interrupt Exception handler.
296
/** Interrupt Exception handler.
297
 *
297
 *
298
 * Determines the sources of interrupt and calls their handlers.
298
 * Determines the sources of interrupt and calls their handlers.
299
 */
299
 */
300
static void irq_exception(int exc_no, istate_t *istate)
300
static void irq_exception(int exc_no, istate_t *istate)
301
{
301
{
302
    machine_irq_exception(exc_no, istate);
302
    machine_irq_exception(exc_no, istate);
303
}
303
}
304
 
304
 
305
/** Fills exception vectors with appropriate exception handlers. */
305
/** Fills exception vectors with appropriate exception handlers. */
306
void install_exception_handlers(void)
306
void install_exception_handlers(void)
307
{
307
{
308
    install_handler((unsigned) reset_exception_entry,
308
    install_handler((unsigned) reset_exception_entry,
309
        (unsigned *) EXC_RESET_VEC);
309
        (unsigned *) EXC_RESET_VEC);
310
   
310
   
311
    install_handler((unsigned) undef_instr_exception_entry,
311
    install_handler((unsigned) undef_instr_exception_entry,
312
        (unsigned *) EXC_UNDEF_INSTR_VEC);
312
        (unsigned *) EXC_UNDEF_INSTR_VEC);
313
   
313
   
314
    install_handler((unsigned) swi_exception_entry,
314
    install_handler((unsigned) swi_exception_entry,
315
        (unsigned *) EXC_SWI_VEC);
315
        (unsigned *) EXC_SWI_VEC);
316
   
316
   
317
    install_handler((unsigned) prefetch_abort_exception_entry,
317
    install_handler((unsigned) prefetch_abort_exception_entry,
318
        (unsigned *) EXC_PREFETCH_ABORT_VEC);
318
        (unsigned *) EXC_PREFETCH_ABORT_VEC);
319
   
319
   
320
    install_handler((unsigned) data_abort_exception_entry,
320
    install_handler((unsigned) data_abort_exception_entry,
321
        (unsigned *) EXC_DATA_ABORT_VEC);
321
        (unsigned *) EXC_DATA_ABORT_VEC);
322
   
322
   
323
    install_handler((unsigned) irq_exception_entry,
323
    install_handler((unsigned) irq_exception_entry,
324
        (unsigned *) EXC_IRQ_VEC);
324
        (unsigned *) EXC_IRQ_VEC);
325
   
325
   
326
    install_handler((unsigned)fiq_exception_entry,
326
    install_handler((unsigned)fiq_exception_entry,
327
        (unsigned *) EXC_FIQ_VEC);
327
        (unsigned *) EXC_FIQ_VEC);
328
}
328
}
329
 
329
 
330
#ifdef HIGH_EXCEPTION_VECTORS
330
#ifdef HIGH_EXCEPTION_VECTORS
331
/** Activates use of high exception vectors addresses. */
331
/** Activates use of high exception vectors addresses. */
332
static void high_vectors(void)
332
static void high_vectors(void)
333
{
333
{
334
    uint32_t control_reg;
334
    uint32_t control_reg;
335
   
335
   
336
    asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
336
    asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
337
   
337
   
338
    /* switch on the high vectors bit */
338
    /* switch on the high vectors bit */
339
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
339
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
340
   
340
   
341
    asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
341
    asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
342
}
342
}
343
#endif
343
#endif
344
 
344
 
345
/** Initializes exception handling.
345
/** Initializes exception handling.
346
 *
346
 *
347
 * Installs low-level exception handlers and then registers
347
 * Installs low-level exception handlers and then registers
348
 * exceptions and their handlers to kernel exception dispatcher.
348
 * exceptions and their handlers to kernel exception dispatcher.
349
 */
349
 */
350
void exception_init(void)
350
void exception_init(void)
351
{
351
{
352
#ifdef HIGH_EXCEPTION_VECTORS
352
#ifdef HIGH_EXCEPTION_VECTORS
353
    high_vectors();
353
    high_vectors();
354
#endif
354
#endif
355
    install_exception_handlers();
355
    install_exception_handlers();
356
   
356
   
357
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
357
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
358
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
358
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
359
        (iroutine) prefetch_abort);
359
        (iroutine) prefetch_abort);
360
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
360
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
361
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
361
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
362
}
362
}
363
 
363
 
364
/** Prints #istate_t structure content.
364
/** Prints #istate_t structure content.
365
 *
365
 *
366
 * @param istate Structure to be printed.
366
 * @param istate Structure to be printed.
367
 */
367
 */
368
void print_istate(istate_t *istate)
368
void print_istate(istate_t *istate)
369
{
369
{
370
    dprintf("istate dump:\n");
370
    dprintf("istate dump:\n");
371
 
371
 
372
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
372
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
373
        istate->r0, istate->r1, istate->r2, istate->r3);
373
        istate->r0, istate->r1, istate->r2, istate->r3);
374
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
374
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
375
        istate->r4, istate->r5, istate->r6, istate->r7);
375
        istate->r4, istate->r5, istate->r6, istate->r7);
376
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
376
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
377
        istate->r8, istate->r9, istate->r10, istate->r11);
377
        istate->r8, istate->r9, istate->r10, istate->r11);
378
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
378
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
379
        istate->r12, istate->sp, istate->lr, istate->spsr);
379
        istate->r12, istate->sp, istate->lr, istate->spsr);
380
 
380
 
381
    dprintf(" pc: %x\n", istate->pc);
381
    dprintf(" pc: %x\n", istate->pc);
382
}
382
}
383
 
383
 
384
/** @}
384
/** @}
385
 */
385
 */
386
 
386