WebSVN – HelenOS – Diff – /tags/0.4.0/boot/arch/ppc32/loader/asm.S


#
# Copyright (c) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include "asm.h"
#include "regname.h"
 
.macro SMC_COHERENCY addr
	dcbst 0, \addr
	sync
	icbi 0, \addr
	sync
	isync
.endm
 
.macro FLUSH_DCACHE addr
	dcbst 0, \addr
	sync
	isync
.endm
 
.macro TLB_FLUSH reg
	tlbie \reg
	addi \reg, \reg, 0x1000
.endm
 
.text
 
.global halt
.global memcpy
.global jump_to_kernel
 
halt:
	b halt
 
memcpy:
	srwi. r7, r5, 3
	addi r6, r3, -4
	addi r4, r4, -4
	beq	2f
	
	andi. r0, r6, 3
	mtctr r7
	bne 5f
	
	1:
	
	lwz r7, 4(r4)
	lwzu r8, 8(r4)
	stw r7, 4(r6)
	stwu r8, 8(r6)
	bdnz 1b
	
	andi. r5, r5, 7
	
	2:
	
	cmplwi 0, r5, 4
	blt 3f
	
	lwzu r0, 4(r4)
	addi r5, r5, -4
	stwu r0, 4(r6)
	
	3:
	
	cmpwi 0, r5, 0
	beqlr
	mtctr r5
	addi r4, r4, 3
	addi r6, r6, 3
	
	4:
	
	lbzu r0, 1(r4)
	stbu r0, 1(r6)
	bdnz 4b
	blr
	
	5:
	
	subfic r0, r0, 4
	mtctr r0
	
	6:
	
	lbz r7, 4(r4)
	addi r4, r4, 1
	stb r7, 4(r6)
	addi r6, r6, 1
	bdnz 6b
	subf r5, r0, r5
	rlwinm. r7, r5, 32-3, 3, 31
	beq 2b
	mtctr r7
	b 1b
 
 
jump_to_kernel:
	
	# r3 = bootinfo (pa)
	# r4 = bootinfo_size
	# r5 = trans (pa)
	# r6 = bytes to copy
	# r7 = real_mode (pa)
	# r8 = framebuffer (pa)
	# r9 = scanline
	
	# disable interrupts
	
	mfmsr r31
	rlwinm r31, r31, 0, 17, 15
	mtmsr r31
	
	# set real_mode meeting point address
	
	mtspr srr0, r7
	
	# jumps to real_mode
	
	mfmsr r31
	lis r30, ~0@h
	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
	and r31, r31, r30
	mtspr srr1, r31
	
	sync
	isync
	rfi
 
.section REALMODE, "ax"
.align PAGE_WIDTH
.global real_mode
 
real_mode:
	
	# copy kernel to proper location
	#
	# r5 = trans (pa)
	# r6 = bytes to copy
	# r8 = framebuffer (pa)
	# r9 = scanline
	
	li r31, PAGE_SIZE >> 2
	li r30, 0
	
	page_copy:
		
		cmpwi r6, 0
		beq copy_end
		
		# copy page
		
		mtctr r31
		lwz r29, 0(r5)
		
		copy_loop:
			
			lwz r28, 0(r29)
			stw r28, 0(r30)
			
			SMC_COHERENCY r30
			
			addi r29, r29, 4
			addi r30, r30, 4
			subi r6, r6, 4
			
			cmpwi r6, 0
			beq copy_end
			
			bdnz copy_loop
			
		addi r5, r5, 4
		b page_copy
	
	copy_end:
	
	# initially fill segment registers
	
	li r31, 0
	
	li r29, 8
	mtctr r29
	li r30, 0                     # ASID 0 (VSIDs 0 .. 7)
	
	seg_fill_uspace:
	
		mtsrin r30, r31
		addi r30, r30, 1
		addis r31, r31, 0x1000    # move to next SR
		
		bdnz seg_fill_uspace
	
	li r29, 8
	mtctr r29
	lis r30, 0x4000               # priviledged access only
	ori r30, r30, 8               # ASID 0 (VSIDs 8 .. 15)
	
	seg_fill_kernel:
	
		mtsrin r30, r31
		addi r30, r30, 1
		addis r31, r31, 0x1000    # move to next SR
		
		bdnz seg_fill_kernel
	
	# invalidate block address translation registers
	
	li r30, 0
	
	mtspr ibat0u, r30
	mtspr ibat0l, r30
	
	mtspr ibat1u, r30
	mtspr ibat1l, r30
	
	mtspr ibat2u, r30
	mtspr ibat2l, r30
	
	mtspr ibat3u, r30
	mtspr ibat3l, r30
	
	mtspr dbat0u, r30
	mtspr dbat0l, r30
	
	mtspr dbat1u, r30
	mtspr dbat1l, r30
	
	mtspr dbat2u, r30
	mtspr dbat2l, r30
	
	mtspr dbat3u, r30
	mtspr dbat3l, r30
	
	# create empty Page Hash Table
	# on top of memory, size 64 KB
	
	lwz r31, 0(r3)                # r31 = memory size
	
	lis r30, 65536@h
	ori r30, r30, 65536@l         # r30 = 65536
	
	subi r29, r30, 1              # r29 = 65535
	
	sub r31, r31, r30
	andc r31, r31, r29            # pht = ALIGN_DOWN(memory_size - 65536, 65536)
	
	mtsdr1 r31
	
	li r29, 2
	srw r30, r30, r29             # r30 = 16384
	li r29, 0
	
	pht_clear:
		
		# write zeroes
		
		stw r29, 0(r31)
		FLUSH_DCACHE r31
		
		addi r31, r31, 4
		subi r30, r30, 4
		
		cmpwi r30, 0
		beq clear_end
		
		bdnz pht_clear
		
	clear_end:
	
#ifdef CONFIG_BAT
	
	# create BAT identity mapping
	
	lwz r31, 0(r3)                # r31 = memory size
	
	lis r29, 0x0002
	cmpw r31, r29
	blt no_bat                    # less than 128 KB -> no BAT
	
	li r29, 18
	srw r31, r31, r29             # r31 = total >> 18
	
	# create Block Length mask by replicating
	# the leading logical one 14 times
	
	li r29, 14
	mtctr r31
	li r29, 1
	
	bat_mask:
		srw r30, r31, r29         # r30 = mask >> 1
		or r31, r31, r30          # mask = mask | r30
		
		bdnz bat_mask
	
	andi. r31, r31, 0x07ff        # mask = mask & 0x07ff (BAT can map up to 256 MB)
	
	li r29, 2
	slw r31, r31, r29             # mask = mask << 2
	ori r31, r31, 0x0002          # mask = mask | 0x0002 (priviledged access only)
	
	lis r29, 0x8000
	or r29, r29, r31
	
	lis r30, 0x0000
	ori r30, r30, 0x0002
	
	mtspr ibat0u, r29
	mtspr ibat0l, r30
	
	mtspr dbat0u, r29
	mtspr dbat0l, r30
	
	no_bat:
	
#endif
	
	# flush TLB
	
	li r31, 0
	sync
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	TLB_FLUSH r31
	
	eieio
	tlbsync
	sync
	
	# start the kernel
	#
	# pc = KERNEL_START_ADDR
	# r3 = bootinfo (pa)
	# sprg0 = KA2PA(KERNEL_START_ADDR)
	# sprg3 = physical memory size
	# sp = 0 (pa)
	
	lis r31, KERNEL_START_ADDR@ha
	addi r31, r31, KERNEL_START_ADDR@l
	
	mtspr srr0, r31
	
	subis r31, r31, 0x8000
	mtsprg0 r31
	
	lwz r31, 0(r3)
	mtsprg3 r31
	
	li sp, 0
	
	mfmsr r31
	ori r31, r31, (msr_ir | msr_dr)@l
	mtspr srr1, r31
	
	sync
	isync
	rfi
 
.align PAGE_WIDTH
.global trans
trans:
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
 

Rev 3856	Rev 3888
1	#	1	#
2	# Copyright (c) 2006 Martin Decky	2	# Copyright (c) 2006 Martin Decky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include "asm.h"	29	#include "asm.h"
30	#include "regname.h"	30	#include "regname.h"
31		31
32	.macro SMC_COHERENCY addr	32	.macro SMC_COHERENCY addr
33	dcbst 0, \addr	33	dcbst 0, \addr
34	sync	34	sync
35	icbi 0, \addr	35	icbi 0, \addr
36	sync	36	sync
37	isync	37	isync
38	.endm	38	.endm
39		39
40	.macro FLUSH_DCACHE addr	40	.macro FLUSH_DCACHE addr
41	dcbst 0, \addr	41	dcbst 0, \addr
42	sync	42	sync
43	isync	43	isync
44	.endm	44	.endm
45		45
46	.macro TLB_FLUSH reg	46	.macro TLB_FLUSH reg
47	tlbie \reg	47	tlbie \reg
48	addi \reg, \reg, 0x1000	48	addi \reg, \reg, 0x1000
49	.endm	49	.endm
50		50
51	.text	51	.text
52		52
53	.global halt	53	.global halt
54	.global memcpy	54	.global memcpy
55	.global jump_to_kernel	55	.global jump_to_kernel
56		56
57	halt:	57	halt:
58	b halt	58	b halt
59		59
60	memcpy:	60	memcpy:
61	srwi. r7, r5, 3	61	srwi. r7, r5, 3
62	addi r6, r3, -4	62	addi r6, r3, -4
63	addi r4, r4, -4	63	addi r4, r4, -4
64	beq 2f	64	beq 2f
65		65
66	andi. r0, r6, 3	66	andi. r0, r6, 3
67	mtctr r7	67	mtctr r7
68	bne 5f	68	bne 5f
69		69
70	1:	70	1:
71		71
72	lwz r7, 4(r4)	72	lwz r7, 4(r4)
73	lwzu r8, 8(r4)	73	lwzu r8, 8(r4)
74	stw r7, 4(r6)	74	stw r7, 4(r6)
75	stwu r8, 8(r6)	75	stwu r8, 8(r6)
76	bdnz 1b	76	bdnz 1b
77		77
78	andi. r5, r5, 7	78	andi. r5, r5, 7
79		79
80	2:	80	2:
81		81
82	cmplwi 0, r5, 4	82	cmplwi 0, r5, 4
83	blt 3f	83	blt 3f
84		84
85	lwzu r0, 4(r4)	85	lwzu r0, 4(r4)
86	addi r5, r5, -4	86	addi r5, r5, -4
87	stwu r0, 4(r6)	87	stwu r0, 4(r6)
88		88
89	3:	89	3:
90		90
91	cmpwi 0, r5, 0	91	cmpwi 0, r5, 0
92	beqlr	92	beqlr
93	mtctr r5	93	mtctr r5
94	addi r4, r4, 3	94	addi r4, r4, 3
95	addi r6, r6, 3	95	addi r6, r6, 3
96		96
97	4:	97	4:
98		98
99	lbzu r0, 1(r4)	99	lbzu r0, 1(r4)
100	stbu r0, 1(r6)	100	stbu r0, 1(r6)
101	bdnz 4b	101	bdnz 4b
102	blr	102	blr
103		103
104	5:	104	5:
105		105
106	subfic r0, r0, 4	106	subfic r0, r0, 4
107	mtctr r0	107	mtctr r0
108		108
109	6:	109	6:
110		110
111	lbz r7, 4(r4)	111	lbz r7, 4(r4)
112	addi r4, r4, 1	112	addi r4, r4, 1
113	stb r7, 4(r6)	113	stb r7, 4(r6)
114	addi r6, r6, 1	114	addi r6, r6, 1
115	bdnz 6b	115	bdnz 6b
116	subf r5, r0, r5	116	subf r5, r0, r5
117	rlwinm. r7, r5, 32-3, 3, 31	117	rlwinm. r7, r5, 32-3, 3, 31
118	beq 2b	118	beq 2b
119	mtctr r7	119	mtctr r7
120	b 1b	120	b 1b
121		121
122		122
123	jump_to_kernel:	123	jump_to_kernel:
124		124
125	# r3 = bootinfo (pa)	125	# r3 = bootinfo (pa)
126	# r4 = bootinfo_size	126	# r4 = bootinfo_size
127	# r5 = trans (pa)	127	# r5 = trans (pa)
128	# r6 = bytes to copy	128	# r6 = bytes to copy
129	# r7 = real_mode (pa)	129	# r7 = real_mode (pa)
130	# r8 = framebuffer (pa)	130	# r8 = framebuffer (pa)
131	# r9 = scanline	131	# r9 = scanline
132		132
133	# disable interrupts	133	# disable interrupts
134		134
135	mfmsr r31	135	mfmsr r31
136	rlwinm r31, r31, 0, 17, 15	136	rlwinm r31, r31, 0, 17, 15
137	mtmsr r31	137	mtmsr r31
138		138
139	# set real_mode meeting point address	139	# set real_mode meeting point address
140		140
141	mtspr srr0, r7	141	mtspr srr0, r7
142		142
143	# jumps to real_mode	143	# jumps to real_mode
144		144
145	mfmsr r31	145	mfmsr r31
146	lis r30, ~0@h	146	lis r30, ~0@h
147	ori r30, r30, ~(msr_ir \| msr_dr \| msr_ee)@l	147	ori r30, r30, ~(msr_ir \| msr_dr \| msr_ee)@l
148	and r31, r31, r30	148	and r31, r31, r30
149	mtspr srr1, r31	149	mtspr srr1, r31
150		150
151	sync	151	sync
152	isync	152	isync
153	rfi	153	rfi
154		154
155	.section REALMODE, "ax"	155	.section REALMODE, "ax"
156	.align PAGE_WIDTH	156	.align PAGE_WIDTH
157	.global real_mode	157	.global real_mode
158		158
159	real_mode:	159	real_mode:
160		160
161	# copy kernel to proper location	161	# copy kernel to proper location
162	#	162	#
163	# r5 = trans (pa)	163	# r5 = trans (pa)
164	# r6 = bytes to copy	164	# r6 = bytes to copy
165	# r8 = framebuffer (pa)	165	# r8 = framebuffer (pa)
166	# r9 = scanline	166	# r9 = scanline
167		167
168	li r31, PAGE_SIZE >> 2	168	li r31, PAGE_SIZE >> 2
169	li r30, 0	169	li r30, 0
170		170
171	page_copy:	171	page_copy:
172		172
173	cmpwi r6, 0	173	cmpwi r6, 0
174	beq copy_end	174	beq copy_end
175		175
176	# copy page	176	# copy page
177		177
178	mtctr r31	178	mtctr r31
179	lwz r29, 0(r5)	179	lwz r29, 0(r5)
180		180
181	copy_loop:	181	copy_loop:
182		182
183	lwz r28, 0(r29)	183	lwz r28, 0(r29)
184	stw r28, 0(r30)	184	stw r28, 0(r30)
185		185
186	SMC_COHERENCY r30	186	SMC_COHERENCY r30
187		187
188	addi r29, r29, 4	188	addi r29, r29, 4
189	addi r30, r30, 4	189	addi r30, r30, 4
190	subi r6, r6, 4	190	subi r6, r6, 4
191		191
192	cmpwi r6, 0	192	cmpwi r6, 0
193	beq copy_end	193	beq copy_end
194		194
195	bdnz copy_loop	195	bdnz copy_loop
196		196
197	addi r5, r5, 4	197	addi r5, r5, 4
198	b page_copy	198	b page_copy
199		199
200	copy_end:	200	copy_end:
201		201
202	# initially fill segment registers	202	# initially fill segment registers
203		203
204	li r31, 0	204	li r31, 0
205		205
206	li r29, 8	206	li r29, 8
207	mtctr r29	207	mtctr r29
208	li r30, 0 # ASID 0 (VSIDs 0 .. 7)	208	li r30, 0 # ASID 0 (VSIDs 0 .. 7)
209		209
210	seg_fill_uspace:	210	seg_fill_uspace:
211		211
212	mtsrin r30, r31	212	mtsrin r30, r31
213	addi r30, r30, 1	213	addi r30, r30, 1
214	addis r31, r31, 0x1000 # move to next SR	214	addis r31, r31, 0x1000 # move to next SR
215		215
216	bdnz seg_fill_uspace	216	bdnz seg_fill_uspace
217		217
218	li r29, 8	218	li r29, 8
219	mtctr r29	219	mtctr r29
220	lis r30, 0x4000 # priviledged access only	220	lis r30, 0x4000 # priviledged access only
221	ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)	221	ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15)
222		222
223	seg_fill_kernel:	223	seg_fill_kernel:
224		224
225	mtsrin r30, r31	225	mtsrin r30, r31
226	addi r30, r30, 1	226	addi r30, r30, 1
227	addis r31, r31, 0x1000 # move to next SR	227	addis r31, r31, 0x1000 # move to next SR
228		228
229	bdnz seg_fill_kernel	229	bdnz seg_fill_kernel
230		230
231	# invalidate block address translation registers	231	# invalidate block address translation registers
232		232
233	li r30, 0	233	li r30, 0
234		234
235	mtspr ibat0u, r30	235	mtspr ibat0u, r30
236	mtspr ibat0l, r30	236	mtspr ibat0l, r30
237		237
238	mtspr ibat1u, r30	238	mtspr ibat1u, r30
239	mtspr ibat1l, r30	239	mtspr ibat1l, r30
240		240
241	mtspr ibat2u, r30	241	mtspr ibat2u, r30
242	mtspr ibat2l, r30	242	mtspr ibat2l, r30
243		243
244	mtspr ibat3u, r30	244	mtspr ibat3u, r30
245	mtspr ibat3l, r30	245	mtspr ibat3l, r30
246		246
247	mtspr dbat0u, r30	247	mtspr dbat0u, r30
248	mtspr dbat0l, r30	248	mtspr dbat0l, r30
249		249
250	mtspr dbat1u, r30	250	mtspr dbat1u, r30
251	mtspr dbat1l, r30	251	mtspr dbat1l, r30
252		252
253	mtspr dbat2u, r30	253	mtspr dbat2u, r30
254	mtspr dbat2l, r30	254	mtspr dbat2l, r30
255		255
256	mtspr dbat3u, r30	256	mtspr dbat3u, r30
257	mtspr dbat3l, r30	257	mtspr dbat3l, r30
258		258
259	# create empty Page Hash Table	259	# create empty Page Hash Table
260	# on top of memory, size 64 KB	260	# on top of memory, size 64 KB
261		261
262	lwz r31, 0(r3) # r31 = memory size	262	lwz r31, 0(r3) # r31 = memory size
263		263
264	lis r30, 65536@h	264	lis r30, 65536@h
265	ori r30, r30, 65536@l # r30 = 65536	265	ori r30, r30, 65536@l # r30 = 65536
266		266
267	subi r29, r30, 1 # r29 = 65535	267	subi r29, r30, 1 # r29 = 65535
268		268
269	sub r31, r31, r30	269	sub r31, r31, r30
270	andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)	270	andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536)
271		271
272	mtsdr1 r31	272	mtsdr1 r31
273		273
274	li r29, 2	274	li r29, 2
275	srw r30, r30, r29 # r30 = 16384	275	srw r30, r30, r29 # r30 = 16384
276	li r29, 0	276	li r29, 0
277		277
278	pht_clear:	278	pht_clear:
279		279
280	# write zeroes	280	# write zeroes
281		281
282	stw r29, 0(r31)	282	stw r29, 0(r31)
283	FLUSH_DCACHE r31	283	FLUSH_DCACHE r31
284		284
285	addi r31, r31, 4	285	addi r31, r31, 4
286	subi r30, r30, 4	286	subi r30, r30, 4
287		287
288	cmpwi r30, 0	288	cmpwi r30, 0
289	beq clear_end	289	beq clear_end
290		290
291	bdnz pht_clear	291	bdnz pht_clear
292		292
293	clear_end:	293	clear_end:
294		294
295	#ifdef CONFIG_BAT	295	#ifdef CONFIG_BAT
296		296
297	# create BAT identity mapping	297	# create BAT identity mapping
298		298
299	lwz r31, 0(r3) # r31 = memory size	299	lwz r31, 0(r3) # r31 = memory size
300		300
301	lis r29, 0x0002	301	lis r29, 0x0002
302	cmpw r31, r29	302	cmpw r31, r29
303	blt no_bat # less than 128 KB -> no BAT	303	blt no_bat # less than 128 KB -> no BAT
304		304
305	li r29, 18	305	li r29, 18
306	srw r31, r31, r29 # r31 = total >> 18	306	srw r31, r31, r29 # r31 = total >> 18
307		307
308	# create Block Length mask by replicating	308	# create Block Length mask by replicating
309	# the leading logical one 14 times	309	# the leading logical one 14 times
310		310
311	li r29, 14	311	li r29, 14
312	mtctr r31	312	mtctr r31
313	li r29, 1	313	li r29, 1
314		314
315	bat_mask:	315	bat_mask:
316	srw r30, r31, r29 # r30 = mask >> 1	316	srw r30, r31, r29 # r30 = mask >> 1
317	or r31, r31, r30 # mask = mask \| r30	317	or r31, r31, r30 # mask = mask \| r30
318		318
319	bdnz bat_mask	319	bdnz bat_mask
320		320
321	andi. r31, r31, 0x07ff # mask = mask & 0x07ff (BAT can map up to 256 MB)	321	andi. r31, r31, 0x07ff # mask = mask & 0x07ff (BAT can map up to 256 MB)
322		322
323	li r29, 2	323	li r29, 2
324	slw r31, r31, r29 # mask = mask << 2	324	slw r31, r31, r29 # mask = mask << 2
325	ori r31, r31, 0x0002 # mask = mask \| 0x0002 (priviledged access only)	325	ori r31, r31, 0x0002 # mask = mask \| 0x0002 (priviledged access only)
326		326
327	lis r29, 0x8000	327	lis r29, 0x8000
328	or r29, r29, r31	328	or r29, r29, r31
329		329
330	lis r30, 0x0000	330	lis r30, 0x0000
331	ori r30, r30, 0x0002	331	ori r30, r30, 0x0002
332		332
333	mtspr ibat0u, r29	333	mtspr ibat0u, r29
334	mtspr ibat0l, r30	334	mtspr ibat0l, r30
335		335
336	mtspr dbat0u, r29	336	mtspr dbat0u, r29
337	mtspr dbat0l, r30	337	mtspr dbat0l, r30
338		338
339	no_bat:	339	no_bat:
340		340
341	#endif	341	#endif
342		342
343	# flush TLB	343	# flush TLB
344		344
345	li r31, 0	345	li r31, 0
346	sync	346	sync
347		347
348	TLB_FLUSH r31	348	TLB_FLUSH r31
349	TLB_FLUSH r31	349	TLB_FLUSH r31
350	TLB_FLUSH r31	350	TLB_FLUSH r31
351	TLB_FLUSH r31	351	TLB_FLUSH r31
352	TLB_FLUSH r31	352	TLB_FLUSH r31
353	TLB_FLUSH r31	353	TLB_FLUSH r31
354	TLB_FLUSH r31	354	TLB_FLUSH r31
355	TLB_FLUSH r31	355	TLB_FLUSH r31
356		356
357	TLB_FLUSH r31	357	TLB_FLUSH r31
358	TLB_FLUSH r31	358	TLB_FLUSH r31
359	TLB_FLUSH r31	359	TLB_FLUSH r31
360	TLB_FLUSH r31	360	TLB_FLUSH r31
361	TLB_FLUSH r31	361	TLB_FLUSH r31
362	TLB_FLUSH r31	362	TLB_FLUSH r31
363	TLB_FLUSH r31	363	TLB_FLUSH r31
364	TLB_FLUSH r31	364	TLB_FLUSH r31
365		365
366	TLB_FLUSH r31	366	TLB_FLUSH r31
367	TLB_FLUSH r31	367	TLB_FLUSH r31
368	TLB_FLUSH r31	368	TLB_FLUSH r31
369	TLB_FLUSH r31	369	TLB_FLUSH r31
370	TLB_FLUSH r31	370	TLB_FLUSH r31
371	TLB_FLUSH r31	371	TLB_FLUSH r31
372	TLB_FLUSH r31	372	TLB_FLUSH r31
373	TLB_FLUSH r31	373	TLB_FLUSH r31
374		374
375	TLB_FLUSH r31	375	TLB_FLUSH r31
376	TLB_FLUSH r31	376	TLB_FLUSH r31
377	TLB_FLUSH r31	377	TLB_FLUSH r31
378	TLB_FLUSH r31	378	TLB_FLUSH r31
379	TLB_FLUSH r31	379	TLB_FLUSH r31
380	TLB_FLUSH r31	380	TLB_FLUSH r31
381	TLB_FLUSH r31	381	TLB_FLUSH r31
382	TLB_FLUSH r31	382	TLB_FLUSH r31
383		383
384	TLB_FLUSH r31	384	TLB_FLUSH r31
385	TLB_FLUSH r31	385	TLB_FLUSH r31
386	TLB_FLUSH r31	386	TLB_FLUSH r31
387	TLB_FLUSH r31	387	TLB_FLUSH r31
388	TLB_FLUSH r31	388	TLB_FLUSH r31
389	TLB_FLUSH r31	389	TLB_FLUSH r31
390	TLB_FLUSH r31	390	TLB_FLUSH r31
391	TLB_FLUSH r31	391	TLB_FLUSH r31
392		392
393	TLB_FLUSH r31	393	TLB_FLUSH r31
394	TLB_FLUSH r31	394	TLB_FLUSH r31
395	TLB_FLUSH r31	395	TLB_FLUSH r31
396	TLB_FLUSH r31	396	TLB_FLUSH r31
397	TLB_FLUSH r31	397	TLB_FLUSH r31
398	TLB_FLUSH r31	398	TLB_FLUSH r31
399	TLB_FLUSH r31	399	TLB_FLUSH r31
400	TLB_FLUSH r31	400	TLB_FLUSH r31
401		401
402	TLB_FLUSH r31	402	TLB_FLUSH r31
403	TLB_FLUSH r31	403	TLB_FLUSH r31
404	TLB_FLUSH r31	404	TLB_FLUSH r31
405	TLB_FLUSH r31	405	TLB_FLUSH r31
406	TLB_FLUSH r31	406	TLB_FLUSH r31
407	TLB_FLUSH r31	407	TLB_FLUSH r31
408	TLB_FLUSH r31	408	TLB_FLUSH r31
409	TLB_FLUSH r31	409	TLB_FLUSH r31
410		410
411	TLB_FLUSH r31	411	TLB_FLUSH r31
412	TLB_FLUSH r31	412	TLB_FLUSH r31
413	TLB_FLUSH r31	413	TLB_FLUSH r31
414	TLB_FLUSH r31	414	TLB_FLUSH r31
415	TLB_FLUSH r31	415	TLB_FLUSH r31
416	TLB_FLUSH r31	416	TLB_FLUSH r31
417	TLB_FLUSH r31	417	TLB_FLUSH r31
418	TLB_FLUSH r31	418	TLB_FLUSH r31
419		419
420	eieio	420	eieio
421	tlbsync	421	tlbsync
422	sync	422	sync
423		423
424	# start the kernel	424	# start the kernel
425	#	425	#
426	# pc = KERNEL_START_ADDR	426	# pc = KERNEL_START_ADDR
427	# r3 = bootinfo (pa)	427	# r3 = bootinfo (pa)
428	# sprg0 = KA2PA(KERNEL_START_ADDR)	428	# sprg0 = KA2PA(KERNEL_START_ADDR)
429	# sprg3 = physical memory size	429	# sprg3 = physical memory size
430	# sp = 0 (pa)	430	# sp = 0 (pa)
431		431
432	lis r31, KERNEL_START_ADDR@ha	432	lis r31, KERNEL_START_ADDR@ha
433	addi r31, r31, KERNEL_START_ADDR@l	433	addi r31, r31, KERNEL_START_ADDR@l
434		434
435	mtspr srr0, r31	435	mtspr srr0, r31
436		436
437	subis r31, r31, 0x8000	437	subis r31, r31, 0x8000
438	mtsprg0 r31	438	mtsprg0 r31
439		439
440	lwz r31, 0(r3)	440	lwz r31, 0(r3)
441	mtsprg3 r31	441	mtsprg3 r31
442		442
443	li sp, 0	443	li sp, 0
444		444
445	mfmsr r31	445	mfmsr r31
446	ori r31, r31, (msr_ir \| msr_dr)@l	446	ori r31, r31, (msr_ir \| msr_dr)@l
447	mtspr srr1, r31	447	mtspr srr1, r31
448		448
449	sync	449	sync
450	isync	450	isync
451	rfi	451	rfi
452		452
453	.align PAGE_WIDTH	453	.align PAGE_WIDTH
454	.global trans	454	.global trans
455	trans:	455	trans:
456	.space (TRANS_SIZE * TRANS_ITEM_SIZE)	456	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
457		457

Subversion Repositories HelenOS

(root)/tags/0.4.0/boot/arch/ppc32/loader/asm.S – Rev 3856 → 3888