WebSVN – HelenOS – Diff – /tags/0.2.0.4/kernel/arch/sparc64/include/drivers/z8530.h


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_Z8530_H_
#define KERN_sparc64_Z8530_H_
 
#include <arch/types.h>
#include <arch/drivers/kbd.h>
 
#define Z8530_CHAN_A    4
#define Z8530_CHAN_B    0
 
#define WR0 0
#define WR1 1
#define WR2 2
#define WR3 3
#define WR4 4
#define WR5 5
#define WR6 6
#define WR7 7
#define WR8 8
#define WR9 9
#define WR10    10
#define WR11    11
#define WR12    12
#define WR13    13
#define WR14    14
#define WR15    15
 
#define RR0 0
#define RR1 1
#define RR2 2
#define RR3 3
#define RR8 8
#define RR10    10
#define RR12    12
#define RR13    13
#define RR14    14
#define RR15    15
 
/* Write Register 0 */
#define WR0_TX_IP_RST   (0x5<<3)    /** Reset pending TX interrupt. */
#define WR0_ERR_RST (0x6<<3)
 
/* Write Register 1 */
#define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
#define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
#define WR1_IARCSC  (0x2<<3)    /** Interrupt on All Receive Characters or Special Conditions. */
#define WR1_RISC    (0x3<<3)    /** Receive Interrupt on Special Condition. */
#define WR1_PISC    (0x1<<2)    /** Parity Is Special Condition. */
 
/* Write Register 3 */
#define WR3_RX_ENABLE   (0x1<<0)    /** Rx Enable. */
#define WR3_RX8BITSCH   (0x3<<6)    /** 8-bits per character. */
 
/* Write Register 9 */
#define WR9_MIE     (0x1<<3)    /** Master Interrupt Enable. */
 
/* Read Register 0 */
#define RR0_RCA     (0x1<<0)    /** Receive Character Available. */
 
/** Structure representing the z8530 device. */
typedef struct {
    devno_t devno;
    volatile uint8_t *reg;      /** Memory mapped registers of the z8530. */
} z8530_t;
 
static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val)
{
    /*
     * Registers 8-15 will automatically issue the Point High
     * command as their bit 3 is 1.
     */
    dev->reg[WR0+chan] = reg;   /* select register */
    dev->reg[WR0+chan] = val;   /* write value */
}
 
static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val)
{
    z8530_write(dev, Z8530_CHAN_A, reg, val);
}
static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val)
{
    z8530_write(dev, Z8530_CHAN_B, reg, val);
}
 
static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg)
{
    /*
     * Registers 8-15 will automatically issue the Point High
     * command as their bit 3 is 1.
     */
    dev->reg[WR0+chan] = reg;   /* select register */
    return dev->reg[WR0+chan];
}
 
static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg)
{
    return z8530_read(dev, Z8530_CHAN_A, reg);
}
static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg)
{
    return z8530_read(dev, Z8530_CHAN_B, reg);
}
 
#endif
 
/** @}
 */
 

Rev 2089	Rev 2130
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_Z8530_H_	35	#ifndef KERN_sparc64_Z8530_H_
36	#define KERN_sparc64_Z8530_H_	36	#define KERN_sparc64_Z8530_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
39	#include <arch/drivers/kbd.h>	39	#include <arch/drivers/kbd.h>
40		40
41	#define Z8530_CHAN_A 4	41	#define Z8530_CHAN_A 4
42	#define Z8530_CHAN_B 0	42	#define Z8530_CHAN_B 0
43		43
44	#define WR0 0	44	#define WR0 0
45	#define WR1 1	45	#define WR1 1
46	#define WR2 2	46	#define WR2 2
47	#define WR3 3	47	#define WR3 3
48	#define WR4 4	48	#define WR4 4
49	#define WR5 5	49	#define WR5 5
50	#define WR6 6	50	#define WR6 6
51	#define WR7 7	51	#define WR7 7
52	#define WR8 8	52	#define WR8 8
53	#define WR9 9	53	#define WR9 9
54	#define WR10 10	54	#define WR10 10
55	#define WR11 11	55	#define WR11 11
56	#define WR12 12	56	#define WR12 12
57	#define WR13 13	57	#define WR13 13
58	#define WR14 14	58	#define WR14 14
59	#define WR15 15	59	#define WR15 15
60		60
61	#define RR0 0	61	#define RR0 0
62	#define RR1 1	62	#define RR1 1
63	#define RR2 2	63	#define RR2 2
64	#define RR3 3	64	#define RR3 3
65	#define RR8 8	65	#define RR8 8
66	#define RR10 10	66	#define RR10 10
67	#define RR12 12	67	#define RR12 12
68	#define RR13 13	68	#define RR13 13
69	#define RR14 14	69	#define RR14 14
70	#define RR15 15	70	#define RR15 15
71		71
72	/* Write Register 0 */	72	/* Write Register 0 */
73	#define WR0_TX_IP_RST (0x5<<3) /** Reset pending TX interrupt. */	73	#define WR0_TX_IP_RST (0x5<<3) /** Reset pending TX interrupt. */
74	#define WR0_ERR_RST (0x6<<3)	74	#define WR0_ERR_RST (0x6<<3)
75		75
76	/* Write Register 1 */	76	/* Write Register 1 */
77	#define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */	77	#define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */
78	#define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */	78	#define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */
79	#define WR1_IARCSC (0x2<<3) /** Interrupt on All Receive Characters or Special Conditions. */	79	#define WR1_IARCSC (0x2<<3) /** Interrupt on All Receive Characters or Special Conditions. */
80	#define WR1_RISC (0x3<<3) /** Receive Interrupt on Special Condition. */	80	#define WR1_RISC (0x3<<3) /** Receive Interrupt on Special Condition. */
81	#define WR1_PISC (0x1<<2) /** Parity Is Special Condition. */	81	#define WR1_PISC (0x1<<2) /** Parity Is Special Condition. */
82		82
83	/* Write Register 3 */	83	/* Write Register 3 */
84	#define WR3_RX_ENABLE (0x1<<0) /** Rx Enable. */	84	#define WR3_RX_ENABLE (0x1<<0) /** Rx Enable. */
85	#define WR3_RX8BITSCH (0x3<<6) /** 8-bits per character. */	85	#define WR3_RX8BITSCH (0x3<<6) /** 8-bits per character. */
86		86
87	/* Write Register 9 */	87	/* Write Register 9 */
88	#define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */	88	#define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */
89		89
90	/* Read Register 0 */	90	/* Read Register 0 */
91	#define RR0_RCA (0x1<<0) /** Receive Character Available. */	91	#define RR0_RCA (0x1<<0) /** Receive Character Available. */
92		92
93	/** Structure representing the z8530 device. */	93	/** Structure representing the z8530 device. */
94	typedef struct {	94	typedef struct {
95	devno_t devno;	95	devno_t devno;
96	volatile uint8_t reg; /* Memory mapped registers of the z8530. */	96	volatile uint8_t reg; /* Memory mapped registers of the z8530. */
97	} z8530_t;	97	} z8530_t;
98		98
99	static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val)	99	static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val)
100	{	100	{
101	/*	101	/*
102	* Registers 8-15 will automatically issue the Point High	102	* Registers 8-15 will automatically issue the Point High
103	* command as their bit 3 is 1.	103	* command as their bit 3 is 1.
104	*/	104	*/
105	dev->reg[WR0+chan] = reg; /* select register */	105	dev->reg[WR0+chan] = reg; /* select register */
106	dev->reg[WR0+chan] = val; /* write value */	106	dev->reg[WR0+chan] = val; /* write value */
107	}	107	}
108		108
109	static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val)	109	static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val)
110	{	110	{
111	z8530_write(dev, Z8530_CHAN_A, reg, val);	111	z8530_write(dev, Z8530_CHAN_A, reg, val);
112	}	112	}
113	static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val)	113	static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val)
114	{	114	{
115	z8530_write(dev, Z8530_CHAN_B, reg, val);	115	z8530_write(dev, Z8530_CHAN_B, reg, val);
116	}	116	}
117		117
118	static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg)	118	static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg)
119	{	119	{
120	/*	120	/*
121	* Registers 8-15 will automatically issue the Point High	121	* Registers 8-15 will automatically issue the Point High
122	* command as their bit 3 is 1.	122	* command as their bit 3 is 1.
123	*/	123	*/
124	dev->reg[WR0+chan] = reg; /* select register */	124	dev->reg[WR0+chan] = reg; /* select register */
125	return dev->reg[WR0+chan];	125	return dev->reg[WR0+chan];
126	}	126	}
127		127
128	static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg)	128	static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg)
129	{	129	{
130	return z8530_read(dev, Z8530_CHAN_A, reg);	130	return z8530_read(dev, Z8530_CHAN_A, reg);
131	}	131	}
132	static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg)	132	static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg)
133	{	133	{
134	return z8530_read(dev, Z8530_CHAN_B, reg);	134	return z8530_read(dev, Z8530_CHAN_B, reg);
135	}	135	}
136		136
137	#endif	137	#endif
138		138
139	/** @}	139	/** @}
140	*/	140	*/
141		141

Subversion Repositories HelenOS

(root)/tags/0.2.0.4/kernel/arch/sparc64/include/drivers/z8530.h – Rev 2089 → 2130