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1
/*
1
/*
2
 * Copyright (C) 2001-2004 Jakub Jermar
2
 * Copyright (C) 2001-2004 Jakub Jermar
3
 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
#include <arch/types.h>
29
#include <arch/types.h>
30
#include <arch/smp/apic.h>
30
#include <arch/smp/apic.h>
31
#include <arch/smp/ap.h>
31
#include <arch/smp/ap.h>
32
#include <arch/smp/mps.h>
32
#include <arch/smp/mps.h>
33
#include <arch/boot/boot.h>
33
#include <arch/boot/boot.h>
34
#include <mm/page.h>
34
#include <mm/page.h>
35
#include <time/delay.h>
35
#include <time/delay.h>
36
#include <interrupt.h>
36
#include <interrupt.h>
37
#include <arch/interrupt.h>
37
#include <arch/interrupt.h>
38
#include <print.h>
38
#include <print.h>
39
#include <arch/asm.h>
39
#include <arch/asm.h>
40
#include <arch.h>
40
#include <arch.h>
41
 
41
 
42
#ifdef CONFIG_SMP
42
#ifdef CONFIG_SMP
43
 
43
 
44
/*
44
/*
45
 * Advanced Programmable Interrupt Controller for SMP systems.
45
 * Advanced Programmable Interrupt Controller for SMP systems.
46
 * Tested on:
46
 * Tested on:
47
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
47
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
48
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
48
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
49
 *  VMware Workstation 5.5 with 2 CPUs
49
 *  VMware Workstation 5.5 with 2 CPUs
50
 *  QEMU 0.8.0 with 2-15 CPUs
50
 *  QEMU 0.8.0 with 2-15 CPUs
51
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
51
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
52
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
52
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
53
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
53
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
54
 */
54
 */
55
 
55
 
56
/*
56
/*
57
 * These variables either stay configured as initilalized, or are changed by
57
 * These variables either stay configured as initilalized, or are changed by
58
 * the MP configuration code.
58
 * the MP configuration code.
59
 *
59
 *
60
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
60
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
61
 * optimize the code too much and accesses to l_apic and io_apic, that must
61
 * optimize the code too much and accesses to l_apic and io_apic, that must
62
 * always be 32-bit, would use byte oriented instructions.
62
 * always be 32-bit, would use byte oriented instructions.
63
 */
63
 */
64
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
64
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
65
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
65
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
66
 
66
 
67
__u32 apic_id_mask = 0;
67
__u32 apic_id_mask = 0;
68
 
68
 
69
static int apic_poll_errors(void);
69
static int apic_poll_errors(void);
70
 
70
 
71
#ifdef LAPIC_VERBOSE
71
#ifdef LAPIC_VERBOSE
72
static char *delmod_str[] = {
72
static char *delmod_str[] = {
73
    "Fixed",
73
    "Fixed",
74
    "Lowest Priority",
74
    "Lowest Priority",
75
    "SMI",
75
    "SMI",
76
    "Reserved",
76
    "Reserved",
77
    "NMI",
77
    "NMI",
78
    "INIT",
78
    "INIT",
79
    "STARTUP",
79
    "STARTUP",
80
    "ExtInt"
80
    "ExtInt"
81
};
81
};
82
 
82
 
83
static char *destmod_str[] = {
83
static char *destmod_str[] = {
84
    "Physical",
84
    "Physical",
85
    "Logical"
85
    "Logical"
86
};
86
};
87
 
87
 
88
static char *trigmod_str[] = {
88
static char *trigmod_str[] = {
89
    "Edge",
89
    "Edge",
90
    "Level"
90
    "Level"
91
};
91
};
92
 
92
 
93
static char *mask_str[] = {
93
static char *mask_str[] = {
94
    "Unmasked",
94
    "Unmasked",
95
    "Masked"
95
    "Masked"
96
};
96
};
97
 
97
 
98
static char *delivs_str[] = {
98
static char *delivs_str[] = {
99
    "Idle",
99
    "Idle",
100
    "Send Pending"
100
    "Send Pending"
101
};
101
};
102
 
102
 
103
static char *tm_mode_str[] = {
103
static char *tm_mode_str[] = {
104
    "One-shot",
104
    "One-shot",
105
    "Periodic"
105
    "Periodic"
106
};
106
};
107
 
107
 
108
static char *intpol_str[] = {
108
static char *intpol_str[] = {
109
    "Polarity High",
109
    "Polarity High",
110
    "Polarity Low"
110
    "Polarity Low"
111
};
111
};
112
#endif /* LAPIC_VERBOSE */
112
#endif /* LAPIC_VERBOSE */
113
 
113
 
114
 
114
 
115
static void apic_spurious(int n, istate_t *istate);
115
static void apic_spurious(int n, istate_t *istate);
116
static void l_apic_timer_interrupt(int n, istate_t *istate);
116
static void l_apic_timer_interrupt(int n, istate_t *istate);
117
 
117
 
118
/** Initialize APIC on BSP. */
118
/** Initialize APIC on BSP. */
119
void apic_init(void)
119
void apic_init(void)
120
{
120
{
121
    io_apic_id_t idreg;
121
    io_apic_id_t idreg;
122
    int i;
122
    int i;
123
 
123
 
124
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
124
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
125
 
125
 
126
    enable_irqs_function = io_apic_enable_irqs;
126
    enable_irqs_function = io_apic_enable_irqs;
127
    disable_irqs_function = io_apic_disable_irqs;
127
    disable_irqs_function = io_apic_disable_irqs;
128
    eoi_function = l_apic_eoi;
128
    eoi_function = l_apic_eoi;
129
   
129
   
130
    /*
130
    /*
131
     * Configure interrupt routing.
131
     * Configure interrupt routing.
132
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
132
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
133
     * Other interrupts will be forwarded to the lowest priority CPU.
133
     * Other interrupts will be forwarded to the lowest priority CPU.
134
     */
134
     */
135
    io_apic_disable_irqs(0xffff);
135
    io_apic_disable_irqs(0xffff);
136
    exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
136
    exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
137
    for (i = 0; i < IRQ_COUNT; i++) {
137
    for (i = 0; i < IRQ_COUNT; i++) {
138
        int pin;
138
        int pin;
139
   
139
   
140
        if ((pin = smp_irq_to_pin(i)) != -1) {
140
        if ((pin = smp_irq_to_pin(i)) != -1) {
141
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
141
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
142
        }
142
        }
143
    }
143
    }
144
   
144
   
145
    /*
145
    /*
146
     * Ensure that io_apic has unique ID.
146
     * Ensure that io_apic has unique ID.
147
     */
147
     */
148
    idreg.value = io_apic_read(IOAPICID);
148
    idreg.value = io_apic_read(IOAPICID);
149
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
149
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
150
        for (i = 0; i < APIC_ID_COUNT; i++) {
150
        for (i = 0; i < APIC_ID_COUNT; i++) {
151
            if (!((1<<i) & apic_id_mask)) {
151
            if (!((1<<i) & apic_id_mask)) {
152
                idreg.apic_id = i;
152
                idreg.apic_id = i;
153
                io_apic_write(IOAPICID, idreg.value);
153
                io_apic_write(IOAPICID, idreg.value);
154
                break;
154
                break;
155
            }
155
            }
156
        }
156
        }
157
    }
157
    }
158
 
158
 
159
    /*
159
    /*
160
     * Configure the BSP's lapic.
160
     * Configure the BSP's lapic.
161
     */
161
     */
162
    l_apic_init();
162
    l_apic_init();
163
 
163
 
164
    l_apic_debug();
164
    l_apic_debug();
165
}
165
}
166
 
166
 
167
/** APIC spurious interrupt handler.
167
/** APIC spurious interrupt handler.
168
 *
168
 *
169
 * @param n Interrupt vector.
169
 * @param n Interrupt vector.
170
 * @param stack Interrupted stack.
170
 * @param stack Interrupted stack.
171
 */
171
 */
172
void apic_spurious(int n, istate_t *istate)
172
void apic_spurious(int n, istate_t *istate)
173
{
173
{
174
#ifdef CONFIG_DEBUG
174
#ifdef CONFIG_DEBUG
175
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
175
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
176
#endif
176
#endif
177
}
177
}
178
 
178
 
179
/** Poll for APIC errors.
179
/** Poll for APIC errors.
180
 *
180
 *
181
 * Examine Error Status Register and report all errors found.
181
 * Examine Error Status Register and report all errors found.
182
 *
182
 *
183
 * @return 0 on error, 1 on success.
183
 * @return 0 on error, 1 on success.
184
 */
184
 */
185
int apic_poll_errors(void)
185
int apic_poll_errors(void)
186
{
186
{
187
    esr_t esr;
187
    esr_t esr;
188
   
188
   
189
    esr.value = l_apic[ESR];
189
    esr.value = l_apic[ESR];
190
   
190
   
191
    if (esr.send_checksum_error)
191
    if (esr.send_checksum_error)
192
        printf("Send Checksum Error\n");
192
        printf("Send Checksum Error\n");
193
    if (esr.receive_checksum_error)
193
    if (esr.receive_checksum_error)
194
        printf("Receive Checksum Error\n");
194
        printf("Receive Checksum Error\n");
195
    if (esr.send_accept_error)
195
    if (esr.send_accept_error)
196
        printf("Send Accept Error\n");
196
        printf("Send Accept Error\n");
197
    if (esr.receive_accept_error)
197
    if (esr.receive_accept_error)
198
        printf("Receive Accept Error\n");
198
        printf("Receive Accept Error\n");
199
    if (esr.send_illegal_vector)
199
    if (esr.send_illegal_vector)
200
        printf("Send Illegal Vector\n");
200
        printf("Send Illegal Vector\n");
201
    if (esr.received_illegal_vector)
201
    if (esr.received_illegal_vector)
202
        printf("Received Illegal Vector\n");
202
        printf("Received Illegal Vector\n");
203
    if (esr.illegal_register_address)
203
    if (esr.illegal_register_address)
204
        printf("Illegal Register Address\n");
204
        printf("Illegal Register Address\n");
205
 
205
 
206
    return !esr.err_bitmap;
206
    return !esr.err_bitmap;
207
}
207
}
208
 
208
 
209
/** Send all CPUs excluding CPU IPI vector.
209
/** Send all CPUs excluding CPU IPI vector.
210
 *
210
 *
211
 * @param vector Interrupt vector to be sent.
211
 * @param vector Interrupt vector to be sent.
212
 *
212
 *
213
 * @return 0 on failure, 1 on success.
213
 * @return 0 on failure, 1 on success.
214
 */
214
 */
215
int l_apic_broadcast_custom_ipi(__u8 vector)
215
int l_apic_broadcast_custom_ipi(__u8 vector)
216
{
216
{
217
    icr_t icr;
217
    icr_t icr;
218
 
218
 
219
    icr.lo = l_apic[ICRlo];
219
    icr.lo = l_apic[ICRlo];
220
    icr.delmod = DELMOD_FIXED;
220
    icr.delmod = DELMOD_FIXED;
221
    icr.destmod = DESTMOD_LOGIC;
221
    icr.destmod = DESTMOD_LOGIC;
222
    icr.level = LEVEL_ASSERT;
222
    icr.level = LEVEL_ASSERT;
223
    icr.shorthand = SHORTHAND_ALL_EXCL;
223
    icr.shorthand = SHORTHAND_ALL_EXCL;
224
    icr.trigger_mode = TRIGMOD_LEVEL;
224
    icr.trigger_mode = TRIGMOD_LEVEL;
225
    icr.vector = vector;
225
    icr.vector = vector;
226
 
226
 
227
    l_apic[ICRlo] = icr.lo;
227
    l_apic[ICRlo] = icr.lo;
228
 
228
 
229
    icr.lo = l_apic[ICRlo];
229
    icr.lo = l_apic[ICRlo];
230
    if (icr.delivs == DELIVS_PENDING) {
230
    if (icr.delivs == DELIVS_PENDING) {
231
#ifdef CONFIG_DEBUG
231
#ifdef CONFIG_DEBUG
232
        printf("IPI is pending.\n");
232
        printf("IPI is pending.\n");
233
#endif
233
#endif
234
    }
234
    }
235
 
235
 
236
    return apic_poll_errors();
236
    return apic_poll_errors();
237
}
237
}
238
 
238
 
239
/** Universal Start-up Algorithm for bringing up the AP processors.
239
/** Universal Start-up Algorithm for bringing up the AP processors.
240
 *
240
 *
241
 * @param apicid APIC ID of the processor to be brought up.
241
 * @param apicid APIC ID of the processor to be brought up.
242
 *
242
 *
243
 * @return 0 on failure, 1 on success.
243
 * @return 0 on failure, 1 on success.
244
 */
244
 */
245
int l_apic_send_init_ipi(__u8 apicid)
245
int l_apic_send_init_ipi(__u8 apicid)
246
{
246
{
247
    icr_t icr;
247
    icr_t icr;
248
    int i;
248
    int i;
249
 
249
 
250
    /*
250
    /*
251
     * Read the ICR register in and zero all non-reserved fields.
251
     * Read the ICR register in and zero all non-reserved fields.
252
     */
252
     */
253
    icr.lo = l_apic[ICRlo];
253
    icr.lo = l_apic[ICRlo];
254
    icr.hi = l_apic[ICRhi];
254
    icr.hi = l_apic[ICRhi];
255
   
255
   
256
    icr.delmod = DELMOD_INIT;
256
    icr.delmod = DELMOD_INIT;
257
    icr.destmod = DESTMOD_PHYS;
257
    icr.destmod = DESTMOD_PHYS;
258
    icr.level = LEVEL_ASSERT;
258
    icr.level = LEVEL_ASSERT;
259
    icr.trigger_mode = TRIGMOD_LEVEL;
259
    icr.trigger_mode = TRIGMOD_LEVEL;
260
    icr.shorthand = SHORTHAND_NONE;
260
    icr.shorthand = SHORTHAND_NONE;
261
    icr.vector = 0;
261
    icr.vector = 0;
262
    icr.dest = apicid;
262
    icr.dest = apicid;
263
   
263
   
264
    l_apic[ICRhi] = icr.hi;
264
    l_apic[ICRhi] = icr.hi;
265
    l_apic[ICRlo] = icr.lo;
265
    l_apic[ICRlo] = icr.lo;
266
 
266
 
267
    /*
267
    /*
268
     * According to MP Specification, 20us should be enough to
268
     * According to MP Specification, 20us should be enough to
269
     * deliver the IPI.
269
     * deliver the IPI.
270
     */
270
     */
271
    delay(20);
271
    delay(20);
272
 
272
 
273
    if (!apic_poll_errors())
273
    if (!apic_poll_errors())
274
        return 0;
274
        return 0;
275
 
275
 
276
    icr.lo = l_apic[ICRlo];
276
    icr.lo = l_apic[ICRlo];
277
    if (icr.delivs == DELIVS_PENDING) {
277
    if (icr.delivs == DELIVS_PENDING) {
278
#ifdef CONFIG_DEBUG
278
#ifdef CONFIG_DEBUG
279
        printf("IPI is pending.\n");
279
        printf("IPI is pending.\n");
280
#endif
280
#endif
281
    }
281
    }
282
 
282
 
283
    icr.delmod = DELMOD_INIT;
283
    icr.delmod = DELMOD_INIT;
284
    icr.destmod = DESTMOD_PHYS;
284
    icr.destmod = DESTMOD_PHYS;
285
    icr.level = LEVEL_DEASSERT;
285
    icr.level = LEVEL_DEASSERT;
286
    icr.shorthand = SHORTHAND_NONE;
286
    icr.shorthand = SHORTHAND_NONE;
287
    icr.trigger_mode = TRIGMOD_LEVEL;
287
    icr.trigger_mode = TRIGMOD_LEVEL;
288
    icr.vector = 0;
288
    icr.vector = 0;
289
    l_apic[ICRlo] = icr.lo;
289
    l_apic[ICRlo] = icr.lo;
290
 
290
 
291
    /*
291
    /*
292
     * Wait 10ms as MP Specification specifies.
292
     * Wait 10ms as MP Specification specifies.
293
     */
293
     */
294
    delay(10000);
294
    delay(10000);
295
 
295
 
296
    if (!is_82489DX_apic(l_apic[LAVR])) {
296
    if (!is_82489DX_apic(l_apic[LAVR])) {
297
        /*
297
        /*
298
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
298
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
299
         */
299
         */
300
        for (i = 0; i<2; i++) {
300
        for (i = 0; i<2; i++) {
301
            icr.lo = l_apic[ICRlo];
301
            icr.lo = l_apic[ICRlo];
302
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
302
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
303
            icr.delmod = DELMOD_STARTUP;
303
            icr.delmod = DELMOD_STARTUP;
304
            icr.destmod = DESTMOD_PHYS;
304
            icr.destmod = DESTMOD_PHYS;
305
            icr.level = LEVEL_ASSERT;
305
            icr.level = LEVEL_ASSERT;
306
            icr.shorthand = SHORTHAND_NONE;
306
            icr.shorthand = SHORTHAND_NONE;
307
            icr.trigger_mode = TRIGMOD_LEVEL;
307
            icr.trigger_mode = TRIGMOD_LEVEL;
308
            l_apic[ICRlo] = icr.lo;
308
            l_apic[ICRlo] = icr.lo;
309
            delay(200);
309
            delay(200);
310
        }
310
        }
311
    }
311
    }
312
   
312
   
313
    return apic_poll_errors();
313
    return apic_poll_errors();
314
}
314
}
315
 
315
 
316
/** Initialize Local APIC. */
316
/** Initialize Local APIC. */
317
void l_apic_init(void)
317
void l_apic_init(void)
318
{
318
{
319
    lvt_error_t error;
319
    lvt_error_t error;
320
    lvt_lint_t lint;
320
    lvt_lint_t lint;
321
    tpr_t tpr;
321
    tpr_t tpr;
322
    svr_t svr;
322
    svr_t svr;
323
    icr_t icr;
323
    icr_t icr;
324
    tdcr_t tdcr;
324
    tdcr_t tdcr;
325
    lvt_tm_t tm;
325
    lvt_tm_t tm;
326
    ldr_t ldr;
326
    ldr_t ldr;
327
    dfr_t dfr;
327
    dfr_t dfr;
328
    __u32 t1, t2;
328
    __u32 t1, t2;
329
 
329
 
330
    /* Initialize LVT Error register. */
330
    /* Initialize LVT Error register. */
331
    error.value = l_apic[LVT_Err];
331
    error.value = l_apic[LVT_Err];
332
    error.masked = true;
332
    error.masked = true;
333
    l_apic[LVT_Err] = error.value;
333
    l_apic[LVT_Err] = error.value;
334
 
334
 
335
    /* Initialize LVT LINT0 register. */
335
    /* Initialize LVT LINT0 register. */
336
    lint.value = l_apic[LVT_LINT0];
336
    lint.value = l_apic[LVT_LINT0];
337
    lint.masked = true;
337
    lint.masked = true;
338
    l_apic[LVT_LINT0] = lint.value;
338
    l_apic[LVT_LINT0] = lint.value;
339
 
339
 
340
    /* Initialize LVT LINT1 register. */
340
    /* Initialize LVT LINT1 register. */
341
    lint.value = l_apic[LVT_LINT1];
341
    lint.value = l_apic[LVT_LINT1];
342
    lint.masked = true;
342
    lint.masked = true;
343
    l_apic[LVT_LINT1] = lint.value;
343
    l_apic[LVT_LINT1] = lint.value;
344
 
344
 
345
    /* Task Priority Register initialization. */
345
    /* Task Priority Register initialization. */
346
    tpr.value = l_apic[TPR];
346
    tpr.value = l_apic[TPR];
347
    tpr.pri_sc = 0;
347
    tpr.pri_sc = 0;
348
    tpr.pri = 0;
348
    tpr.pri = 0;
349
    l_apic[TPR] = tpr.value;
349
    l_apic[TPR] = tpr.value;
350
   
350
   
351
    /* Spurious-Interrupt Vector Register initialization. */
351
    /* Spurious-Interrupt Vector Register initialization. */
352
    svr.value = l_apic[SVR];
352
    svr.value = l_apic[SVR];
353
    svr.vector = VECTOR_APIC_SPUR;
353
    svr.vector = VECTOR_APIC_SPUR;
354
    svr.lapic_enabled = true;
354
    svr.lapic_enabled = true;
355
    svr.focus_checking = true;
355
    svr.focus_checking = true;
356
    l_apic[SVR] = svr.value;
356
    l_apic[SVR] = svr.value;
357
 
357
 
358
    if (CPU->arch.family >= 6)
358
    if (CPU->arch.family >= 6)
359
        enable_l_apic_in_msr();
359
        enable_l_apic_in_msr();
360
   
360
   
361
    /* Interrupt Command Register initialization. */
361
    /* Interrupt Command Register initialization. */
362
    icr.lo = l_apic[ICRlo];
362
    icr.lo = l_apic[ICRlo];
363
    icr.delmod = DELMOD_INIT;
363
    icr.delmod = DELMOD_INIT;
364
    icr.destmod = DESTMOD_PHYS;
364
    icr.destmod = DESTMOD_PHYS;
365
    icr.level = LEVEL_DEASSERT;
365
    icr.level = LEVEL_DEASSERT;
366
    icr.shorthand = SHORTHAND_ALL_INCL;
366
    icr.shorthand = SHORTHAND_ALL_INCL;
367
    icr.trigger_mode = TRIGMOD_LEVEL;
367
    icr.trigger_mode = TRIGMOD_LEVEL;
368
    l_apic[ICRlo] = icr.lo;
368
    l_apic[ICRlo] = icr.lo;
369
   
369
   
370
    /* Timer Divide Configuration Register initialization. */
370
    /* Timer Divide Configuration Register initialization. */
371
    tdcr.value = l_apic[TDCR];
371
    tdcr.value = l_apic[TDCR];
372
    tdcr.div_value = DIVIDE_1;
372
    tdcr.div_value = DIVIDE_1;
373
    l_apic[TDCR] = tdcr.value;
373
    l_apic[TDCR] = tdcr.value;
374
 
374
 
375
    /* Program local timer. */
375
    /* Program local timer. */
376
    tm.value = l_apic[LVT_Tm];
376
    tm.value = l_apic[LVT_Tm];
377
    tm.vector = VECTOR_CLK;
377
    tm.vector = VECTOR_CLK;
378
    tm.mode = TIMER_PERIODIC;
378
    tm.mode = TIMER_PERIODIC;
379
    tm.masked = false;
379
    tm.masked = false;
380
    l_apic[LVT_Tm] = tm.value;
380
    l_apic[LVT_Tm] = tm.value;
381
 
381
 
382
    /*
382
    /*
383
     * Measure and configure the timer to generate timer
383
     * Measure and configure the timer to generate timer
384
     * interrupt with period 1s/HZ seconds.
384
     * interrupt with period 1s/HZ seconds.
385
     */
385
     */
386
    t1 = l_apic[CCRT];
386
    t1 = l_apic[CCRT];
387
    l_apic[ICRT] = 0xffffffff;
387
    l_apic[ICRT] = 0xffffffff;
388
 
388
 
389
    while (l_apic[CCRT] == t1)
389
    while (l_apic[CCRT] == t1)
390
        ;
390
        ;
391
       
391
       
392
    t1 = l_apic[CCRT];
392
    t1 = l_apic[CCRT];
393
    delay(1000000/HZ);
393
    delay(1000000/HZ);
394
    t2 = l_apic[CCRT];
394
    t2 = l_apic[CCRT];
395
   
395
   
396
    l_apic[ICRT] = t1-t2;
396
    l_apic[ICRT] = t1-t2;
397
   
397
   
398
    /* Program Logical Destination Register. */
398
    /* Program Logical Destination Register. */
399
    ldr.value = l_apic[LDR];
399
    ldr.value = l_apic[LDR];
400
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
400
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
401
        ldr.id = (1<<CPU->id);
401
        ldr.id = (1<<CPU->id);
402
    l_apic[LDR] = ldr.value;
402
    l_apic[LDR] = ldr.value;
403
   
403
   
404
    /* Program Destination Format Register for Flat mode. */
404
    /* Program Destination Format Register for Flat mode. */
405
    dfr.value = l_apic[DFR];
405
    dfr.value = l_apic[DFR];
406
    dfr.model = MODEL_FLAT;
406
    dfr.model = MODEL_FLAT;
407
    l_apic[DFR] = dfr.value;
407
    l_apic[DFR] = dfr.value;
408
}
408
}
409
 
409
 
410
/** Local APIC End of Interrupt. */
410
/** Local APIC End of Interrupt. */
411
void l_apic_eoi(void)
411
void l_apic_eoi(void)
412
{
412
{
413
    l_apic[EOI] = 0;
413
    l_apic[EOI] = 0;
414
}
414
}
415
 
415
 
416
/** Dump content of Local APIC registers. */
416
/** Dump content of Local APIC registers. */
417
void l_apic_debug(void)
417
void l_apic_debug(void)
418
{
418
{
419
#ifdef LAPIC_VERBOSE
419
#ifdef LAPIC_VERBOSE
420
    lvt_tm_t tm;
420
    lvt_tm_t tm;
421
    lvt_lint_t lint;
421
    lvt_lint_t lint;
422
    lvt_error_t error; 
422
    lvt_error_t error; 
423
   
423
   
424
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
424
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
425
 
425
 
426
    tm.value = l_apic[LVT_Tm];
426
    tm.value = l_apic[LVT_Tm];
427
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
427
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
428
    lint.value = l_apic[LVT_LINT0];
428
    lint.value = l_apic[LVT_LINT0];
429
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
429
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
430
    lint.value = l_apic[LVT_LINT1];
430
    lint.value = l_apic[LVT_LINT1];
431
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
431
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
432
    error.value = l_apic[LVT_Err];
432
    error.value = l_apic[LVT_Err];
433
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
433
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
434
#endif
434
#endif
435
}
435
}
436
 
436
 
437
/** Local APIC Timer Interrupt.
437
/** Local APIC Timer Interrupt.
438
 *
438
 *
439
 * @param n Interrupt vector number.
439
 * @param n Interrupt vector number.
440
 * @param stack Interrupted stack.
440
 * @param stack Interrupted stack.
441
 */
441
 */
442
void l_apic_timer_interrupt(int n, istate_t *istate)
442
void l_apic_timer_interrupt(int n, istate_t *istate)
443
{
443
{
444
    l_apic_eoi();
444
    l_apic_eoi();
445
    clock();
445
    clock();
446
}
446
}
447
 
447
 
448
/** Get Local APIC ID.
448
/** Get Local APIC ID.
449
 *
449
 *
450
 * @return Local APIC ID.
450
 * @return Local APIC ID.
451
 */
451
 */
452
__u8 l_apic_id(void)
452
__u8 l_apic_id(void)
453
{
453
{
454
    l_apic_id_t idreg;
454
    l_apic_id_t idreg;
455
   
455
   
456
    idreg.value = l_apic[L_APIC_ID];
456
    idreg.value = l_apic[L_APIC_ID];
457
    return idreg.apic_id;
457
    return idreg.apic_id;
458
}
458
}
459
 
459
 
460
/** Read from IO APIC register.
460
/** Read from IO APIC register.
461
 *
461
 *
462
 * @param address IO APIC register address.
462
 * @param address IO APIC register address.
463
 *
463
 *
464
 * @return Content of the addressed IO APIC register.
464
 * @return Content of the addressed IO APIC register.
465
 */
465
 */
466
__u32 io_apic_read(__u8 address)
466
__u32 io_apic_read(__u8 address)
467
{
467
{
468
    io_regsel_t regsel;
468
    io_regsel_t regsel;
469
   
469
   
470
    regsel.value = io_apic[IOREGSEL];
470
    regsel.value = io_apic[IOREGSEL];
471
    regsel.reg_addr = address;
471
    regsel.reg_addr = address;
472
    io_apic[IOREGSEL] = regsel.value;
472
    io_apic[IOREGSEL] = regsel.value;
473
    return io_apic[IOWIN];
473
    return io_apic[IOWIN];
474
}
474
}
475
 
475
 
476
/** Write to IO APIC register.
476
/** Write to IO APIC register.
477
 *
477
 *
478
 * @param address IO APIC register address.
478
 * @param address IO APIC register address.
479
 * @param Content to be written to the addressed IO APIC register.
479
 * @param Content to be written to the addressed IO APIC register.
480
 */
480
 */
481
void io_apic_write(__u8 address, __u32 x)
481
void io_apic_write(__u8 address, __u32 x)
482
{
482
{
483
    io_regsel_t regsel;
483
    io_regsel_t regsel;
484
   
484
   
485
    regsel.value = io_apic[IOREGSEL];
485
    regsel.value = io_apic[IOREGSEL];
486
    regsel.reg_addr = address;
486
    regsel.reg_addr = address;
487
    io_apic[IOREGSEL] = regsel.value;
487
    io_apic[IOREGSEL] = regsel.value;
488
    io_apic[IOWIN] = x;
488
    io_apic[IOWIN] = x;
489
}
489
}
490
 
490
 
491
/** Change some attributes of one item in I/O Redirection Table.
491
/** Change some attributes of one item in I/O Redirection Table.
492
 *
492
 *
493
 * @param pin IO APIC pin number.
493
 * @param pin IO APIC pin number.
494
 * @param dest Interrupt destination address.
494
 * @param dest Interrupt destination address.
495
 * @param v Interrupt vector to trigger.
495
 * @param v Interrupt vector to trigger.
496
 * @param flags Flags.
496
 * @param flags Flags.
497
 */
497
 */
498
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
498
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
499
{
499
{
500
    io_redirection_reg_t reg;
500
    io_redirection_reg_t reg;
501
    int dlvr = DELMOD_FIXED;
501
    int dlvr = DELMOD_FIXED;
502
   
502
   
503
    if (flags & LOPRI)
503
    if (flags & LOPRI)
504
        dlvr = DELMOD_LOWPRI;
504
        dlvr = DELMOD_LOWPRI;
505
 
505
 
506
    reg.lo = io_apic_read(IOREDTBL + pin*2);
506
    reg.lo = io_apic_read(IOREDTBL + pin*2);
507
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
507
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
508
   
508
   
509
    reg.dest = dest;
509
    reg.dest = dest;
510
    reg.destmod = DESTMOD_LOGIC;
510
    reg.destmod = DESTMOD_LOGIC;
511
    reg.trigger_mode = TRIGMOD_EDGE;
511
    reg.trigger_mode = TRIGMOD_EDGE;
512
    reg.intpol = POLARITY_HIGH;
512
    reg.intpol = POLARITY_HIGH;
513
    reg.delmod = dlvr;
513
    reg.delmod = dlvr;
514
    reg.intvec = v;
514
    reg.intvec = v;
515
 
515
 
516
    io_apic_write(IOREDTBL + pin*2, reg.lo);
516
    io_apic_write(IOREDTBL + pin*2, reg.lo);
517
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
517
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
518
}
518
}
519
 
519
 
520
/** Mask IRQs in IO APIC.
520
/** Mask IRQs in IO APIC.
521
 *
521
 *
522
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
522
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
523
 */
523
 */
524
void io_apic_disable_irqs(__u16 irqmask)
524
void io_apic_disable_irqs(__u16 irqmask)
525
{
525
{
526
    io_redirection_reg_t reg;
526
    io_redirection_reg_t reg;
527
    int i, pin;
527
    int i, pin;
528
   
528
   
529
    for (i=0;i<16;i++) {
529
    for (i=0;i<16;i++) {
530
        if (irqmask & (1<<i)) {
530
        if (irqmask & (1<<i)) {
531
            /*
531
            /*
532
             * Mask the signal input in IO APIC if there is a
532
             * Mask the signal input in IO APIC if there is a
533
             * mapping for the respective IRQ number.
533
             * mapping for the respective IRQ number.
534
             */
534
             */
535
            pin = smp_irq_to_pin(i);
535
            pin = smp_irq_to_pin(i);
536
            if (pin != -1) {
536
            if (pin != -1) {
537
                reg.lo = io_apic_read(IOREDTBL + pin*2);
537
                reg.lo = io_apic_read(IOREDTBL + pin*2);
538
                reg.masked = true;
538
                reg.masked = true;
539
                io_apic_write(IOREDTBL + pin*2, reg.lo);
539
                io_apic_write(IOREDTBL + pin*2, reg.lo);
540
            }
540
            }
541
           
541
           
542
        }
542
        }
543
    }
543
    }
544
}
544
}
545
 
545
 
546
/** Unmask IRQs in IO APIC.
546
/** Unmask IRQs in IO APIC.
547
 *
547
 *
548
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
548
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
549
 */
549
 */
550
void io_apic_enable_irqs(__u16 irqmask)
550
void io_apic_enable_irqs(__u16 irqmask)
551
{
551
{
552
    int i, pin;
552
    int i, pin;
553
    io_redirection_reg_t reg;  
553
    io_redirection_reg_t reg;  
554
   
554
   
555
    for (i=0;i<16;i++) {
555
    for (i=0;i<16;i++) {
556
        if (irqmask & (1<<i)) {
556
        if (irqmask & (1<<i)) {
557
            /*
557
            /*
558
             * Unmask the signal input in IO APIC if there is a
558
             * Unmask the signal input in IO APIC if there is a
559
             * mapping for the respective IRQ number.
559
             * mapping for the respective IRQ number.
560
             */
560
             */
561
            pin = smp_irq_to_pin(i);
561
            pin = smp_irq_to_pin(i);
562
            if (pin != -1) {
562
            if (pin != -1) {
563
                reg.lo = io_apic_read(IOREDTBL + pin*2);
563
                reg.lo = io_apic_read(IOREDTBL + pin*2);
564
                reg.masked = false;
564
                reg.masked = false;
565
                io_apic_write(IOREDTBL + pin*2, reg.lo);
565
                io_apic_write(IOREDTBL + pin*2, reg.lo);
566
            }
566
            }
567
           
567
           
568
        }
568
        }
569
    }
569
    }
570
}
570
}
571
 
571
 
572
#endif /* CONFIG_SMP */
572
#endif /* CONFIG_SMP */
573
 
573