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1 | # |
1 | # |
2 | # Copyright (C) 2003-2004 Jakub Jermar |
2 | # Copyright (C) 2003-2004 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
30 | 30 | ||
31 | .text |
31 | .text |
32 | 32 | ||
33 | .macro cp0_read reg |
33 | .macro cp0_read reg |
34 | mfc0 $2,\reg |
34 | mfc0 $2,\reg |
35 | j $31 |
35 | j $31 |
36 | nop |
36 | nop |
37 | .endm |
37 | .endm |
38 | 38 | ||
39 | .macro cp0_write reg |
39 | .macro cp0_write reg |
40 | mtc0 $4,\reg |
40 | mtc0 $4,\reg |
41 | j $31 |
41 | j $31 |
42 | nop |
42 | nop |
43 | .endm |
43 | .endm |
44 | 44 | ||
45 | .set noat |
45 | .set noat |
46 | .set noreorder |
46 | .set noreorder |
47 | .set nomacro |
47 | .set nomacro |
48 | 48 | ||
49 | .global cpu_halt |
49 | .global cpu_halt |
50 | cpu_halt: |
50 | cpu_halt: |
51 | j cpu_halt |
51 | j cpu_halt |
52 | nop |
52 | nop |
53 | 53 | ||
54 | 54 | ||
55 | .global memsetb |
55 | .global memsetb |
56 | memsetb: |
56 | memsetb: |
57 | j _memsetb |
57 | j _memsetb |
58 | nop |
58 | nop |
59 | 59 | ||
60 | 60 | ||
61 | .global memcpy |
61 | .global memcpy |
62 | .global memcpy_from_uspace |
62 | .global memcpy_from_uspace |
63 | .global memcpy_to_uspace |
63 | .global memcpy_to_uspace |
64 | .global memcpy_from_uspace_failover_address |
64 | .global memcpy_from_uspace_failover_address |
65 | .global memcpy_to_uspace_failover_address |
65 | .global memcpy_to_uspace_failover_address |
66 | memcpy: |
66 | memcpy: |
67 | memcpy_from_uspace: |
67 | memcpy_from_uspace: |
68 | memcpy_to_uspace: |
68 | memcpy_to_uspace: |
69 | srl $t1,$a2,0x2 |
69 | srl $t1,$a2,0x2 |
70 | beqz $t1,1f |
70 | beqz $t1,1f |
71 | move $t0,$zero |
71 | move $t0,$zero |
72 | move $a3,$zero |
72 | move $a3,$zero |
73 | 2: |
73 | 2: |
74 | addu $v0,$a1,$a3 |
74 | addu $v0,$a1,$a3 |
75 | lw $v1,0($v0) |
75 | lw $v1,0($v0) |
76 | addiu $t0,$t0,1 |
76 | addiu $t0,$t0,1 |
77 | addu $v0,$a0,$a3 |
77 | addu $v0,$a0,$a3 |
78 | sw $v1,0($v0) |
78 | sw $v1,0($v0) |
79 | bne $t0,$t1,2b |
79 | bne $t0,$t1,2b |
80 | addiu $a3,$a3,4 |
80 | addiu $a3,$a3,4 |
81 | 1: |
81 | 1: |
82 | andi $a2,$a2,0x3 |
82 | andi $a2,$a2,0x3 |
83 | beqz $a2,3f |
83 | beqz $a2,3f |
84 | move $a3,$zero |
84 | move $a3,$zero |
85 | sll $v0,$t0,0x2 |
85 | sll $v0,$t0,0x2 |
86 | addu $t1,$a0,$v0 |
86 | addu $t1,$a0,$v0 |
87 | addu $t0,$v0,$a1 |
87 | addu $t0,$v0,$a1 |
88 | 4: |
88 | 4: |
89 | addu $v0,$t0,$a3 |
89 | addu $v0,$t0,$a3 |
90 | lbu $a0,0($v0) |
90 | lbu $a0,0($v0) |
91 | addu $v1,$t1,$a3 |
91 | addu $v1,$t1,$a3 |
92 | addiu $a3,$a3,1 |
92 | addiu $a3,$a3,1 |
93 | bne $a3,$a2,4b |
93 | bne $a3,$a2,4b |
94 | sb $a0,0($v1) |
94 | sb $a0,0($v1) |
95 | 3: |
95 | 3: |
96 | jr $ra |
96 | jr $ra |
97 | move $v0,$a1 |
97 | move $v0,$a1 |
98 | 98 | ||
99 | memcpy_from_uspace_failover_address: |
99 | memcpy_from_uspace_failover_address: |
100 | memcpy_to_uspace_failover_address: |
100 | memcpy_to_uspace_failover_address: |
101 | jr $ra |
101 | jr $ra |
102 | move $v0, $zero |
102 | move $v0, $zero |
103 | 103 | ||
104 | 104 | ||
105 | 105 | ||
106 | .macro fpu_gp_save reg ctx |
106 | .macro fpu_gp_save reg ctx |
107 | mfc1 $t0,$\reg |
107 | mfc1 $t0,$\reg |
108 | sw $t0, \reg*4(\ctx) |
108 | sw $t0, \reg*4(\ctx) |
109 | .endm |
109 | .endm |
110 | 110 | ||
111 | .macro fpu_gp_restore reg ctx |
111 | .macro fpu_gp_restore reg ctx |
112 | lw $t0, \reg*4(\ctx) |
112 | lw $t0, \reg*4(\ctx) |
113 | mtc1 $t0,$\reg |
113 | mtc1 $t0,$\reg |
114 | .endm |
114 | .endm |
115 | 115 | ||
116 | .macro fpu_ct_save reg ctx |
116 | .macro fpu_ct_save reg ctx |
117 | cfc1 $t0,$1 |
117 | cfc1 $t0,$1 |
118 | sw $t0, (\reg+32)*4(\ctx) |
118 | sw $t0, (\reg+32)*4(\ctx) |
119 | .endm |
119 | .endm |
120 | 120 | ||
121 | .macro fpu_ct_restore reg ctx |
121 | .macro fpu_ct_restore reg ctx |
122 | lw $t0, (\reg+32)*4(\ctx) |
122 | lw $t0, (\reg+32)*4(\ctx) |
123 | ctc1 $t0,$\reg |
123 | ctc1 $t0,$\reg |
124 | .endm |
124 | .endm |
125 | 125 | ||
126 | 126 | ||
127 | .global fpu_context_save |
127 | .global fpu_context_save |
128 | fpu_context_save: |
128 | fpu_context_save: |
129 | #ifdef ARCH_HAS_FPU |
129 | #ifdef ARCH_HAS_FPU |
130 | fpu_gp_save 0,$a0 |
130 | fpu_gp_save 0,$a0 |
131 | fpu_gp_save 1,$a0 |
131 | fpu_gp_save 1,$a0 |
132 | fpu_gp_save 2,$a0 |
132 | fpu_gp_save 2,$a0 |
133 | fpu_gp_save 3,$a0 |
133 | fpu_gp_save 3,$a0 |
134 | fpu_gp_save 4,$a0 |
134 | fpu_gp_save 4,$a0 |
135 | fpu_gp_save 5,$a0 |
135 | fpu_gp_save 5,$a0 |
136 | fpu_gp_save 6,$a0 |
136 | fpu_gp_save 6,$a0 |
137 | fpu_gp_save 7,$a0 |
137 | fpu_gp_save 7,$a0 |
138 | fpu_gp_save 8,$a0 |
138 | fpu_gp_save 8,$a0 |
139 | fpu_gp_save 9,$a0 |
139 | fpu_gp_save 9,$a0 |
140 | fpu_gp_save 10,$a0 |
140 | fpu_gp_save 10,$a0 |
141 | fpu_gp_save 11,$a0 |
141 | fpu_gp_save 11,$a0 |
142 | fpu_gp_save 12,$a0 |
142 | fpu_gp_save 12,$a0 |
143 | fpu_gp_save 13,$a0 |
143 | fpu_gp_save 13,$a0 |
144 | fpu_gp_save 14,$a0 |
144 | fpu_gp_save 14,$a0 |
145 | fpu_gp_save 15,$a0 |
145 | fpu_gp_save 15,$a0 |
146 | fpu_gp_save 16,$a0 |
146 | fpu_gp_save 16,$a0 |
147 | fpu_gp_save 17,$a0 |
147 | fpu_gp_save 17,$a0 |
148 | fpu_gp_save 18,$a0 |
148 | fpu_gp_save 18,$a0 |
149 | fpu_gp_save 19,$a0 |
149 | fpu_gp_save 19,$a0 |
150 | fpu_gp_save 20,$a0 |
150 | fpu_gp_save 20,$a0 |
151 | fpu_gp_save 21,$a0 |
151 | fpu_gp_save 21,$a0 |
152 | fpu_gp_save 22,$a0 |
152 | fpu_gp_save 22,$a0 |
153 | fpu_gp_save 23,$a0 |
153 | fpu_gp_save 23,$a0 |
154 | fpu_gp_save 24,$a0 |
154 | fpu_gp_save 24,$a0 |
155 | fpu_gp_save 25,$a0 |
155 | fpu_gp_save 25,$a0 |
156 | fpu_gp_save 26,$a0 |
156 | fpu_gp_save 26,$a0 |
157 | fpu_gp_save 27,$a0 |
157 | fpu_gp_save 27,$a0 |
158 | fpu_gp_save 28,$a0 |
158 | fpu_gp_save 28,$a0 |
159 | fpu_gp_save 29,$a0 |
159 | fpu_gp_save 29,$a0 |
160 | fpu_gp_save 30,$a0 |
160 | fpu_gp_save 30,$a0 |
161 | fpu_gp_save 31,$a0 |
161 | fpu_gp_save 31,$a0 |
162 | 162 | ||
163 | fpu_ct_save 1,$a0 |
163 | fpu_ct_save 1,$a0 |
164 | fpu_ct_save 2,$a0 |
164 | fpu_ct_save 2,$a0 |
165 | fpu_ct_save 3,$a0 |
165 | fpu_ct_save 3,$a0 |
166 | fpu_ct_save 4,$a0 |
166 | fpu_ct_save 4,$a0 |
167 | fpu_ct_save 5,$a0 |
167 | fpu_ct_save 5,$a0 |
168 | fpu_ct_save 6,$a0 |
168 | fpu_ct_save 6,$a0 |
169 | fpu_ct_save 7,$a0 |
169 | fpu_ct_save 7,$a0 |
170 | fpu_ct_save 8,$a0 |
170 | fpu_ct_save 8,$a0 |
171 | fpu_ct_save 9,$a0 |
171 | fpu_ct_save 9,$a0 |
172 | fpu_ct_save 10,$a0 |
172 | fpu_ct_save 10,$a0 |
173 | fpu_ct_save 11,$a0 |
173 | fpu_ct_save 11,$a0 |
174 | fpu_ct_save 12,$a0 |
174 | fpu_ct_save 12,$a0 |
175 | fpu_ct_save 13,$a0 |
175 | fpu_ct_save 13,$a0 |
176 | fpu_ct_save 14,$a0 |
176 | fpu_ct_save 14,$a0 |
177 | fpu_ct_save 15,$a0 |
177 | fpu_ct_save 15,$a0 |
178 | fpu_ct_save 16,$a0 |
178 | fpu_ct_save 16,$a0 |
179 | fpu_ct_save 17,$a0 |
179 | fpu_ct_save 17,$a0 |
180 | fpu_ct_save 18,$a0 |
180 | fpu_ct_save 18,$a0 |
181 | fpu_ct_save 19,$a0 |
181 | fpu_ct_save 19,$a0 |
182 | fpu_ct_save 20,$a0 |
182 | fpu_ct_save 20,$a0 |
183 | fpu_ct_save 21,$a0 |
183 | fpu_ct_save 21,$a0 |
184 | fpu_ct_save 22,$a0 |
184 | fpu_ct_save 22,$a0 |
185 | fpu_ct_save 23,$a0 |
185 | fpu_ct_save 23,$a0 |
186 | fpu_ct_save 24,$a0 |
186 | fpu_ct_save 24,$a0 |
187 | fpu_ct_save 25,$a0 |
187 | fpu_ct_save 25,$a0 |
188 | fpu_ct_save 26,$a0 |
188 | fpu_ct_save 26,$a0 |
189 | fpu_ct_save 27,$a0 |
189 | fpu_ct_save 27,$a0 |
190 | fpu_ct_save 28,$a0 |
190 | fpu_ct_save 28,$a0 |
191 | fpu_ct_save 29,$a0 |
191 | fpu_ct_save 29,$a0 |
192 | fpu_ct_save 30,$a0 |
192 | fpu_ct_save 30,$a0 |
193 | fpu_ct_save 31,$a0 |
193 | fpu_ct_save 31,$a0 |
194 | #endif |
194 | #endif |
195 | j $ra |
195 | j $ra |
196 | nop |
196 | nop |
197 | 197 | ||
198 | .global fpu_context_restore |
198 | .global fpu_context_restore |
199 | fpu_context_restore: |
199 | fpu_context_restore: |
200 | #ifdef ARCH_HAS_FPU |
200 | #ifdef ARCH_HAS_FPU |
201 | fpu_gp_restore 0,$a0 |
201 | fpu_gp_restore 0,$a0 |
202 | fpu_gp_restore 1,$a0 |
202 | fpu_gp_restore 1,$a0 |
203 | fpu_gp_restore 2,$a0 |
203 | fpu_gp_restore 2,$a0 |
204 | fpu_gp_restore 3,$a0 |
204 | fpu_gp_restore 3,$a0 |
205 | fpu_gp_restore 4,$a0 |
205 | fpu_gp_restore 4,$a0 |
206 | fpu_gp_restore 5,$a0 |
206 | fpu_gp_restore 5,$a0 |
207 | fpu_gp_restore 6,$a0 |
207 | fpu_gp_restore 6,$a0 |
208 | fpu_gp_restore 7,$a0 |
208 | fpu_gp_restore 7,$a0 |
209 | fpu_gp_restore 8,$a0 |
209 | fpu_gp_restore 8,$a0 |
210 | fpu_gp_restore 9,$a0 |
210 | fpu_gp_restore 9,$a0 |
211 | fpu_gp_restore 10,$a0 |
211 | fpu_gp_restore 10,$a0 |
212 | fpu_gp_restore 11,$a0 |
212 | fpu_gp_restore 11,$a0 |
213 | fpu_gp_restore 12,$a0 |
213 | fpu_gp_restore 12,$a0 |
214 | fpu_gp_restore 13,$a0 |
214 | fpu_gp_restore 13,$a0 |
215 | fpu_gp_restore 14,$a0 |
215 | fpu_gp_restore 14,$a0 |
216 | fpu_gp_restore 15,$a0 |
216 | fpu_gp_restore 15,$a0 |
217 | fpu_gp_restore 16,$a0 |
217 | fpu_gp_restore 16,$a0 |
218 | fpu_gp_restore 17,$a0 |
218 | fpu_gp_restore 17,$a0 |
219 | fpu_gp_restore 18,$a0 |
219 | fpu_gp_restore 18,$a0 |
220 | fpu_gp_restore 19,$a0 |
220 | fpu_gp_restore 19,$a0 |
221 | fpu_gp_restore 20,$a0 |
221 | fpu_gp_restore 20,$a0 |
222 | fpu_gp_restore 21,$a0 |
222 | fpu_gp_restore 21,$a0 |
223 | fpu_gp_restore 22,$a0 |
223 | fpu_gp_restore 22,$a0 |
224 | fpu_gp_restore 23,$a0 |
224 | fpu_gp_restore 23,$a0 |
225 | fpu_gp_restore 24,$a0 |
225 | fpu_gp_restore 24,$a0 |
226 | fpu_gp_restore 25,$a0 |
226 | fpu_gp_restore 25,$a0 |
227 | fpu_gp_restore 26,$a0 |
227 | fpu_gp_restore 26,$a0 |
228 | fpu_gp_restore 27,$a0 |
228 | fpu_gp_restore 27,$a0 |
229 | fpu_gp_restore 28,$a0 |
229 | fpu_gp_restore 28,$a0 |
230 | fpu_gp_restore 29,$a0 |
230 | fpu_gp_restore 29,$a0 |
231 | fpu_gp_restore 30,$a0 |
231 | fpu_gp_restore 30,$a0 |
232 | fpu_gp_restore 31,$a0 |
232 | fpu_gp_restore 31,$a0 |
233 | 233 | ||
234 | fpu_ct_restore 1,$a0 |
234 | fpu_ct_restore 1,$a0 |
235 | fpu_ct_restore 2,$a0 |
235 | fpu_ct_restore 2,$a0 |
236 | fpu_ct_restore 3,$a0 |
236 | fpu_ct_restore 3,$a0 |
237 | fpu_ct_restore 4,$a0 |
237 | fpu_ct_restore 4,$a0 |
238 | fpu_ct_restore 5,$a0 |
238 | fpu_ct_restore 5,$a0 |
239 | fpu_ct_restore 6,$a0 |
239 | fpu_ct_restore 6,$a0 |
240 | fpu_ct_restore 7,$a0 |
240 | fpu_ct_restore 7,$a0 |
241 | fpu_ct_restore 8,$a0 |
241 | fpu_ct_restore 8,$a0 |
242 | fpu_ct_restore 9,$a0 |
242 | fpu_ct_restore 9,$a0 |
243 | fpu_ct_restore 10,$a0 |
243 | fpu_ct_restore 10,$a0 |
244 | fpu_ct_restore 11,$a0 |
244 | fpu_ct_restore 11,$a0 |
245 | fpu_ct_restore 12,$a0 |
245 | fpu_ct_restore 12,$a0 |
246 | fpu_ct_restore 13,$a0 |
246 | fpu_ct_restore 13,$a0 |
247 | fpu_ct_restore 14,$a0 |
247 | fpu_ct_restore 14,$a0 |
248 | fpu_ct_restore 15,$a0 |
248 | fpu_ct_restore 15,$a0 |
249 | fpu_ct_restore 16,$a0 |
249 | fpu_ct_restore 16,$a0 |
250 | fpu_ct_restore 17,$a0 |
250 | fpu_ct_restore 17,$a0 |
251 | fpu_ct_restore 18,$a0 |
251 | fpu_ct_restore 18,$a0 |
252 | fpu_ct_restore 19,$a0 |
252 | fpu_ct_restore 19,$a0 |
253 | fpu_ct_restore 20,$a0 |
253 | fpu_ct_restore 20,$a0 |
254 | fpu_ct_restore 21,$a0 |
254 | fpu_ct_restore 21,$a0 |
255 | fpu_ct_restore 22,$a0 |
255 | fpu_ct_restore 22,$a0 |
256 | fpu_ct_restore 23,$a0 |
256 | fpu_ct_restore 23,$a0 |
257 | fpu_ct_restore 24,$a0 |
257 | fpu_ct_restore 24,$a0 |
258 | fpu_ct_restore 25,$a0 |
258 | fpu_ct_restore 25,$a0 |
259 | fpu_ct_restore 26,$a0 |
259 | fpu_ct_restore 26,$a0 |
260 | fpu_ct_restore 27,$a0 |
260 | fpu_ct_restore 27,$a0 |
261 | fpu_ct_restore 28,$a0 |
261 | fpu_ct_restore 28,$a0 |
262 | fpu_ct_restore 29,$a0 |
262 | fpu_ct_restore 29,$a0 |
263 | fpu_ct_restore 30,$a0 |
263 | fpu_ct_restore 30,$a0 |
264 | fpu_ct_restore 31,$a0 |
264 | fpu_ct_restore 31,$a0 |
265 | #endif |
265 | #endif |
266 | j $ra |
266 | j $ra |
267 | nop |
267 | nop |
268 | 268 | ||
269 | 269 | ||
270 |
|
270 |
|
271 | 271 | ||
272 | 272 | ||
273 | 273 |