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Memory management
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Memory management
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=================
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=================
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1. Virtual Address Translation
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1.1 Hierarchical 4-level per address space page tables
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SPARTAN kernel deploys generic interface for 4-level page tables,
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SPARTAN kernel deploys generic interface for 4-level page tables
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for these architectures: amd64, ia32, mips32 and ppc32. In this
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no matter what the real underlying hardware architecture is.
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setting, page tables are hierarchical and are not shared by
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address spaces (i.e. one set of page tables per address space).
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 VADDR
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 VADDR
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 +-----------------------------------------------------------------------------+
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 +-----------------------------------------------------------------------------+
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 |   PTL0_INDEX  |   PTL1_INDEX   |   PTL2_INDEX   |   PTL3_INDEX   |   OFFSET |
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 |   PTL0_INDEX  |   PTL1_INDEX   |   PTL2_INDEX   |   PTL3_INDEX   |   OFFSET |
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 +-----------------------------------------------------------------------------+
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 +-----------------------------------------------------------------------------+
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 PTL0                   PTL1                   PTL2                   PTL3
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 PTL0                   PTL1                   PTL2                   PTL3
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 +--------+             +--------+             +--------+             +--------+
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 +--------+             +--------+             +--------+             +--------+
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 |        |             |        |             |  PTL3  | -----\      |        |
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 |        |             |        |             |  PTL3  | -----\      |        |
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 |        |             |        |             +--------+      |      |        |
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 |        |             |        |             +--------+      |      |        |
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 |        |             +--------+             |        |      |      |        |
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 |        |             +--------+             |        |      |      |        |
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 |        |             |  PTL2  | -----\      |        |      |      |        |
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 |        |             |  PTL2  | -----\      |        |      |      |        |
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 |        |             +--------+      |      |        |      |      |        |
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 |        |             +--------+      |      |        |      |      |        |
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 |        |             |        |      |      |        |      |      +--------+
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 |        |             |        |      |      |        |      |      +--------+
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 +--------+             |        |      |      |        |      |      | FRAME  |
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 +--------+             |        |      |      |        |      |      | FRAME  |
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 |  PTL1  | -----\      |        |      |      |        |      |      +--------+
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 |  PTL1  | -----\      |        |      |      |        |      |      +--------+
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 +--------+      |      |        |      |      |        |      |      |        |
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 +--------+      |      |        |      |      |        |      |      |        |
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 |        |      |      |        |      |      |        |      |      |        |
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 |        |      |      |        |      |      |        |      |      |        |
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 |        |      |      |        |      |      |        |      |      |        |
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 |        |      |      |        |      |      |        |      |      |        |
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 +--------+      \----> +--------+      \----> +--------+      \----> +--------+
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 +--------+      \----> +--------+      \----> +--------+      \----> +--------+
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     ^
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     ^
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     |
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     |
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     |
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     |
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 +--------+
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 +--------+
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 |  PTL0  |
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 |  PTL0  |
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 +--------+
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 +--------+
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PTL0		Page Table Level 0 (Page Directory)
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PTL0		Page Table Level 0 (Page Directory)
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PTL1		Page Table Level 1
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PTL1		Page Table Level 1
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PTL2		Page Table Level 2
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PTL2		Page Table Level 2
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PTL3		Page Table Level 3
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PTL3		Page Table Level 3
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PTL0_INDEX	Index into PTL0
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PTL0_INDEX	Index into PTL0
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PTL1_INDEX	Index into PTL1
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PTL1_INDEX	Index into PTL1
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PTL2_INDEX	Index into PTL2
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PTL2_INDEX	Index into PTL2
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PTL3_INDEX	Index into PTL3
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PTL3_INDEX	Index into PTL3
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VADDR		Virtual address for which mapping is looked up
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VADDR		Virtual address for which mapping is looked up
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FRAME		Physical address of memory frame to which VADDR is mapped
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FRAME		Physical address of memory frame to which VADDR is mapped
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On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are
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On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are
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left out. TLB-only architectures are to define custom format for software page
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left out. TLB-only architectures are to define custom format for software page
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tables.
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tables.
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1.2 Single global page hash table
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Generic page hash table interface is deployed on 64-bit architectures without
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implied hardware support for hierarchical page tables, i.e. ia64 and sparc64.
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There is only one global page hash table in the system shared by all address
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spaces.
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