WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <mm/asid.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
 
#include <arch/drivers/fb.h>
#include <arch/drivers/i8042.h>
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
/** Initialize ITLB and DTLB.
 *
 * The goal of this function is to disable MMU
 * so that both TLBs can be purged and new
 * kernel 4M locked entry can be installed.
 * After TLB is initialized, MMU is enabled
 * again.
 *
 * Switching MMU off imposes the requirement for
 * the kernel to run in identity mapped environment.
 */
void tlb_arch_init(void)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    frame_address_t fr;
    page_address_t pg;
 
    fr.address = config.base;
    pg.address = config.base;
 
    immu_disable();
    dmmu_disable();
   
    /*
     * We do identity mapping of 4M-page at 4M.
     */
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    itlb_tag_access_write(tag.value);
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 1;
    data.cv = 1;
    data.p = true;
    data.w = true;
    data.g = true;
 
    itlb_data_in_write(data.value);
    dtlb_data_in_write(data.value);
 
    /*
     * Register window traps can occur before MMU is enabled again.
     * This ensures that any such traps will be handled from
     * kernel identity mapped trap handler.
     */
    trap_switch_trap_table();
   
    tlb_invalidate_all();
 
    dmmu_enable();
    immu_enable();
}
 
 
 
 
 
 
 
 
 
 
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
 
 
 
 
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
    data.cv = cacheable;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
    tlb_tag_access_reg_t tag;
 
    __address tpc;
    char *tpc_str;
 
    tag.value = dtlb_tag_access_read();
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
        tpc = tpc_read();
        tpc_str = get_symtab_entry(tpc);
 
        printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
        printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
        panic("%s\n", __FUNCTION__);
    }
 
    /*
     * Identity map piece of faulting kernel address space.
     */
 
 
 
 
 
 
 
 
 
 
 
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
   
    for (i = 0; i < cnt; i++) {
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    }
}
 

Rev 895	Rev 897
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <mm/tlb.h>	30	#include <mm/tlb.h>
31	#include <arch/mm/frame.h>	31	#include <arch/mm/frame.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <arch/mm/mmu.h>	33	#include <arch/mm/mmu.h>
34	#include <mm/asid.h>	34	#include <mm/asid.h>
35	#include <print.h>	35	#include <print.h>
36	#include <arch/types.h>	36	#include <arch/types.h>
37	#include <typedefs.h>	37	#include <typedefs.h>
38	#include <config.h>	38	#include <config.h>
39	#include <arch/trap/trap.h>	39	#include <arch/trap/trap.h>
40	#include <panic.h>	40	#include <panic.h>
41	#include <arch/asm.h>	41	#include <arch/asm.h>
42	#include <symtab.h>	42	#include <symtab.h>
43		43
44	#include <arch/drivers/fb.h>	44	#include <arch/drivers/fb.h>
45	#include <arch/drivers/i8042.h>	45	#include <arch/drivers/i8042.h>
46		46
47	char *context_encoding[] = {	47	char *context_encoding[] = {
48	"Primary",	48	"Primary",
49	"Secondary",	49	"Secondary",
50	"Nucleus",	50	"Nucleus",
51	"Reserved"	51	"Reserved"
52	};	52	};
53		53
54	/** Initialize ITLB and DTLB.	54	/** Initialize ITLB and DTLB.
55	*	55	*
56	* The goal of this function is to disable MMU	56	* The goal of this function is to disable MMU
57	* so that both TLBs can be purged and new	57	* so that both TLBs can be purged and new
58	* kernel 4M locked entry can be installed.	58	* kernel 4M locked entry can be installed.
59	* After TLB is initialized, MMU is enabled	59	* After TLB is initialized, MMU is enabled
60	* again.	60	* again.
61	*	61	*
62	* Switching MMU off imposes the requirement for	62	* Switching MMU off imposes the requirement for
63	* the kernel to run in identity mapped environment.	63	* the kernel to run in identity mapped environment.
64	*/	64	*/
65	void tlb_arch_init(void)	65	void tlb_arch_init(void)
66	{	66	{
67	tlb_tag_access_reg_t tag;	67	tlb_tag_access_reg_t tag;
68	tlb_data_t data;	68	tlb_data_t data;
69	frame_address_t fr;	69	frame_address_t fr;
70	page_address_t pg;	70	page_address_t pg;
71		71
72	fr.address = config.base;	72	fr.address = config.base;
73	pg.address = config.base;	73	pg.address = config.base;
74		74
75	immu_disable();	75	immu_disable();
76	dmmu_disable();	76	dmmu_disable();
77		77
78	/*	78	/*
79	* We do identity mapping of 4M-page at 4M.	79	* We do identity mapping of 4M-page at 4M.
80	*/	80	*/
81	tag.value = ASID_KERNEL;	81	tag.value = ASID_KERNEL;
82	tag.vpn = pg.vpn;	82	tag.vpn = pg.vpn;
83		83
84	itlb_tag_access_write(tag.value);	84	itlb_tag_access_write(tag.value);
85	dtlb_tag_access_write(tag.value);	85	dtlb_tag_access_write(tag.value);
86		86
87	data.value = 0;	87	data.value = 0;
88	data.v = true;	88	data.v = true;
89	data.size = PAGESIZE_4M;	89	data.size = PAGESIZE_4M;
90	data.pfn = fr.pfn;	90	data.pfn = fr.pfn;
91	data.l = true;	91	data.l = true;
92	data.cp = 1;	92	data.cp = 1;
93	data.cv = 1;	93	data.cv = 1;
94	data.p = true;	94	data.p = true;
95	data.w = true;	95	data.w = true;
96	data.g = true;	96	data.g = true;
97		97
98	itlb_data_in_write(data.value);	98	itlb_data_in_write(data.value);
99	dtlb_data_in_write(data.value);	99	dtlb_data_in_write(data.value);
100		100
101	/*	101	/*
102	* Register window traps can occur before MMU is enabled again.	102	* Register window traps can occur before MMU is enabled again.
103	* This ensures that any such traps will be handled from	103	* This ensures that any such traps will be handled from
104	* kernel identity mapped trap handler.	104	* kernel identity mapped trap handler.
105	*/	105	*/
106	trap_switch_trap_table();	106	trap_switch_trap_table();
107		107
108	tlb_invalidate_all();	108	tlb_invalidate_all();
109		109
110	dmmu_enable();	110	dmmu_enable();
111	immu_enable();	111	immu_enable();
112		112	}
113	/*	-
114	* Quick hack: map frame buffer	-
115	*/	-
116	fr.address = FB_PHYS_ADDRESS;	-
117	pg.address = FB_VIRT_ADDRESS;	-
118		-
119	tag.value = ASID_KERNEL;	-
120	tag.vpn = pg.vpn;	-
121		-
122	dtlb_tag_access_write(tag.value);	-
123		113
124	data.value = 0;	114	/** Insert privileged mapping into DMMU TLB.
125	data.v = true;	115	*
126	data.size = PAGESIZE_4M;	116	* @param page Virtual page address.
127	data.pfn = fr.pfn;	117	* @param frame Physical frame address.
128	data.l = true;	118	* @param pagesize Page size.
-		119	* @param locked True for permanent mappings, false otherwise.
-		120	* @param cacheable True if the mapping is cacheable, false otherwise.
129	data.cp = 0;	121	*/
-		122	void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
-		123	{
130	data.cv = 0;	124	tlb_tag_access_reg_t tag;
131	data.p = true;	125	tlb_data_t data;
132	data.w = true;	126	page_address_t pg;
133	data.g = true;	127	frame_address_t fr;
134		128
135	dtlb_data_in_write(data.value);	-
136		-
137	/*	-
138	* Quick hack: map keyboard	-
139	*/	-
140	fr.address = KBD_PHYS_ADDRESS;	129	pg.address = page;
141	pg.address = KBD_VIRT_ADDRESS;	130	fr.address = frame;
142		131
143	tag.value = ASID_KERNEL;	132	tag.value = ASID_KERNEL;
144	tag.vpn = pg.vpn;	133	tag.vpn = pg.vpn;
145		134
146	dtlb_tag_access_write(tag.value);	135	dtlb_tag_access_write(tag.value);
147		136
148	data.value = 0;	137	data.value = 0;
149	data.v = true;	138	data.v = true;
150	data.size = PAGESIZE_8K;	139	data.size = pagesize;
151	data.pfn = fr.pfn;	140	data.pfn = fr.pfn;
152	data.l = true;	141	data.l = locked;
153	data.cp = 0;	142	data.cp = cacheable;
154	data.cv = 0;	143	data.cv = cacheable;
155	data.p = true;	144	data.p = true;
156	data.w = true;	145	data.w = true;
157	data.g = true;	146	data.g = true;
158		147
159	dtlb_data_in_write(data.value);	148	dtlb_data_in_write(data.value);
160	}	149	}
161		150
162	/** ITLB miss handler. */	151	/** ITLB miss handler. */
163	void fast_instruction_access_mmu_miss(void)	152	void fast_instruction_access_mmu_miss(void)
164	{	153	{
165	panic("%s\n", __FUNCTION__);	154	panic("%s\n", __FUNCTION__);
166	}	155	}
167		156
168	/** DTLB miss handler. */	157	/** DTLB miss handler. */
169	void fast_data_access_mmu_miss(void)	158	void fast_data_access_mmu_miss(void)
170	{	159	{
171	tlb_tag_access_reg_t tag;	160	tlb_tag_access_reg_t tag;
172	tlb_data_t data;	-
173	__address tpc;	161	__address tpc;
174	char *tpc_str;	162	char *tpc_str;
175		163
176	tag.value = dtlb_tag_access_read();	164	tag.value = dtlb_tag_access_read();
177	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {	165	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {
178	tpc = tpc_read();	166	tpc = tpc_read();
179	tpc_str = get_symtab_entry(tpc);	167	tpc_str = get_symtab_entry(tpc);
180		168
181	printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);	169	printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
182	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");	170	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
183	panic("%s\n", __FUNCTION__);	171	panic("%s\n", __FUNCTION__);
184	}	172	}
185		173
186	/*	174	/*
187	* Identity map piece of faulting kernel address space.	175	* Identity map piece of faulting kernel address space.
188	*/	176	*/
189	data.value = 0;	-
190	data.v = true;	-
191	data.size = PAGESIZE_8K;	-
192	data.pfn = tag.vpn;	-
193	data.l = false;	-
194	data.cp = 1;	-
195	data.cv = 1;	-
196	data.p = true;	-
197	data.w = true;	-
198	data.g = true;	-
199		-
200	dtlb_data_in_write(data.value);	177	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
201	}	178	}
202		179
203	/** DTLB protection fault handler. */	180	/** DTLB protection fault handler. */
204	void fast_data_access_protection(void)	181	void fast_data_access_protection(void)
205	{	182	{
206	panic("%s\n", __FUNCTION__);	183	panic("%s\n", __FUNCTION__);
207	}	184	}
208		185
209	/** Print contents of both TLBs. */	186	/** Print contents of both TLBs. */
210	void tlb_print(void)	187	void tlb_print(void)
211	{	188	{
212	int i;	189	int i;
213	tlb_data_t d;	190	tlb_data_t d;
214	tlb_tag_read_reg_t t;	191	tlb_tag_read_reg_t t;
215		192
216	printf("I-TLB contents:\n");	193	printf("I-TLB contents:\n");
217	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	194	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
218	d.value = itlb_data_access_read(i);	195	d.value = itlb_data_access_read(i);
219	t.value = itlb_tag_read_read(i);	196	t.value = itlb_tag_read_read(i);
220		197
221	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	198	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
222	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	199	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
223	}	200	}
224		201
225	printf("D-TLB contents:\n");	202	printf("D-TLB contents:\n");
226	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	203	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
227	d.value = dtlb_data_access_read(i);	204	d.value = dtlb_data_access_read(i);
228	t.value = dtlb_tag_read_read(i);	205	t.value = dtlb_tag_read_read(i);
229		206
230	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	207	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
231	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	208	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
232	}	209	}
233		210
234	}	211	}
235		212
236	/** Invalidate all unlocked ITLB and DTLB entries. */	213	/** Invalidate all unlocked ITLB and DTLB entries. */
237	void tlb_invalidate_all(void)	214	void tlb_invalidate_all(void)
238	{	215	{
239	int i;	216	int i;
240	tlb_data_t d;	217	tlb_data_t d;
241	tlb_tag_read_reg_t t;	218	tlb_tag_read_reg_t t;
242		219
243	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	220	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
244	d.value = itlb_data_access_read(i);	221	d.value = itlb_data_access_read(i);
245	if (!d.l) {	222	if (!d.l) {
246	t.value = itlb_tag_read_read(i);	223	t.value = itlb_tag_read_read(i);
247	d.v = false;	224	d.v = false;
248	itlb_tag_access_write(t.value);	225	itlb_tag_access_write(t.value);
249	itlb_data_access_write(i, d.value);	226	itlb_data_access_write(i, d.value);
250	}	227	}
251	}	228	}
252		229
253	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	230	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
254	d.value = dtlb_data_access_read(i);	231	d.value = dtlb_data_access_read(i);
255	if (!d.l) {	232	if (!d.l) {
256	t.value = dtlb_tag_read_read(i);	233	t.value = dtlb_tag_read_read(i);
257	d.v = false;	234	d.v = false;
258	dtlb_tag_access_write(t.value);	235	dtlb_tag_access_write(t.value);
259	dtlb_data_access_write(i, d.value);	236	dtlb_data_access_write(i, d.value);
260	}	237	}
261	}	238	}
262		239
263	}	240	}
264		241
265	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	242	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
266	*	243	*
267	* @param asid Address Space ID.	244	* @param asid Address Space ID.
268	*/	245	*/
269	void tlb_invalidate_asid(asid_t asid)	246	void tlb_invalidate_asid(asid_t asid)
270	{	247	{
271	/* TODO: write asid to some Context register and encode the register in second parameter below. */	248	/* TODO: write asid to some Context register and encode the register in second parameter below. */
272	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	249	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
273	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	250	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
274	}	251	}
275		252
276	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	253	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
277	*	254	*
278	* @param asid Address Space ID.	255	* @param asid Address Space ID.
279	* @param page First page which to sweep out from ITLB and DTLB.	256	* @param page First page which to sweep out from ITLB and DTLB.
280	* @param cnt Number of ITLB and DTLB entries to invalidate.	257	* @param cnt Number of ITLB and DTLB entries to invalidate.
281	*/	258	*/
282	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	259	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
283	{	260	{
284	int i;	261	int i;
285		262
286	for (i = 0; i < cnt; i++) {	263	for (i = 0; i < cnt; i++) {
287	/* TODO: write asid to some Context register and encode the register in second parameter below. */	264	/* TODO: write asid to some Context register and encode the register in second parameter below. */
288	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	265	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
289	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	266	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
290	}	267	}
291	}	268	}
292		269

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(root)/kernel/trunk/arch/sparc64/src/mm/tlb.c – Rev 895 → 897