WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <mm/asid.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
/** Initialize ITLB and DTLB.
 *
 * The goal of this function is to disable MMU
 * so that both TLBs can be purged and new
 * kernel 4M locked entry can be installed.
 * After TLB is initialized, MMU is enabled
 * again.
 *
 * Switching MMU off imposes the requirement for
 * the kernel to run in identity mapped environment.
 */
void tlb_arch_init(void)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    frame_address_t fr;
    page_address_t pg;
 
    fr.address = config.base;
    pg.address = config.base;
 
    immu_disable();
    dmmu_disable();
   
    /*
     * We do identity mapping of 4M-page at 4M.
     */
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    itlb_tag_access_write(tag.value);
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 1;
    data.cv = 1;
    data.p = true;
    data.w = true;
    data.g = true;
 
    itlb_data_in_write(data.value);
    dtlb_data_in_write(data.value);
 
    /*
     * Register window traps can occur before MMU is enabled again.
     * This ensures that any such traps will be handled from
     * kernel identity mapped trap handler.
     */
    trap_switch_trap_table();
   
    tlb_invalidate_all();
 
    dmmu_enable();
    immu_enable();
   
    /*
     * Quick hack: map frame buffer
     */
    fr.address = 0x1C901000000ULL;
    pg.address = 0xc0000000;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 0;
    data.cv = 0;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
 
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    __address tpc;
    char *tpc_str;
   
    tag.value = dtlb_tag_access_read();
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
        tpc = tpc_read();
        tpc_str = get_symtab_entry(tpc);
 
 
        printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
        printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
        panic("%s\n", __FUNCTION__);
    }
 
    /*
     * Identity map piece of faulting kernel address space.
     */
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = tag.vpn;
    data.l = false;
    data.cp = 1;
    data.cv = 1;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
   
    for (i = 0; i < cnt; i++) {
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    }
}
 

Rev 873	Rev 877
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <mm/tlb.h>	30	#include <mm/tlb.h>
31	#include <arch/mm/frame.h>	31	#include <arch/mm/frame.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <arch/mm/mmu.h>	33	#include <arch/mm/mmu.h>
-		34	#include <mm/asid.h>
34	#include <print.h>	35	#include <print.h>
35	#include <arch/types.h>	36	#include <arch/types.h>
36	#include <typedefs.h>	37	#include <typedefs.h>
37	#include <config.h>	38	#include <config.h>
38	#include <arch/trap/trap.h>	39	#include <arch/trap/trap.h>
39	#include <panic.h>	40	#include <panic.h>
40	#include <arch/asm.h>	41	#include <arch/asm.h>
41	#include <symtab.h>	42	#include <symtab.h>
42		43
43	char *context_encoding[] = {	44	char *context_encoding[] = {
44	"Primary",	45	"Primary",
45	"Secondary",	46	"Secondary",
46	"Nucleus",	47	"Nucleus",
47	"Reserved"	48	"Reserved"
48	};	49	};
49		50
50	/** Initialize ITLB and DTLB.	51	/** Initialize ITLB and DTLB.
51	*	52	*
52	* The goal of this function is to disable MMU	53	* The goal of this function is to disable MMU
53	* so that both TLBs can be purged and new	54	* so that both TLBs can be purged and new
54	* kernel 4M locked entry can be installed.	55	* kernel 4M locked entry can be installed.
55	* After TLB is initialized, MMU is enabled	56	* After TLB is initialized, MMU is enabled
56	* again.	57	* again.
57	*	58	*
58	* Switching MMU off imposes the requirement for	59	* Switching MMU off imposes the requirement for
59	* the kernel to run in identity mapped environment.	60	* the kernel to run in identity mapped environment.
60	*/	61	*/
61	void tlb_arch_init(void)	62	void tlb_arch_init(void)
62	{	63	{
63	tlb_tag_access_reg_t tag;	64	tlb_tag_access_reg_t tag;
64	tlb_data_t data;	65	tlb_data_t data;
65	frame_address_t fr;	66	frame_address_t fr;
66	page_address_t pg;	67	page_address_t pg;
67		68
68	fr.address = config.base;	69	fr.address = config.base;
69	pg.address = config.base;	70	pg.address = config.base;
70		71
71	immu_disable();	72	immu_disable();
72	dmmu_disable();	73	dmmu_disable();
73		74
74	/*	75	/*
75	* We do identity mapping of 4M-page at 4M.	76	* We do identity mapping of 4M-page at 4M.
76	*/	77	*/
77	tag.value = 0;	78	tag.value = ASID_KERNEL;
78	tag.vpn = pg.vpn;	79	tag.vpn = pg.vpn;
79		80
80	itlb_tag_access_write(tag.value);	81	itlb_tag_access_write(tag.value);
81	dtlb_tag_access_write(tag.value);	82	dtlb_tag_access_write(tag.value);
82		83
83	data.value = 0;	84	data.value = 0;
84	data.v = true;	85	data.v = true;
85	data.size = PAGESIZE_4M;	86	data.size = PAGESIZE_4M;
86	data.pfn = fr.pfn;	87	data.pfn = fr.pfn;
87	data.l = true;	88	data.l = true;
88	data.cp = 1;	89	data.cp = 1;
89	data.cv = 1;	90	data.cv = 1;
90	data.p = true;	91	data.p = true;
91	data.w = true;	92	data.w = true;
92	data.g = true;	93	data.g = true;
93		94
94	itlb_data_in_write(data.value);	95	itlb_data_in_write(data.value);
95	dtlb_data_in_write(data.value);	96	dtlb_data_in_write(data.value);
96		97
97	/*	98	/*
98	* Register window traps can occur before MMU is enabled again.	99	* Register window traps can occur before MMU is enabled again.
99	* This ensures that any such traps will be handled from	100	* This ensures that any such traps will be handled from
100	* kernel identity mapped trap handler.	101	* kernel identity mapped trap handler.
101	*/	102	*/
102	trap_switch_trap_table();	103	trap_switch_trap_table();
103		104
104	tlb_invalidate_all();	105	tlb_invalidate_all();
105		106
106	dmmu_enable();	107	dmmu_enable();
107	immu_enable();	108	immu_enable();
108		109
109	/*	110	/*
110	* Quick hack: map frame buffer	111	* Quick hack: map frame buffer
111	*/	112	*/
112	fr.address = 0x1C901000000ULL;	113	fr.address = 0x1C901000000ULL;
113	pg.address = 0xc0000000;	114	pg.address = 0xc0000000;
114		115
115	tag.value = 0;	116	tag.value = ASID_KERNEL;
116	tag.vpn = pg.vpn;	117	tag.vpn = pg.vpn;
117		118
118	dtlb_tag_access_write(tag.value);	119	dtlb_tag_access_write(tag.value);
119		120
120	data.value = 0;	121	data.value = 0;
121	data.v = true;	122	data.v = true;
122	data.size = PAGESIZE_4M;	123	data.size = PAGESIZE_4M;
123	data.pfn = fr.pfn;	124	data.pfn = fr.pfn;
124	data.l = true;	125	data.l = true;
125	data.cp = 0;	126	data.cp = 0;
126	data.cv = 0;	127	data.cv = 0;
127	data.p = true;	128	data.p = true;
128	data.w = true;	129	data.w = true;
129	data.g = true;	130	data.g = true;
130		131
131	dtlb_data_in_write(data.value);	132	dtlb_data_in_write(data.value);
132		133
133	}	134	}
134		135
135	/** ITLB miss handler. */	136	/** ITLB miss handler. */
136	void fast_instruction_access_mmu_miss(void)	137	void fast_instruction_access_mmu_miss(void)
137	{	138	{
138	panic("%s\n", __FUNCTION__);	139	panic("%s\n", __FUNCTION__);
139	}	140	}
140		141
141	/** DTLB miss handler. */	142	/** DTLB miss handler. */
142	void fast_data_access_mmu_miss(void)	143	void fast_data_access_mmu_miss(void)
143	{	144	{
144	tlb_sfsr_reg_t status;	145	tlb_tag_access_reg_t tag;
-		146	tlb_data_t data;
145	__address address, tpc;	147	__address tpc;
146	char *tpc_str;	148	char *tpc_str;
147		149
148	status.value = dtlb_sfsr_read();	150	tag.value = dtlb_tag_access_read();
149	address = dtlb_sfar_read();	151	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {
150	tpc = tpc_read();	152	tpc = tpc_read();
151	tpc_str = get_symtab_entry(tpc);	153	tpc_str = get_symtab_entry(tpc);
152		154
153	printf("ASI=%B, Context=%s\n", status.asi, context_encoding[status.ct]);	-
154	printf("Faulting address: %P\n", dtlb_sfar_read());	155	printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
155	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");	156	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
156	panic("%s\n", __FUNCTION__);	157	panic("%s\n", __FUNCTION__);
-		158	}
-		159
-		160	/*
-		161	* Identity map piece of faulting kernel address space.
-		162	*/
-		163	data.value = 0;
-		164	data.v = true;
-		165	data.size = PAGESIZE_8K;
-		166	data.pfn = tag.vpn;
-		167	data.l = false;
-		168	data.cp = 1;
-		169	data.cv = 1;
-		170	data.p = true;
-		171	data.w = true;
-		172	data.g = true;
-		173
-		174	dtlb_data_in_write(data.value);
157	}	175	}
158		176
159	/** DTLB protection fault handler. */	177	/** DTLB protection fault handler. */
160	void fast_data_access_protection(void)	178	void fast_data_access_protection(void)
161	{	179	{
162	panic("%s\n", __FUNCTION__);	180	panic("%s\n", __FUNCTION__);
163	}	181	}
164		182
165	/** Print contents of both TLBs. */	183	/** Print contents of both TLBs. */
166	void tlb_print(void)	184	void tlb_print(void)
167	{	185	{
168	int i;	186	int i;
169	tlb_data_t d;	187	tlb_data_t d;
170	tlb_tag_read_reg_t t;	188	tlb_tag_read_reg_t t;
171		189
172	printf("I-TLB contents:\n");	190	printf("I-TLB contents:\n");
173	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	191	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
174	d.value = itlb_data_access_read(i);	192	d.value = itlb_data_access_read(i);
175	t.value = itlb_tag_read_read(i);	193	t.value = itlb_tag_read_read(i);
176		194
177	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	195	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
178	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	196	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
179	}	197	}
180		198
181	printf("D-TLB contents:\n");	199	printf("D-TLB contents:\n");
182	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	200	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
183	d.value = dtlb_data_access_read(i);	201	d.value = dtlb_data_access_read(i);
184	t.value = dtlb_tag_read_read(i);	202	t.value = dtlb_tag_read_read(i);
185		203
186	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	204	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
187	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	205	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
188	}	206	}
189		207
190	}	208	}
191		209
192	/** Invalidate all unlocked ITLB and DTLB entries. */	210	/** Invalidate all unlocked ITLB and DTLB entries. */
193	void tlb_invalidate_all(void)	211	void tlb_invalidate_all(void)
194	{	212	{
195	int i;	213	int i;
196	tlb_data_t d;	214	tlb_data_t d;
197	tlb_tag_read_reg_t t;	215	tlb_tag_read_reg_t t;
198		216
199	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	217	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
200	d.value = itlb_data_access_read(i);	218	d.value = itlb_data_access_read(i);
201	if (!d.l) {	219	if (!d.l) {
202	t.value = itlb_tag_read_read(i);	220	t.value = itlb_tag_read_read(i);
203	d.v = false;	221	d.v = false;
204	itlb_tag_access_write(t.value);	222	itlb_tag_access_write(t.value);
205	itlb_data_access_write(i, d.value);	223	itlb_data_access_write(i, d.value);
206	}	224	}
207	}	225	}
208		226
209	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	227	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
210	d.value = dtlb_data_access_read(i);	228	d.value = dtlb_data_access_read(i);
211	if (!d.l) {	229	if (!d.l) {
212	t.value = dtlb_tag_read_read(i);	230	t.value = dtlb_tag_read_read(i);
213	d.v = false;	231	d.v = false;
214	dtlb_tag_access_write(t.value);	232	dtlb_tag_access_write(t.value);
215	dtlb_data_access_write(i, d.value);	233	dtlb_data_access_write(i, d.value);
216	}	234	}
217	}	235	}
218		236
219	}	237	}
220		238
221	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	239	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
222	*	240	*
223	* @param asid Address Space ID.	241	* @param asid Address Space ID.
224	*/	242	*/
225	void tlb_invalidate_asid(asid_t asid)	243	void tlb_invalidate_asid(asid_t asid)
226	{	244	{
227	/* TODO: write asid to some Context register and encode the register in second parameter below. */	245	/* TODO: write asid to some Context register and encode the register in second parameter below. */
228	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	246	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
229	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	247	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
230	}	248	}
231		249
232	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	250	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
233	*	251	*
234	* @param asid Address Space ID.	252	* @param asid Address Space ID.
235	* @param page First page which to sweep out from ITLB and DTLB.	253	* @param page First page which to sweep out from ITLB and DTLB.
236	* @param cnt Number of ITLB and DTLB entries to invalidate.	254	* @param cnt Number of ITLB and DTLB entries to invalidate.
237	*/	255	*/
238	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	256	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
239	{	257	{
240	int i;	258	int i;
241		259
242	for (i = 0; i < cnt; i++) {	260	for (i = 0; i < cnt; i++) {
243	/* TODO: write asid to some Context register and encode the register in second parameter below. */	261	/* TODO: write asid to some Context register and encode the register in second parameter below. */
244	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	262	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
245	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	263	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
246	}	264	}
247	}	265	}
248		266

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(root)/kernel/trunk/arch/sparc64/src/mm/tlb.c – Rev 873 → 877