WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
/** Initialize ITLB and DTLB.
 *
 * The goal of this function is to disable MMU
 * so that both TLBs can be purged and new
 * kernel 4M locked entry can be installed.
 * After TLB is initialized, MMU is enabled
 * again.
 *
 * Switching MMU off imposes the requirement for
 * the kernel to run in identity mapped environment.
 */
void tlb_arch_init(void)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    frame_address_t fr;
    page_address_t pg;
 
    fr.address = config.base;
    pg.address = config.base;
 
    immu_disable();
    dmmu_disable();
   
    /*
     * We do identity mapping of 4M-page at 4M.
     */
    tag.value = 0;
    tag.vpn = pg.vpn;
 
    itlb_tag_access_write(tag.value);
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 1;
    data.cv = 1;
    data.p = true;
    data.w = true;
    data.g = true;
 
    itlb_data_in_write(data.value);
    dtlb_data_in_write(data.value);
 
    /*
     * Register window traps can occur before MMU is enabled again.
     * This ensures that any such traps will be handled from
     * kernel identity mapped trap handler.
     */
    trap_switch_trap_table();
   
    tlb_invalidate_all();
 
    dmmu_enable();
    immu_enable();
   
    /*
     * Quick hack: map frame buffer
     */
    fr.address = 0x1C901000000ULL;
    pg.address = 0xc0000000;
 
    tag.value = 0;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 0;
    data.cv = 0;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
 
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
    tlb_sfsr_reg_t status;
    __address address, tpc;
    char *tpc_str;
   
    status.value = dtlb_sfsr_read();
    address = dtlb_sfar_read();
    tpc = tpc_read();
    tpc_str = get_symtab_entry(tpc);
 
    printf("ASI=%B, Context=%s\n", status.asi, context_encoding[status.ct]);
    printf("Faulting address: %P\n", dtlb_sfar_read());
    printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
   
    for (i = 0; i < cnt; i++) {
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    }
}
 

Rev 863	Rev 873
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <mm/tlb.h>	30	#include <mm/tlb.h>
31	#include <arch/mm/frame.h>	31	#include <arch/mm/frame.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <arch/mm/mmu.h>	33	#include <arch/mm/mmu.h>
34	#include <print.h>	34	#include <print.h>
35	#include <arch/types.h>	35	#include <arch/types.h>
36	#include <typedefs.h>	36	#include <typedefs.h>
37	#include <config.h>	37	#include <config.h>
38	#include <arch/trap/trap.h>	38	#include <arch/trap/trap.h>
39	#include <panic.h>	39	#include <panic.h>
-		40	#include <arch/asm.h>
-		41	#include <symtab.h>
-		42
-		43	char *context_encoding[] = {
-		44	"Primary",
-		45	"Secondary",
-		46	"Nucleus",
-		47	"Reserved"
-		48	};
40		49
41	/** Initialize ITLB and DTLB.	50	/** Initialize ITLB and DTLB.
42	*	51	*
43	* The goal of this function is to disable MMU	52	* The goal of this function is to disable MMU
44	* so that both TLBs can be purged and new	53	* so that both TLBs can be purged and new
45	* kernel 4M locked entry can be installed.	54	* kernel 4M locked entry can be installed.
46	* After TLB is initialized, MMU is enabled	55	* After TLB is initialized, MMU is enabled
47	* again.	56	* again.
48	*	57	*
49	* Switching MMU off imposes the requirement for	58	* Switching MMU off imposes the requirement for
50	* the kernel to run in identity mapped environment.	59	* the kernel to run in identity mapped environment.
51	*/	60	*/
52	void tlb_arch_init(void)	61	void tlb_arch_init(void)
53	{	62	{
54	tlb_tag_access_reg_t tag;	63	tlb_tag_access_reg_t tag;
55	tlb_data_t data;	64	tlb_data_t data;
56	frame_address_t fr;	65	frame_address_t fr;
57	page_address_t pg;	66	page_address_t pg;
58		67
59	fr.address = config.base;	68	fr.address = config.base;
60	pg.address = config.base;	69	pg.address = config.base;
61		70
62	immu_disable();	71	immu_disable();
63	dmmu_disable();	72	dmmu_disable();
64		73
65	/*	74	/*
66	* We do identity mapping of 4M-page at 4M.	75	* We do identity mapping of 4M-page at 4M.
67	*/	76	*/
68	tag.value = 0;	77	tag.value = 0;
69	tag.vpn = pg.vpn;	78	tag.vpn = pg.vpn;
70		79
71	itlb_tag_access_write(tag.value);	80	itlb_tag_access_write(tag.value);
72	dtlb_tag_access_write(tag.value);	81	dtlb_tag_access_write(tag.value);
73		82
74	data.value = 0;	83	data.value = 0;
75	data.v = true;	84	data.v = true;
76	data.size = PAGESIZE_4M;	85	data.size = PAGESIZE_4M;
77	data.pfn = fr.pfn;	86	data.pfn = fr.pfn;
78	data.l = true;	87	data.l = true;
79	data.cp = 1;	88	data.cp = 1;
80	data.cv = 1;	89	data.cv = 1;
81	data.p = true;	90	data.p = true;
82	data.w = true;	91	data.w = true;
83	data.g = true;	92	data.g = true;
84		93
85	itlb_data_in_write(data.value);	94	itlb_data_in_write(data.value);
86	dtlb_data_in_write(data.value);	95	dtlb_data_in_write(data.value);
87		96
88	/*	97	/*
89	* Register window traps can occur before MMU is enabled again.	98	* Register window traps can occur before MMU is enabled again.
90	* This ensures that any such traps will be handled from	99	* This ensures that any such traps will be handled from
91	* kernel identity mapped trap handler.	100	* kernel identity mapped trap handler.
92	*/	101	*/
93	trap_switch_trap_table();	102	trap_switch_trap_table();
94		103
95	tlb_invalidate_all();	104	tlb_invalidate_all();
96		105
97	dmmu_enable();	106	dmmu_enable();
98	immu_enable();	107	immu_enable();
-		108
-		109	/*
-		110	* Quick hack: map frame buffer
-		111	*/
-		112	fr.address = 0x1C901000000ULL;
-		113	pg.address = 0xc0000000;
-		114
-		115	tag.value = 0;
-		116	tag.vpn = pg.vpn;
-		117
-		118	dtlb_tag_access_write(tag.value);
-		119
-		120	data.value = 0;
-		121	data.v = true;
-		122	data.size = PAGESIZE_4M;
-		123	data.pfn = fr.pfn;
-		124	data.l = true;
-		125	data.cp = 0;
-		126	data.cv = 0;
-		127	data.p = true;
-		128	data.w = true;
-		129	data.g = true;
-		130
-		131	dtlb_data_in_write(data.value);
-		132
99	}	133	}
100		134
101	/** ITLB miss handler. */	135	/** ITLB miss handler. */
102	void fast_instruction_access_mmu_miss(void)	136	void fast_instruction_access_mmu_miss(void)
103	{	137	{
104	panic("%s\n", __FUNCTION__);	138	panic("%s\n", __FUNCTION__);
105	}	139	}
106		140
107	/** DTLB miss handler. */	141	/** DTLB miss handler. */
108	void fast_data_access_mmu_miss(void)	142	void fast_data_access_mmu_miss(void)
109	{	143	{
-		144	tlb_sfsr_reg_t status;
-		145	__address address, tpc;
-		146	char *tpc_str;
-		147
-		148	status.value = dtlb_sfsr_read();
-		149	address = dtlb_sfar_read();
-		150	tpc = tpc_read();
-		151	tpc_str = get_symtab_entry(tpc);
-		152
-		153	printf("ASI=%B, Context=%s\n", status.asi, context_encoding[status.ct]);
-		154	printf("Faulting address: %P\n", dtlb_sfar_read());
-		155	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
110	panic("%s\n", __FUNCTION__);	156	panic("%s\n", __FUNCTION__);
111	}	157	}
112		158
113	/** DTLB protection fault handler. */	159	/** DTLB protection fault handler. */
114	void fast_data_access_protection(void)	160	void fast_data_access_protection(void)
115	{	161	{
116	panic("%s\n", __FUNCTION__);	162	panic("%s\n", __FUNCTION__);
117	}	163	}
118		164
119	/** Print contents of both TLBs. */	165	/** Print contents of both TLBs. */
120	void tlb_print(void)	166	void tlb_print(void)
121	{	167	{
122	int i;	168	int i;
123	tlb_data_t d;	169	tlb_data_t d;
124	tlb_tag_read_reg_t t;	170	tlb_tag_read_reg_t t;
125		171
126	printf("I-TLB contents:\n");	172	printf("I-TLB contents:\n");
127	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	173	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
128	d.value = itlb_data_access_read(i);	174	d.value = itlb_data_access_read(i);
129	t.value = itlb_tag_read_read(i);	175	t.value = itlb_tag_read_read(i);
130		176
131	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	177	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
132	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	178	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
133	}	179	}
134		180
135	printf("D-TLB contents:\n");	181	printf("D-TLB contents:\n");
136	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	182	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
137	d.value = dtlb_data_access_read(i);	183	d.value = dtlb_data_access_read(i);
138	t.value = dtlb_tag_read_read(i);	184	t.value = dtlb_tag_read_read(i);
139		185
140	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	186	printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
141	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	187	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
142	}	188	}
143		189
144	}	190	}
145		191
146	/** Invalidate all unlocked ITLB and DTLB entries. */	192	/** Invalidate all unlocked ITLB and DTLB entries. */
147	void tlb_invalidate_all(void)	193	void tlb_invalidate_all(void)
148	{	194	{
149	int i;	195	int i;
150	tlb_data_t d;	196	tlb_data_t d;
151	tlb_tag_read_reg_t t;	197	tlb_tag_read_reg_t t;
152		198
153	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	199	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
154	d.value = itlb_data_access_read(i);	200	d.value = itlb_data_access_read(i);
155	if (!d.l) {	201	if (!d.l) {
156	t.value = itlb_tag_read_read(i);	202	t.value = itlb_tag_read_read(i);
157	d.v = false;	203	d.v = false;
158	itlb_tag_access_write(t.value);	204	itlb_tag_access_write(t.value);
159	itlb_data_access_write(i, d.value);	205	itlb_data_access_write(i, d.value);
160	}	206	}
161	}	207	}
162		208
163	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	209	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
164	d.value = dtlb_data_access_read(i);	210	d.value = dtlb_data_access_read(i);
165	if (!d.l) {	211	if (!d.l) {
166	t.value = dtlb_tag_read_read(i);	212	t.value = dtlb_tag_read_read(i);
167	d.v = false;	213	d.v = false;
168	dtlb_tag_access_write(t.value);	214	dtlb_tag_access_write(t.value);
169	dtlb_data_access_write(i, d.value);	215	dtlb_data_access_write(i, d.value);
170	}	216	}
171	}	217	}
172		218
173	}	219	}
174		220
175	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	221	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
176	*	222	*
177	* @param asid Address Space ID.	223	* @param asid Address Space ID.
178	*/	224	*/
179	void tlb_invalidate_asid(asid_t asid)	225	void tlb_invalidate_asid(asid_t asid)
180	{	226	{
181	/* TODO: write asid to some Context register and encode the register in second parameter below. */	227	/* TODO: write asid to some Context register and encode the register in second parameter below. */
182	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	228	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
183	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	229	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
184	}	230	}
185		231
186	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	232	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
187	*	233	*
188	* @param asid Address Space ID.	234	* @param asid Address Space ID.
189	* @param page First page which to sweep out from ITLB and DTLB.	235	* @param page First page which to sweep out from ITLB and DTLB.
190	* @param cnt Number of ITLB and DTLB entries to invalidate.	236	* @param cnt Number of ITLB and DTLB entries to invalidate.
191	*/	237	*/
192	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	238	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
193	{	239	{
194	int i;	240	int i;
195		241
196	for (i = 0; i < cnt; i++) {	242	for (i = 0; i < cnt; i++) {
197	/* TODO: write asid to some Context register and encode the register in second parameter below. */	243	/* TODO: write asid to some Context register and encode the register in second parameter below. */
198	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	244	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
199	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	245	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
200	}	246	}
201	}	247	}
202		248

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(root)/kernel/trunk/arch/sparc64/src/mm/tlb.c – Rev 863 → 873