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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
30 | #include <mm/tlb.h> |
30 | #include <mm/tlb.h> |
- | 31 | #include <arch/mm/frame.h> |
|
- | 32 | #include <arch/mm/page.h> |
|
- | 33 | #include <arch/mm/mmu.h> |
|
31 | #include <print.h> |
34 | #include <print.h> |
32 | #include <arch/types.h> |
35 | #include <arch/types.h> |
33 | #include <typedefs.h> |
36 | #include <typedefs.h> |
- | 37 | #include <config.h> |
|
34 | 38 | ||
- | 39 | /** Initialize ITLB and DTLB. |
|
- | 40 | * |
|
- | 41 | * The goal of this function is to disable MMU |
|
- | 42 | * so that both TLBs can be purged and new |
|
- | 43 | * kernel 4M locked entry can be installed. |
|
- | 44 | * After TLB is initialized, MMU is enabled |
|
- | 45 | * again. |
|
- | 46 | */ |
|
35 | void tlb_arch_init(void) |
47 | void tlb_arch_init(void) |
36 | { |
48 | { |
- | 49 | tlb_tag_access_reg_t tag; |
|
- | 50 | tlb_data_t data; |
|
- | 51 | frame_address_t fr; |
|
- | 52 | page_address_t pg; |
|
- | 53 | ||
- | 54 | fr.address = config.base; |
|
- | 55 | pg.address = config.base; |
|
- | 56 | ||
- | 57 | immu_disable(); |
|
- | 58 | dmmu_disable(); |
|
- | 59 | ||
- | 60 | /* |
|
- | 61 | * For simplicity, we do identity mapping of first 4M of memory. |
|
- | 62 | * The very next change should be leaving the first 4M unmapped. |
|
- | 63 | */ |
|
- | 64 | tag.value = 0; |
|
- | 65 | tag.vpn = pg.vpn; |
|
- | 66 | ||
- | 67 | itlb_tag_access_write(tag.value); |
|
- | 68 | dtlb_tag_access_write(tag.value); |
|
- | 69 | ||
- | 70 | data.value = 0; |
|
- | 71 | data.v = true; |
|
- | 72 | data.size = PAGESIZE_4M; |
|
- | 73 | data.pfn = fr.pfn; |
|
- | 74 | data.l = true; |
|
- | 75 | data.cp = 1; |
|
- | 76 | data.cv = 1; |
|
- | 77 | data.p = true; |
|
- | 78 | data.w = true; |
|
- | 79 | data.g = true; |
|
- | 80 | ||
- | 81 | itlb_data_in_write(data.value); |
|
- | 82 | dtlb_data_in_write(data.value); |
|
- | 83 | ||
- | 84 | tlb_invalidate_all(); |
|
- | 85 | ||
- | 86 | dmmu_enable(); |
|
- | 87 | immu_enable(); |
|
37 | } |
88 | } |
38 | 89 | ||
39 | /** Print contents of both TLBs. */ |
90 | /** Print contents of both TLBs. */ |
40 | void tlb_print(void) |
91 | void tlb_print(void) |
41 | { |
92 | { |
42 | int i; |
93 | int i; |
43 | tlb_data_t d; |
94 | tlb_data_t d; |
44 | tlb_tag_read_reg_t t; |
95 | tlb_tag_read_reg_t t; |
45 | 96 | ||
46 | printf("I-TLB contents:\n"); |
97 | printf("I-TLB contents:\n"); |
47 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
98 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
48 | d.value = itlb_data_access_read(i); |
99 | d.value = itlb_data_access_read(i); |
49 | t.value = itlb_tag_read_read(i); |
100 | t.value = itlb_tag_read_read(i); |
50 | 101 | ||
51 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
102 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
52 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
103 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
53 | } |
104 | } |
54 | 105 | ||
55 | printf("D-TLB contents:\n"); |
106 | printf("D-TLB contents:\n"); |
56 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
107 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
57 | d.value = dtlb_data_access_read(i); |
108 | d.value = dtlb_data_access_read(i); |
58 | t.value = dtlb_tag_read_read(i); |
109 | t.value = dtlb_tag_read_read(i); |
59 | 110 | ||
60 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
111 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
61 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
112 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
62 | } |
113 | } |
63 | 114 | ||
64 | } |
115 | } |
65 | 116 | ||
66 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
117 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
67 | void tlb_invalidate_all(void) |
118 | void tlb_invalidate_all(void) |
68 | { |
119 | { |
69 | int i; |
120 | int i; |
70 | tlb_data_t d; |
121 | tlb_data_t d; |
71 | tlb_tag_read_reg_t t; |
122 | tlb_tag_read_reg_t t; |
72 | 123 | ||
73 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
124 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
74 | d.value = itlb_data_access_read(i); |
125 | d.value = itlb_data_access_read(i); |
75 | if (!d.l) { |
126 | if (!d.l) { |
76 | printf("invalidating "); |
- | |
77 | t.value = itlb_tag_read_read(i); |
127 | t.value = itlb_tag_read_read(i); |
78 | d.v = false; |
128 | d.v = false; |
79 | itlb_tag_access_write(t.value); |
129 | itlb_tag_access_write(t.value); |
80 | itlb_data_access_write(i, d.value); |
130 | itlb_data_access_write(i, d.value); |
81 | } |
131 | } |
82 | } |
132 | } |
83 | 133 | ||
84 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
134 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
85 | d.value = dtlb_data_access_read(i); |
135 | d.value = dtlb_data_access_read(i); |
86 | if (!d.l) { |
136 | if (!d.l) { |
87 | t.value = dtlb_tag_read_read(i); |
137 | t.value = dtlb_tag_read_read(i); |
88 | d.v = false; |
138 | d.v = false; |
89 | dtlb_tag_access_write(t.value); |
139 | dtlb_tag_access_write(t.value); |
90 | dtlb_data_access_write(i, d.value); |
140 | dtlb_data_access_write(i, d.value); |
91 | } |
141 | } |
92 | } |
142 | } |
93 | 143 | ||
94 | } |
144 | } |
95 | 145 | ||
96 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
146 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
97 | * |
147 | * |
98 | * @param asid Address Space ID. |
148 | * @param asid Address Space ID. |
99 | */ |
149 | */ |
100 | void tlb_invalidate_asid(asid_t asid) |
150 | void tlb_invalidate_asid(asid_t asid) |
101 | { |
151 | { |
102 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
152 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
103 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
153 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
104 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
154 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
105 | } |
155 | } |
106 | 156 | ||
107 | /** Invalidate all ITLB and DLTB entries for specified page in specified address space. |
157 | /** Invalidate all ITLB and DLTB entries for specified page in specified address space. |
108 | * |
158 | * |
109 | * @param asid Address Space ID. |
159 | * @param asid Address Space ID. |
110 | * @param page Page which to sweep out from ITLB and DTLB. |
160 | * @param page Page which to sweep out from ITLB and DTLB. |
111 | */ |
161 | */ |
112 | void tlb_invalidate_page(asid_t asid, __address page) |
162 | void tlb_invalidate_page(asid_t asid, __address page) |
113 | { |
163 | { |
114 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
164 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
115 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page); |
165 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page); |
116 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page); |
166 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page); |
117 | } |
167 | } |
118 | 168 |