WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <mm/asid.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
 
#include <arch/drivers/fb.h>
#include <arch/drivers/i8042.h>
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
/** Initialize ITLB and DTLB.
 *
 * The goal of this function is to disable MMU
 * so that both TLBs can be purged and new
 * kernel 4M locked entry can be installed.
 * After TLB is initialized, MMU is enabled
 * again.
 *
 * Switching MMU off imposes the requirement for
 * the kernel to run in identity mapped environment.
 */
void tlb_arch_init(void)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    frame_address_t fr;
    page_address_t pg;
 
    fr.address = config.base;
    pg.address = config.base;
 
    immu_disable();
    dmmu_disable();
 
    /*
     * Demap everything, especially OpenFirmware.
     */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
   
    /*
     * We do identity mapping of 4M-page at 4M.
     */
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    itlb_tag_access_write(tag.value);
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_4M;
    data.pfn = fr.pfn;
    data.l = true;
    data.cp = 1;
    data.cv = 1;
    data.p = true;
    data.w = true;
    data.g = true;
 
    itlb_data_in_write(data.value);
    dtlb_data_in_write(data.value);
 
    /*
     * Register window traps can occur before MMU is enabled again.
     * This ensures that any such traps will be handled from
     * kernel identity mapped trap handler.
     */
    trap_switch_trap_table();
   
    tlb_invalidate_all();
 
    dmmu_enable();
    immu_enable();
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
    data.cv = cacheable;
    data.p = true;
    data.w = true;
    data.g = true;
 
    dtlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
    tlb_tag_access_reg_t tag;
    __address tpc;
    char *tpc_str;
 
    tag.value = dtlb_tag_access_read();
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
        tpc = tpc_read();
        tpc_str = get_symtab_entry(tpc);
 
        printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
        printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
        panic("%s\n", __FUNCTION__);
    }
 
    /*
     * Identity map piece of faulting kernel address space.
     */
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
    panic("%s\n", __FUNCTION__);
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
   
    for (i = 0; i < cnt; i++) {
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    }
}
 

Rev 1196	Rev 1221
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <mm/tlb.h>	30	#include <mm/tlb.h>
31	#include <arch/mm/frame.h>	31	#include <arch/mm/frame.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <arch/mm/mmu.h>	33	#include <arch/mm/mmu.h>
34	#include <mm/asid.h>	34	#include <mm/asid.h>
35	#include <print.h>	35	#include <print.h>
36	#include <arch/types.h>	36	#include <arch/types.h>
37	#include <typedefs.h>	37	#include <typedefs.h>
38	#include <config.h>	38	#include <config.h>
39	#include <arch/trap/trap.h>	39	#include <arch/trap/trap.h>
40	#include <panic.h>	40	#include <panic.h>
41	#include <arch/asm.h>	41	#include <arch/asm.h>
42	#include <symtab.h>	42	#include <symtab.h>
43		43
44	#include <arch/drivers/fb.h>	44	#include <arch/drivers/fb.h>
45	#include <arch/drivers/i8042.h>	45	#include <arch/drivers/i8042.h>
46		46
47	char *context_encoding[] = {	47	char *context_encoding[] = {
48	"Primary",	48	"Primary",
49	"Secondary",	49	"Secondary",
50	"Nucleus",	50	"Nucleus",
51	"Reserved"	51	"Reserved"
52	};	52	};
53		53
54	/** Initialize ITLB and DTLB.	54	/** Initialize ITLB and DTLB.
55	*	55	*
56	* The goal of this function is to disable MMU	56	* The goal of this function is to disable MMU
57	* so that both TLBs can be purged and new	57	* so that both TLBs can be purged and new
58	* kernel 4M locked entry can be installed.	58	* kernel 4M locked entry can be installed.
59	* After TLB is initialized, MMU is enabled	59	* After TLB is initialized, MMU is enabled
60	* again.	60	* again.
61	*	61	*
62	* Switching MMU off imposes the requirement for	62	* Switching MMU off imposes the requirement for
63	* the kernel to run in identity mapped environment.	63	* the kernel to run in identity mapped environment.
64	*/	64	*/
65	void tlb_arch_init(void)	65	void tlb_arch_init(void)
66	{	66	{
67	tlb_tag_access_reg_t tag;	67	tlb_tag_access_reg_t tag;
68	tlb_data_t data;	68	tlb_data_t data;
69	frame_address_t fr;	69	frame_address_t fr;
70	page_address_t pg;	70	page_address_t pg;
71		71
72	fr.address = config.base;	72	fr.address = config.base;
73	pg.address = config.base;	73	pg.address = config.base;
74		74
75	immu_disable();	75	immu_disable();
76	dmmu_disable();	76	dmmu_disable();
77		77
78	/*	78	/*
79	* Demap everything, especially OpenFirmware.	79	* Demap everything, especially OpenFirmware.
80	*/	80	*/
81	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	81	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
82	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	82	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
83		83
84	/*	84	/*
85	* We do identity mapping of 4M-page at 4M.	85	* We do identity mapping of 4M-page at 4M.
86	*/	86	*/
87	tag.value = ASID_KERNEL;	87	tag.value = ASID_KERNEL;
88	tag.vpn = pg.vpn;	88	tag.vpn = pg.vpn;
89		89
90	itlb_tag_access_write(tag.value);	90	itlb_tag_access_write(tag.value);
91	dtlb_tag_access_write(tag.value);	91	dtlb_tag_access_write(tag.value);
92		92
93	data.value = 0;	93	data.value = 0;
94	data.v = true;	94	data.v = true;
95	data.size = PAGESIZE_4M;	95	data.size = PAGESIZE_4M;
96	data.pfn = fr.pfn;	96	data.pfn = fr.pfn;
97	data.l = true;	97	data.l = true;
98	data.cp = 1;	98	data.cp = 1;
99	data.cv = 1;	99	data.cv = 1;
100	data.p = true;	100	data.p = true;
101	data.w = true;	101	data.w = true;
102	data.g = true;	102	data.g = true;
103		103
104	itlb_data_in_write(data.value);	104	itlb_data_in_write(data.value);
105	dtlb_data_in_write(data.value);	105	dtlb_data_in_write(data.value);
106		106
107	/*	107	/*
108	* Register window traps can occur before MMU is enabled again.	108	* Register window traps can occur before MMU is enabled again.
109	* This ensures that any such traps will be handled from	109	* This ensures that any such traps will be handled from
110	* kernel identity mapped trap handler.	110	* kernel identity mapped trap handler.
111	*/	111	*/
112	trap_switch_trap_table();	112	trap_switch_trap_table();
113		113
114	tlb_invalidate_all();	114	tlb_invalidate_all();
115		115
116	dmmu_enable();	116	dmmu_enable();
117	immu_enable();	117	immu_enable();
118	}	118	}
119		119
120	/** Insert privileged mapping into DMMU TLB.	120	/** Insert privileged mapping into DMMU TLB.
121	*	121	*
122	* @param page Virtual page address.	122	* @param page Virtual page address.
123	* @param frame Physical frame address.	123	* @param frame Physical frame address.
124	* @param pagesize Page size.	124	* @param pagesize Page size.
125	* @param locked True for permanent mappings, false otherwise.	125	* @param locked True for permanent mappings, false otherwise.
126	* @param cacheable True if the mapping is cacheable, false otherwise.	126	* @param cacheable True if the mapping is cacheable, false otherwise.
127	*/	127	*/
128	void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)	128	void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
129	{	129	{
130	tlb_tag_access_reg_t tag;	130	tlb_tag_access_reg_t tag;
131	tlb_data_t data;	131	tlb_data_t data;
132	page_address_t pg;	132	page_address_t pg;
133	frame_address_t fr;	133	frame_address_t fr;
134		134
135	pg.address = page;	135	pg.address = page;
136	fr.address = frame;	136	fr.address = frame;
137		137
138	tag.value = ASID_KERNEL;	138	tag.value = ASID_KERNEL;
139	tag.vpn = pg.vpn;	139	tag.vpn = pg.vpn;
140		140
141	dtlb_tag_access_write(tag.value);	141	dtlb_tag_access_write(tag.value);
142		142
143	data.value = 0;	143	data.value = 0;
144	data.v = true;	144	data.v = true;
145	data.size = pagesize;	145	data.size = pagesize;
146	data.pfn = fr.pfn;	146	data.pfn = fr.pfn;
147	data.l = locked;	147	data.l = locked;
148	data.cp = cacheable;	148	data.cp = cacheable;
149	data.cv = cacheable;	149	data.cv = cacheable;
150	data.p = true;	150	data.p = true;
151	data.w = true;	151	data.w = true;
152	data.g = true;	152	data.g = true;
153		153
154	dtlb_data_in_write(data.value);	154	dtlb_data_in_write(data.value);
155	}	155	}
156		156
157	/** ITLB miss handler. */	157	/** ITLB miss handler. */
158	void fast_instruction_access_mmu_miss(void)	158	void fast_instruction_access_mmu_miss(void)
159	{	159	{
160	panic("%s\n", __FUNCTION__);	160	panic("%s\n", __FUNCTION__);
161	}	161	}
162		162
163	/** DTLB miss handler. */	163	/** DTLB miss handler. */
164	void fast_data_access_mmu_miss(void)	164	void fast_data_access_mmu_miss(void)
165	{	165	{
166	tlb_tag_access_reg_t tag;	166	tlb_tag_access_reg_t tag;
167	__address tpc;	167	__address tpc;
168	char *tpc_str;	168	char *tpc_str;
169		169
170	tag.value = dtlb_tag_access_read();	170	tag.value = dtlb_tag_access_read();
171	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {	171	if (tag.context != ASID_KERNEL \|\| tag.vpn == 0) {
172	tpc = tpc_read();	172	tpc = tpc_read();
173	tpc_str = get_symtab_entry(tpc);	173	tpc_str = get_symtab_entry(tpc);
174		174
175	printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);	175	printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
176	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");	176	printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
177	panic("%s\n", __FUNCTION__);	177	panic("%s\n", __FUNCTION__);
178	}	178	}
179		179
180	/*	180	/*
181	* Identity map piece of faulting kernel address space.	181	* Identity map piece of faulting kernel address space.
182	*/	182	*/
183	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);	183	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
184	}	184	}
185		185
186	/** DTLB protection fault handler. */	186	/** DTLB protection fault handler. */
187	void fast_data_access_protection(void)	187	void fast_data_access_protection(void)
188	{	188	{
189	panic("%s\n", __FUNCTION__);	189	panic("%s\n", __FUNCTION__);
190	}	190	}
191		191
192	/** Print contents of both TLBs. */	192	/** Print contents of both TLBs. */
193	void tlb_print(void)	193	void tlb_print(void)
194	{	194	{
195	int i;	195	int i;
196	tlb_data_t d;	196	tlb_data_t d;
197	tlb_tag_read_reg_t t;	197	tlb_tag_read_reg_t t;
198		198
199	printf("I-TLB contents:\n");	199	printf("I-TLB contents:\n");
200	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	200	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
201	d.value = itlb_data_access_read(i);	201	d.value = itlb_data_access_read(i);
202	t.value = itlb_tag_read_read(i);	202	t.value = itlb_tag_read_read(i);
203		203
204	printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	204	printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
205	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	205	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
206	}	206	}
207		207
208	printf("D-TLB contents:\n");	208	printf("D-TLB contents:\n");
209	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	209	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
210	d.value = dtlb_data_access_read(i);	210	d.value = dtlb_data_access_read(i);
211	t.value = dtlb_tag_read_read(i);	211	t.value = dtlb_tag_read_read(i);
212		212
213	printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	213	printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
214	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	214	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
215	}	215	}
216		216
217	}	217	}
218		218
219	/** Invalidate all unlocked ITLB and DTLB entries. */	219	/** Invalidate all unlocked ITLB and DTLB entries. */
220	void tlb_invalidate_all(void)	220	void tlb_invalidate_all(void)
221	{	221	{
222	int i;	222	int i;
223	tlb_data_t d;	223	tlb_data_t d;
224	tlb_tag_read_reg_t t;	224	tlb_tag_read_reg_t t;
225		225
226	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	226	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
227	d.value = itlb_data_access_read(i);	227	d.value = itlb_data_access_read(i);
228	if (!d.l) {	228	if (!d.l) {
229	t.value = itlb_tag_read_read(i);	229	t.value = itlb_tag_read_read(i);
230	d.v = false;	230	d.v = false;
231	itlb_tag_access_write(t.value);	231	itlb_tag_access_write(t.value);
232	itlb_data_access_write(i, d.value);	232	itlb_data_access_write(i, d.value);
233	}	233	}
234	}	234	}
235		235
236	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	236	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
237	d.value = dtlb_data_access_read(i);	237	d.value = dtlb_data_access_read(i);
238	if (!d.l) {	238	if (!d.l) {
239	t.value = dtlb_tag_read_read(i);	239	t.value = dtlb_tag_read_read(i);
240	d.v = false;	240	d.v = false;
241	dtlb_tag_access_write(t.value);	241	dtlb_tag_access_write(t.value);
242	dtlb_data_access_write(i, d.value);	242	dtlb_data_access_write(i, d.value);
243	}	243	}
244	}	244	}
245		245
246	}	246	}
247		247
248	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	248	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
249	*	249	*
250	* @param asid Address Space ID.	250	* @param asid Address Space ID.
251	*/	251	*/
252	void tlb_invalidate_asid(asid_t asid)	252	void tlb_invalidate_asid(asid_t asid)
253	{	253	{
254	/* TODO: write asid to some Context register and encode the register in second parameter below. */	254	/* TODO: write asid to some Context register and encode the register in second parameter below. */
255	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	255	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
256	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);	256	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
257	}	257	}
258		258
259	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	259	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
260	*	260	*
261	* @param asid Address Space ID.	261	* @param asid Address Space ID.
262	* @param page First page which to sweep out from ITLB and DTLB.	262	* @param page First page which to sweep out from ITLB and DTLB.
263	* @param cnt Number of ITLB and DTLB entries to invalidate.	263	* @param cnt Number of ITLB and DTLB entries to invalidate.
264	*/	264	*/
265	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	265	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
266	{	266	{
267	int i;	267	int i;
268		268
269	for (i = 0; i < cnt; i++) {	269	for (i = 0; i < cnt; i++) {
270	/* TODO: write asid to some Context register and encode the register in second parameter below. */	270	/* TODO: write asid to some Context register and encode the register in second parameter below. */
271	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	271	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
272	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);	272	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
273	}	273	}
274	}	274	}
275		275

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(root)/kernel/trunk/arch/sparc64/src/mm/tlb.c @ 1702 – Rev 1196 → 1221