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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __sparc64_TLB_H__ |
29 | #ifndef __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
31 | 31 | ||
32 | #include <arch/mm/tte.h> |
32 | #include <arch/mm/tte.h> |
- | 33 | #include <arch/mm/mmu.h> |
|
33 | #include <arch/mm/page.h> |
34 | #include <arch/mm/page.h> |
34 | #include <arch/asm.h> |
35 | #include <arch/asm.h> |
35 | #include <arch/barrier.h> |
36 | #include <arch/barrier.h> |
36 | #include <arch/types.h> |
37 | #include <arch/types.h> |
37 | #include <typedefs.h> |
38 | #include <typedefs.h> |
38 | 39 | ||
39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
41 | #define DTLB_ENTRY_COUNT 64 |
41 | 42 | ||
42 | /** I-MMU ASIs. */ |
43 | /** Page sizes. */ |
43 | #define ASI_IMMU 0x50 |
44 | #define PAGESIZE_8K 0 |
44 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
- | |
45 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
- | |
46 | #define ASI_ITLB_DATA_IN_REG 0x54 |
- | |
47 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
- | |
48 | #define ASI_ITLB_TAG_READ_REG 0x56 |
- | |
49 | #define ASI_IMMU_DEMAP 0x57 |
45 | #define PAGESIZE_64K 1 |
50 | - | ||
51 | /** Virtual Addresses within ASI_IMMU. */ |
- | |
52 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
- | |
53 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
- | |
54 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
- | |
55 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
- | |
56 | - | ||
57 | /** D-MMU ASIs. */ |
- | |
58 | #define ASI_DMMU 0x58 |
46 | #define PAGESIZE_512K 2 |
59 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
- | |
60 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
- | |
61 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
- | |
62 | #define ASI_DTLB_DATA_IN_REG 0x5c |
- | |
63 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
- | |
64 | #define ASI_DTLB_TAG_READ_REG 0x5e |
- | |
65 | #define ASI_DMMU_DEMAP 0x5f |
47 | #define PAGESIZE_4M 3 |
66 | - | ||
67 | /** Virtual Addresses within ASI_DMMU. */ |
- | |
68 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
- | |
69 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
- | |
70 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
- | |
71 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
- | |
72 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
- | |
73 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
- | |
74 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
- | |
75 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
- | |
76 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
- | |
77 | 48 | ||
78 | /** I-/D-TLB Data In/Access Register type. */ |
49 | /** I-/D-TLB Data In/Access Register type. */ |
79 | typedef tte_data_t tlb_data_t; |
50 | typedef tte_data_t tlb_data_t; |
80 | 51 | ||
81 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
52 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
82 | union tlb_data_access_addr { |
53 | union tlb_data_access_addr { |
83 | __u64 value; |
54 | __u64 value; |
84 | struct { |
55 | struct { |
85 | __u64 : 55; |
56 | __u64 : 55; |
86 | unsigned tlb_entry : 6; |
57 | unsigned tlb_entry : 6; |
87 | unsigned : 3; |
58 | unsigned : 3; |
88 | } __attribute__ ((packed)); |
59 | } __attribute__ ((packed)); |
89 | }; |
60 | }; |
90 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
61 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
91 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
62 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
92 | 63 | ||
93 | /** I-/D-TLB Tag Read Register. */ |
64 | /** I-/D-TLB Tag Read Register. */ |
94 | union tlb_tag_read_reg { |
65 | union tlb_tag_read_reg { |
95 | __u64 value; |
66 | __u64 value; |
96 | struct { |
67 | struct { |
97 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
68 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
98 | unsigned context : 13; /**< Context identifier. */ |
69 | unsigned context : 13; /**< Context identifier. */ |
99 | } __attribute__ ((packed)); |
70 | } __attribute__ ((packed)); |
100 | }; |
71 | }; |
101 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
72 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
102 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
73 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
103 | 74 | ||
104 | /** TLB Demap Operation types. */ |
75 | /** TLB Demap Operation types. */ |
105 | #define TLB_DEMAP_PAGE 0 |
76 | #define TLB_DEMAP_PAGE 0 |
106 | #define TLB_DEMAP_CONTEXT 1 |
77 | #define TLB_DEMAP_CONTEXT 1 |
107 | 78 | ||
108 | /** TLB Demap Operation Context register encodings. */ |
79 | /** TLB Demap Operation Context register encodings. */ |
109 | #define TLB_DEMAP_PRIMARY 0 |
80 | #define TLB_DEMAP_PRIMARY 0 |
110 | #define TLB_DEMAP_SECONDARY 1 |
81 | #define TLB_DEMAP_SECONDARY 1 |
111 | #define TLB_DEMAP_NUCLEUS 2 |
82 | #define TLB_DEMAP_NUCLEUS 2 |
112 | 83 | ||
113 | /** TLB Demap Operation Address. */ |
84 | /** TLB Demap Operation Address. */ |
114 | union tlb_demap_addr { |
85 | union tlb_demap_addr { |
115 | __u64 value; |
86 | __u64 value; |
116 | struct { |
87 | struct { |
117 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
88 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
118 | unsigned : 6; /**< Ignored. */ |
89 | unsigned : 6; /**< Ignored. */ |
119 | unsigned type : 1; /**< The type of demap operation. */ |
90 | unsigned type : 1; /**< The type of demap operation. */ |
120 | unsigned context : 2; /**< Context register selection. */ |
91 | unsigned context : 2; /**< Context register selection. */ |
121 | unsigned : 4; /**< Zero. */ |
92 | unsigned : 4; /**< Zero. */ |
122 | } __attribute__ ((packed)); |
93 | } __attribute__ ((packed)); |
123 | }; |
94 | }; |
124 | typedef union tlb_demap_addr tlb_demap_addr_t; |
95 | typedef union tlb_demap_addr tlb_demap_addr_t; |
125 | 96 | ||
126 | /** Read IMMU TLB Data Access Register. |
97 | /** Read IMMU TLB Data Access Register. |
127 | * |
98 | * |
128 | * @param entry TLB Entry index. |
99 | * @param entry TLB Entry index. |
129 | * |
100 | * |
130 | * @return Current value of specified IMMU TLB Data Access Register. |
101 | * @return Current value of specified IMMU TLB Data Access Register. |
131 | */ |
102 | */ |
132 | static inline __u64 itlb_data_access_read(index_t entry) |
103 | static inline __u64 itlb_data_access_read(index_t entry) |
133 | { |
104 | { |
134 | tlb_data_access_addr_t reg; |
105 | tlb_data_access_addr_t reg; |
135 | 106 | ||
136 | reg.value = 0; |
107 | reg.value = 0; |
137 | reg.tlb_entry = entry; |
108 | reg.tlb_entry = entry; |
138 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
109 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
139 | } |
110 | } |
140 | 111 | ||
141 | /** Write IMMU TLB Data Access Register. |
112 | /** Write IMMU TLB Data Access Register. |
142 | * |
113 | * |
143 | * @param entry TLB Entry index. |
114 | * @param entry TLB Entry index. |
144 | * @param value Value to be written. |
115 | * @param value Value to be written. |
145 | */ |
116 | */ |
146 | static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
117 | static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
147 | { |
118 | { |
148 | tlb_data_access_addr_t reg; |
119 | tlb_data_access_addr_t reg; |
149 | 120 | ||
150 | reg.value = 0; |
121 | reg.value = 0; |
151 | reg.tlb_entry = entry; |
122 | reg.tlb_entry = entry; |
152 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
123 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
153 | flush(); |
124 | flush(); |
154 | } |
125 | } |
155 | 126 | ||
156 | /** Read DMMU TLB Data Access Register. |
127 | /** Read DMMU TLB Data Access Register. |
157 | * |
128 | * |
158 | * @param entry TLB Entry index. |
129 | * @param entry TLB Entry index. |
159 | * |
130 | * |
160 | * @return Current value of specified DMMU TLB Data Access Register. |
131 | * @return Current value of specified DMMU TLB Data Access Register. |
161 | */ |
132 | */ |
162 | static inline __u64 dtlb_data_access_read(index_t entry) |
133 | static inline __u64 dtlb_data_access_read(index_t entry) |
163 | { |
134 | { |
164 | tlb_data_access_addr_t reg; |
135 | tlb_data_access_addr_t reg; |
165 | 136 | ||
166 | reg.value = 0; |
137 | reg.value = 0; |
167 | reg.tlb_entry = entry; |
138 | reg.tlb_entry = entry; |
168 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
139 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
169 | } |
140 | } |
170 | 141 | ||
171 | /** Write DMMU TLB Data Access Register. |
142 | /** Write DMMU TLB Data Access Register. |
172 | * |
143 | * |
173 | * @param entry TLB Entry index. |
144 | * @param entry TLB Entry index. |
174 | * @param value Value to be written. |
145 | * @param value Value to be written. |
175 | */ |
146 | */ |
176 | static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
147 | static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
177 | { |
148 | { |
178 | tlb_data_access_addr_t reg; |
149 | tlb_data_access_addr_t reg; |
179 | 150 | ||
180 | reg.value = 0; |
151 | reg.value = 0; |
181 | reg.tlb_entry = entry; |
152 | reg.tlb_entry = entry; |
182 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
153 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
183 | flush(); |
154 | flush(); |
184 | } |
155 | } |
185 | 156 | ||
186 | /** Read IMMU TLB Tag Read Register. |
157 | /** Read IMMU TLB Tag Read Register. |
187 | * |
158 | * |
188 | * @param entry TLB Entry index. |
159 | * @param entry TLB Entry index. |
189 | * |
160 | * |
190 | * @return Current value of specified IMMU TLB Tag Read Register. |
161 | * @return Current value of specified IMMU TLB Tag Read Register. |
191 | */ |
162 | */ |
192 | static inline __u64 itlb_tag_read_read(index_t entry) |
163 | static inline __u64 itlb_tag_read_read(index_t entry) |
193 | { |
164 | { |
194 | tlb_tag_read_addr_t tag; |
165 | tlb_tag_read_addr_t tag; |
195 | 166 | ||
196 | tag.value = 0; |
167 | tag.value = 0; |
197 | tag.tlb_entry = entry; |
168 | tag.tlb_entry = entry; |
198 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
169 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
199 | } |
170 | } |
200 | 171 | ||
201 | /** Read DMMU TLB Tag Read Register. |
172 | /** Read DMMU TLB Tag Read Register. |
202 | * |
173 | * |
203 | * @param entry TLB Entry index. |
174 | * @param entry TLB Entry index. |
204 | * |
175 | * |
205 | * @return Current value of specified DMMU TLB Tag Read Register. |
176 | * @return Current value of specified DMMU TLB Tag Read Register. |
206 | */ |
177 | */ |
207 | static inline __u64 dtlb_tag_read_read(index_t entry) |
178 | static inline __u64 dtlb_tag_read_read(index_t entry) |
208 | { |
179 | { |
209 | tlb_tag_read_addr_t tag; |
180 | tlb_tag_read_addr_t tag; |
210 | 181 | ||
211 | tag.value = 0; |
182 | tag.value = 0; |
212 | tag.tlb_entry = entry; |
183 | tag.tlb_entry = entry; |
213 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
184 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
214 | } |
185 | } |
215 | 186 | ||
216 | /** Write IMMU TLB Tag Access Register. |
187 | /** Write IMMU TLB Tag Access Register. |
217 | * |
188 | * |
218 | * @param v Value to be written. |
189 | * @param v Value to be written. |
219 | */ |
190 | */ |
220 | static inline void itlb_tag_access_write(__u64 v) |
191 | static inline void itlb_tag_access_write(__u64 v) |
221 | { |
192 | { |
222 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
193 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
223 | flush(); |
194 | flush(); |
224 | } |
195 | } |
225 | 196 | ||
226 | /** Write DMMU TLB Tag Access Register. |
197 | /** Write DMMU TLB Tag Access Register. |
227 | * |
198 | * |
228 | * @param v Value to be written. |
199 | * @param v Value to be written. |
229 | */ |
200 | */ |
230 | static inline void dtlb_tag_access_write(__u64 v) |
201 | static inline void dtlb_tag_access_write(__u64 v) |
231 | { |
202 | { |
232 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
203 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
233 | flush(); |
204 | flush(); |
234 | } |
205 | } |
235 | 206 | ||
236 | /** Write IMMU TLB Data in Register. |
207 | /** Write IMMU TLB Data in Register. |
237 | * |
208 | * |
238 | * @param v Value to be written. |
209 | * @param v Value to be written. |
239 | */ |
210 | */ |
240 | static inline void itlb_data_in_write(__u64 v) |
211 | static inline void itlb_data_in_write(__u64 v) |
241 | { |
212 | { |
242 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
213 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
243 | flush(); |
214 | flush(); |
244 | } |
215 | } |
245 | 216 | ||
246 | /** Write DMMU TLB Data in Register. |
217 | /** Write DMMU TLB Data in Register. |
247 | * |
218 | * |
248 | * @param v Value to be written. |
219 | * @param v Value to be written. |
249 | */ |
220 | */ |
250 | static inline void dtlb_data_in_write(__u64 v) |
221 | static inline void dtlb_data_in_write(__u64 v) |
251 | { |
222 | { |
252 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
223 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
253 | flush(); |
224 | flush(); |
254 | } |
225 | } |
255 | 226 | ||
256 | /** Perform IMMU TLB Demap Operation. |
227 | /** Perform IMMU TLB Demap Operation. |
257 | * |
228 | * |
258 | * @param type Selects between context and page demap. |
229 | * @param type Selects between context and page demap. |
259 | * @param context_encoding Specifies which Context register has Context ID for demap. |
230 | * @param context_encoding Specifies which Context register has Context ID for demap. |
260 | * @param page Address which is on the page to be demapped. |
231 | * @param page Address which is on the page to be demapped. |
261 | */ |
232 | */ |
262 | static inline void itlb_demap(int type, int context_encoding, __address page) |
233 | static inline void itlb_demap(int type, int context_encoding, __address page) |
263 | { |
234 | { |
264 | tlb_demap_addr_t da; |
235 | tlb_demap_addr_t da; |
265 | page_address_t pg; |
236 | page_address_t pg; |
266 | 237 | ||
267 | da.value = 0; |
238 | da.value = 0; |
268 | pg.address = page; |
239 | pg.address = page; |
269 | 240 | ||
270 | da.type = type; |
241 | da.type = type; |
271 | da.context = context_encoding; |
242 | da.context = context_encoding; |
272 | da.vpn = pg.vpn; |
243 | da.vpn = pg.vpn; |
273 | 244 | ||
274 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
245 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
275 | flush(); |
246 | flush(); |
276 | } |
247 | } |
277 | 248 | ||
278 | /** Perform DMMU TLB Demap Operation. |
249 | /** Perform DMMU TLB Demap Operation. |
279 | * |
250 | * |
280 | * @param type Selects between context and page demap. |
251 | * @param type Selects between context and page demap. |
281 | * @param context_encoding Specifies which Context register has Context ID for demap. |
252 | * @param context_encoding Specifies which Context register has Context ID for demap. |
282 | * @param page Address which is on the page to be demapped. |
253 | * @param page Address which is on the page to be demapped. |
283 | */ |
254 | */ |
284 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
255 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
285 | { |
256 | { |
286 | tlb_demap_addr_t da; |
257 | tlb_demap_addr_t da; |
287 | page_address_t pg; |
258 | page_address_t pg; |
288 | 259 | ||
289 | da.value = 0; |
260 | da.value = 0; |
290 | pg.address = page; |
261 | pg.address = page; |
291 | 262 | ||
292 | da.type = type; |
263 | da.type = type; |
293 | da.context = context_encoding; |
264 | da.context = context_encoding; |
294 | da.vpn = pg.vpn; |
265 | da.vpn = pg.vpn; |
295 | 266 | ||
296 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
267 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
297 | flush(); |
268 | flush(); |
298 | } |
269 | } |
299 | 270 | ||
300 | #endif |
271 | #endif |
301 | 272 |