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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __sparc64_TLB_H__ |
29 | #ifndef __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
31 | 31 | ||
32 | #include <arch/mm/tte.h> |
32 | #include <arch/mm/tte.h> |
- | 33 | #include <arch/mm/page.h> |
|
33 | #include <arch/asm.h> |
34 | #include <arch/asm.h> |
34 | #include <arch/barrier.h> |
35 | #include <arch/barrier.h> |
35 | #include <arch/types.h> |
36 | #include <arch/types.h> |
36 | #include <typedefs.h> |
37 | #include <typedefs.h> |
37 | 38 | ||
38 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
40 | 41 | ||
41 | /** I-MMU ASIs. */ |
42 | /** I-MMU ASIs. */ |
42 | #define ASI_IMMU 0x50 |
43 | #define ASI_IMMU 0x50 |
43 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
44 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
44 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
45 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
45 | #define ASI_ITLB_DATA_IN_REG 0x54 |
46 | #define ASI_ITLB_DATA_IN_REG 0x54 |
46 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
47 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
47 | #define ASI_ITLB_TAG_READ_REG 0x56 |
48 | #define ASI_ITLB_TAG_READ_REG 0x56 |
48 | #define ASI_IMMU_DEMAP 0x57 |
49 | #define ASI_IMMU_DEMAP 0x57 |
49 | 50 | ||
50 | /** Virtual Addresses within ASI_IMMU. */ |
51 | /** Virtual Addresses within ASI_IMMU. */ |
51 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
52 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
52 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
53 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
53 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
54 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
54 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
55 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
55 | 56 | ||
56 | /** D-MMU ASIs. */ |
57 | /** D-MMU ASIs. */ |
57 | #define ASI_DMMU 0x58 |
58 | #define ASI_DMMU 0x58 |
58 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
59 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
59 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
60 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
60 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
61 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
61 | #define ASI_DTLB_DATA_IN_REG 0x5c |
62 | #define ASI_DTLB_DATA_IN_REG 0x5c |
62 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
63 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
63 | #define ASI_DTLB_TAG_READ_REG 0x5e |
64 | #define ASI_DTLB_TAG_READ_REG 0x5e |
64 | #define ASI_DMMU_DEMAP 0x5f |
65 | #define ASI_DMMU_DEMAP 0x5f |
65 | 66 | ||
66 | /** Virtual Addresses within ASI_DMMU. */ |
67 | /** Virtual Addresses within ASI_DMMU. */ |
67 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
68 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
68 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
69 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
69 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
70 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
70 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
71 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
71 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
72 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
72 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
73 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
73 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
74 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
74 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
75 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
75 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
76 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
76 | 77 | ||
77 | /** I-/D-TLB Data In/Access Register type. */ |
78 | /** I-/D-TLB Data In/Access Register type. */ |
78 | typedef tte_data_t tlb_data_t; |
79 | typedef tte_data_t tlb_data_t; |
79 | 80 | ||
80 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
81 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
81 | union tlb_data_access_addr { |
82 | union tlb_data_access_addr { |
82 | __u64 value; |
83 | __u64 value; |
83 | struct { |
84 | struct { |
84 | __u64 : 55; |
85 | __u64 : 55; |
85 | unsigned tlb_entry : 6; |
86 | unsigned tlb_entry : 6; |
86 | unsigned : 3; |
87 | unsigned : 3; |
87 | } __attribute__ ((packed)); |
88 | } __attribute__ ((packed)); |
88 | }; |
89 | }; |
89 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
90 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
90 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
91 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
91 | 92 | ||
92 | /** I-/D-TLB Tag Read Register. */ |
93 | /** I-/D-TLB Tag Read Register. */ |
93 | union tlb_tag_read_reg { |
94 | union tlb_tag_read_reg { |
94 | __u64 value; |
95 | __u64 value; |
95 | struct { |
96 | struct { |
96 | __u64 va : 51; /**< Virtual Address. */ |
97 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
97 | unsigned context : 13; /**< Context identifier. */ |
98 | unsigned context : 13; /**< Context identifier. */ |
98 | } __attribute__ ((packed)); |
99 | } __attribute__ ((packed)); |
99 | }; |
100 | }; |
100 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
101 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
101 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
102 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
102 | 103 | ||
- | 104 | /** TLB Demap Operation types. */ |
|
- | 105 | #define TLB_DEMAP_PAGE 0 |
|
- | 106 | #define TLB_DEMAP_CONTEXT 1 |
|
- | 107 | ||
- | 108 | /** TLB Demap Operation Context register encodings. */ |
|
- | 109 | #define TLB_DEMAP_PRIMARY 0 |
|
- | 110 | #define TLB_DEMAP_SECONDARY 1 |
|
- | 111 | #define TLB_DEMAP_NUCLEUS 2 |
|
- | 112 | ||
- | 113 | /** TLB Demap Operation Address. */ |
|
- | 114 | union tlb_demap_addr { |
|
- | 115 | __u64 value; |
|
- | 116 | struct { |
|
- | 117 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
|
- | 118 | unsigned : 6; /**< Ignored. */ |
|
- | 119 | unsigned type : 1; /**< The type of demap operation. */ |
|
- | 120 | unsigned context : 2; /**< Context register selection. */ |
|
- | 121 | unsigned : 4; /**< Zero. */ |
|
- | 122 | } __attribute__ ((packed)); |
|
- | 123 | }; |
|
- | 124 | typedef union tlb_demap_addr tlb_demap_addr_t; |
|
- | 125 | ||
103 | /** Read IMMU TLB Data Access Register. |
126 | /** Read IMMU TLB Data Access Register. |
104 | * |
127 | * |
105 | * @param entry TLB Entry index. |
128 | * @param entry TLB Entry index. |
106 | * |
129 | * |
107 | * @return Current value of specified IMMU TLB Data Access Register. |
130 | * @return Current value of specified IMMU TLB Data Access Register. |
108 | */ |
131 | */ |
109 | static inline __u64 itlb_data_access_read(index_t entry) |
132 | static inline __u64 itlb_data_access_read(index_t entry) |
110 | { |
133 | { |
111 | tlb_data_access_addr_t reg; |
134 | tlb_data_access_addr_t reg; |
112 | 135 | ||
113 | reg.value = 0; |
136 | reg.value = 0; |
114 | reg.tlb_entry = entry; |
137 | reg.tlb_entry = entry; |
115 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
138 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
116 | } |
139 | } |
117 | 140 | ||
- | 141 | /** Write IMMU TLB Data Access Register. |
|
- | 142 | * |
|
- | 143 | * @param entry TLB Entry index. |
|
- | 144 | * @param value Value to be written. |
|
- | 145 | */ |
|
- | 146 | static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
|
- | 147 | { |
|
- | 148 | tlb_data_access_addr_t reg; |
|
- | 149 | ||
- | 150 | reg.value = 0; |
|
- | 151 | reg.tlb_entry = entry; |
|
- | 152 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
|
- | 153 | flush(); |
|
- | 154 | } |
|
- | 155 | ||
118 | /** Read DMMU TLB Data Access Register. |
156 | /** Read DMMU TLB Data Access Register. |
119 | * |
157 | * |
120 | * @param entry TLB Entry index. |
158 | * @param entry TLB Entry index. |
121 | * |
159 | * |
122 | * @return Current value of specified DMMU TLB Data Access Register. |
160 | * @return Current value of specified DMMU TLB Data Access Register. |
123 | */ |
161 | */ |
124 | static inline __u64 dtlb_data_access_read(index_t entry) |
162 | static inline __u64 dtlb_data_access_read(index_t entry) |
125 | { |
163 | { |
126 | tlb_data_access_addr_t reg; |
164 | tlb_data_access_addr_t reg; |
127 | 165 | ||
128 | reg.value = 0; |
166 | reg.value = 0; |
129 | reg.tlb_entry = entry; |
167 | reg.tlb_entry = entry; |
130 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
168 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
131 | } |
169 | } |
132 | 170 | ||
- | 171 | /** Write DMMU TLB Data Access Register. |
|
- | 172 | * |
|
- | 173 | * @param entry TLB Entry index. |
|
- | 174 | * @param value Value to be written. |
|
- | 175 | */ |
|
- | 176 | static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
|
- | 177 | { |
|
- | 178 | tlb_data_access_addr_t reg; |
|
- | 179 | ||
- | 180 | reg.value = 0; |
|
- | 181 | reg.tlb_entry = entry; |
|
- | 182 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
|
- | 183 | flush(); |
|
- | 184 | } |
|
- | 185 | ||
133 | /** Read IMMU TLB Tag Read Register. |
186 | /** Read IMMU TLB Tag Read Register. |
134 | * |
187 | * |
135 | * @param entry TLB Entry index. |
188 | * @param entry TLB Entry index. |
136 | * |
189 | * |
137 | * @return Current value of specified IMMU TLB Tag Read Register. |
190 | * @return Current value of specified IMMU TLB Tag Read Register. |
138 | */ |
191 | */ |
139 | static inline __u64 itlb_tag_read_read(index_t entry) |
192 | static inline __u64 itlb_tag_read_read(index_t entry) |
140 | { |
193 | { |
141 | tlb_tag_read_addr_t tag; |
194 | tlb_tag_read_addr_t tag; |
142 | 195 | ||
143 | tag.value = 0; |
196 | tag.value = 0; |
144 | tag.tlb_entry = entry; |
197 | tag.tlb_entry = entry; |
145 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
198 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
146 | } |
199 | } |
147 | 200 | ||
148 | /** Read DMMU TLB Tag Read Register. |
201 | /** Read DMMU TLB Tag Read Register. |
149 | * |
202 | * |
150 | * @param entry TLB Entry index. |
203 | * @param entry TLB Entry index. |
151 | * |
204 | * |
152 | * @return Current value of specified DMMU TLB Tag Read Register. |
205 | * @return Current value of specified DMMU TLB Tag Read Register. |
153 | */ |
206 | */ |
154 | static inline __u64 dtlb_tag_read_read(index_t entry) |
207 | static inline __u64 dtlb_tag_read_read(index_t entry) |
155 | { |
208 | { |
156 | tlb_tag_read_addr_t tag; |
209 | tlb_tag_read_addr_t tag; |
157 | 210 | ||
158 | tag.value = 0; |
211 | tag.value = 0; |
159 | tag.tlb_entry = entry; |
212 | tag.tlb_entry = entry; |
160 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
213 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
161 | } |
214 | } |
162 | 215 | ||
163 | /** Write IMMU TLB Tag Access Register. |
216 | /** Write IMMU TLB Tag Access Register. |
164 | * |
217 | * |
165 | * @param v Value to be written. |
218 | * @param v Value to be written. |
166 | */ |
219 | */ |
167 | static inline void itlb_tag_access_write(__u64 v) |
220 | static inline void itlb_tag_access_write(__u64 v) |
168 | { |
221 | { |
169 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
222 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
170 | flush(); |
223 | flush(); |
171 | } |
224 | } |
172 | 225 | ||
173 | /** Write DMMU TLB Tag Access Register. |
226 | /** Write DMMU TLB Tag Access Register. |
174 | * |
227 | * |
175 | * @param v Value to be written. |
228 | * @param v Value to be written. |
176 | */ |
229 | */ |
177 | static inline void dtlb_tag_access_write(__u64 v) |
230 | static inline void dtlb_tag_access_write(__u64 v) |
178 | { |
231 | { |
179 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
232 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
180 | flush(); |
233 | flush(); |
181 | } |
234 | } |
182 | 235 | ||
183 | /** Write IMMU TLB Data in Register. |
236 | /** Write IMMU TLB Data in Register. |
184 | * |
237 | * |
185 | * @param v Value to be written. |
238 | * @param v Value to be written. |
186 | */ |
239 | */ |
187 | static inline void itlb_data_in_write(__u64 v) |
240 | static inline void itlb_data_in_write(__u64 v) |
188 | { |
241 | { |
189 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
242 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
190 | flush(); |
243 | flush(); |
191 | } |
244 | } |
192 | 245 | ||
193 | /** Write DMMU TLB Data in Register. |
246 | /** Write DMMU TLB Data in Register. |
194 | * |
247 | * |
195 | * @param v Value to be written. |
248 | * @param v Value to be written. |
196 | */ |
249 | */ |
197 | static inline void dtlb_data_in_write(__u64 v) |
250 | static inline void dtlb_data_in_write(__u64 v) |
198 | { |
251 | { |
199 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
252 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
200 | flush(); |
253 | flush(); |
- | 254 | } |
|
- | 255 | ||
- | 256 | /** Perform IMMU TLB Demap Operation. |
|
- | 257 | * |
|
- | 258 | * @param type Selects between context and page demap. |
|
- | 259 | * @param context_encoding Specifies which Context register has Context ID for demap. |
|
- | 260 | * @param page Address which is on the page to be demapped. |
|
- | 261 | */ |
|
- | 262 | static inline void itlb_demap(int type, int context_encoding, __address page) |
|
- | 263 | { |
|
- | 264 | tlb_demap_addr_t da; |
|
- | 265 | page_address_t pg; |
|
- | 266 | ||
- | 267 | da.value = 0; |
|
- | 268 | pg.address = page; |
|
- | 269 | ||
- | 270 | da.type = type; |
|
- | 271 | da.context = context_encoding; |
|
- | 272 | da.vpn = pg.vpn; |
|
- | 273 | ||
- | 274 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
|
- | 275 | flush(); |
|
- | 276 | } |
|
- | 277 | ||
- | 278 | /** Perform DMMU TLB Demap Operation. |
|
- | 279 | * |
|
- | 280 | * @param type Selects between context and page demap. |
|
- | 281 | * @param context_encoding Specifies which Context register has Context ID for demap. |
|
- | 282 | * @param page Address which is on the page to be demapped. |
|
- | 283 | */ |
|
- | 284 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
|
- | 285 | { |
|
- | 286 | tlb_demap_addr_t da; |
|
- | 287 | page_address_t pg; |
|
- | 288 | ||
- | 289 | da.value = 0; |
|
- | 290 | pg.address = page; |
|
- | 291 | ||
- | 292 | da.type = type; |
|
- | 293 | da.context = context_encoding; |
|
- | 294 | da.vpn = pg.vpn; |
|
- | 295 | ||
- | 296 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
|
- | 297 | flush(); |
|
201 | } |
298 | } |
202 | 299 | ||
203 | #endif |
300 | #endif |
204 | 301 |