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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __sparc64_TLB_H__ |
29 | #ifndef __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
31 | 31 | ||
32 | #include <arch/mm/tte.h> |
32 | #include <arch/mm/tte.h> |
33 | #include <arch/asm.h> |
33 | #include <arch/asm.h> |
- | 34 | #include <arch/barrier.h> |
|
34 | #include <arch/types.h> |
35 | #include <arch/types.h> |
35 | #include <typedefs.h> |
36 | #include <typedefs.h> |
36 | 37 | ||
37 | #define ITLB_ENTRY_COUNT 64 |
38 | #define ITLB_ENTRY_COUNT 64 |
38 | #define DTLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
39 | 40 | ||
40 | /** I-MMU ASIs. */ |
41 | /** I-MMU ASIs. */ |
41 | #define ASI_IMMU 0x50 |
42 | #define ASI_IMMU 0x50 |
42 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
43 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
43 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
44 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
44 | #define ASI_ITLB_DATA_IN_REG 0x54 |
45 | #define ASI_ITLB_DATA_IN_REG 0x54 |
45 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
46 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
46 | #define ASI_ITLB_TAG_READ_REG 0x56 |
47 | #define ASI_ITLB_TAG_READ_REG 0x56 |
47 | #define ASI_IMMU_DEMAP 0x57 |
48 | #define ASI_IMMU_DEMAP 0x57 |
48 | 49 | ||
49 | /** Virtual Addresses within ASI_IMMU. */ |
50 | /** Virtual Addresses within ASI_IMMU. */ |
50 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
51 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
51 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
52 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
52 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
53 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
53 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
54 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
54 | 55 | ||
55 | /** D-MMU ASIs. */ |
56 | /** D-MMU ASIs. */ |
56 | #define ASI_DMMU 0x58 |
57 | #define ASI_DMMU 0x58 |
57 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
58 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
58 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
59 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
59 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
60 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
60 | #define ASI_DTLB_DATA_IN_REG 0x5c |
61 | #define ASI_DTLB_DATA_IN_REG 0x5c |
61 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
62 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
62 | #define ASI_DTLB_TAG_READ_REG 0x5e |
63 | #define ASI_DTLB_TAG_READ_REG 0x5e |
63 | #define ASI_DMMU_DEMAP 0x5f |
64 | #define ASI_DMMU_DEMAP 0x5f |
64 | 65 | ||
65 | /** Virtual Addresses within ASI_DMMU. */ |
66 | /** Virtual Addresses within ASI_DMMU. */ |
66 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
67 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
67 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
68 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
68 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
69 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
69 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
70 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
70 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
71 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
71 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
72 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
72 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
73 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
73 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
74 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
74 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
75 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
75 | 76 | ||
76 | /** I-/D-TLB Data In/Access Register type. */ |
77 | /** I-/D-TLB Data In/Access Register type. */ |
77 | typedef tte_data_t tlb_data_t; |
78 | typedef tte_data_t tlb_data_t; |
78 | 79 | ||
79 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
80 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
80 | union tlb_data_access_addr { |
81 | union tlb_data_access_addr { |
81 | __u64 value; |
82 | __u64 value; |
82 | struct { |
83 | struct { |
83 | __u64 : 55; |
84 | __u64 : 55; |
84 | unsigned tlb_entry : 6; |
85 | unsigned tlb_entry : 6; |
85 | unsigned : 3; |
86 | unsigned : 3; |
86 | } __attribute__ ((packed)); |
87 | } __attribute__ ((packed)); |
87 | }; |
88 | }; |
88 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
89 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
89 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
90 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
90 | 91 | ||
91 | /** I-/D-TLB Tag Read Register. */ |
92 | /** I-/D-TLB Tag Read Register. */ |
92 | union tlb_tag_read_reg { |
93 | union tlb_tag_read_reg { |
93 | __u64 value; |
94 | __u64 value; |
94 | struct { |
95 | struct { |
95 | __u64 va : 51; /**< Virtual Address. */ |
96 | __u64 va : 51; /**< Virtual Address. */ |
96 | unsigned context : 13; /**< Context identifier. */ |
97 | unsigned context : 13; /**< Context identifier. */ |
97 | } __attribute__ ((packed)); |
98 | } __attribute__ ((packed)); |
98 | }; |
99 | }; |
99 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
100 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
- | 101 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
|
100 | 102 | ||
101 | /** Read IMMU TLB Data Access Register. |
103 | /** Read IMMU TLB Data Access Register. |
102 | * |
104 | * |
103 | * @param entry TLB Entry index. |
105 | * @param entry TLB Entry index. |
104 | * |
106 | * |
105 | * @return Current value of specified IMMU TLB Data Access Register. |
107 | * @return Current value of specified IMMU TLB Data Access Register. |
106 | */ |
108 | */ |
107 | static inline __u64 itlb_data_access_read(index_t entry) |
109 | static inline __u64 itlb_data_access_read(index_t entry) |
108 | { |
110 | { |
109 | tlb_data_access_addr_t reg; |
111 | tlb_data_access_addr_t reg; |
110 | 112 | ||
111 | reg.value = 0; |
113 | reg.value = 0; |
112 | reg.tlb_entry = entry; |
114 | reg.tlb_entry = entry; |
113 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
115 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
114 | } |
116 | } |
115 | 117 | ||
116 | /** Read DMMU TLB Data Access Register. |
118 | /** Read DMMU TLB Data Access Register. |
117 | * |
119 | * |
118 | * @param entry TLB Entry index. |
120 | * @param entry TLB Entry index. |
119 | * |
121 | * |
120 | * @return Current value of specified DMMU TLB Data Access Register. |
122 | * @return Current value of specified DMMU TLB Data Access Register. |
121 | */ |
123 | */ |
122 | static inline __u64 dtlb_data_access_read(index_t entry) |
124 | static inline __u64 dtlb_data_access_read(index_t entry) |
123 | { |
125 | { |
124 | tlb_data_access_addr_t reg; |
126 | tlb_data_access_addr_t reg; |
125 | 127 | ||
126 | reg.value = 0; |
128 | reg.value = 0; |
127 | reg.tlb_entry = entry; |
129 | reg.tlb_entry = entry; |
128 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
130 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
129 | } |
131 | } |
130 | 132 | ||
131 | /** Read IMMU TLB Tag Read Register. |
133 | /** Read IMMU TLB Tag Read Register. |
132 | * |
134 | * |
133 | * @param entry TLB Entry index. |
135 | * @param entry TLB Entry index. |
134 | * |
136 | * |
135 | * @return Current value of specified IMMU TLB Tag Read Register. |
137 | * @return Current value of specified IMMU TLB Tag Read Register. |
136 | */ |
138 | */ |
137 | static inline __u64 itlb_tag_read(index_t entry) |
139 | static inline __u64 itlb_tag_read_read(index_t entry) |
138 | { |
140 | { |
139 | tlb_tag_read_addr_t tag; |
141 | tlb_tag_read_addr_t tag; |
140 | 142 | ||
141 | tag.value = 0; |
143 | tag.value = 0; |
142 | tag.tlb_entry = entry; |
144 | tag.tlb_entry = entry; |
143 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
145 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
144 | } |
146 | } |
145 | 147 | ||
146 | /** Read DMMU TLB Tag Read Register. |
148 | /** Read DMMU TLB Tag Read Register. |
147 | * |
149 | * |
148 | * @param entry TLB Entry index. |
150 | * @param entry TLB Entry index. |
149 | * |
151 | * |
150 | * @return Current value of specified DMMU TLB Tag Read Register. |
152 | * @return Current value of specified DMMU TLB Tag Read Register. |
151 | */ |
153 | */ |
152 | static inline __u64 dtlb_tag_read(index_t entry) |
154 | static inline __u64 dtlb_tag_read_read(index_t entry) |
153 | { |
155 | { |
154 | tlb_tag_read_addr_t tag; |
156 | tlb_tag_read_addr_t tag; |
155 | 157 | ||
156 | tag.value = 0; |
158 | tag.value = 0; |
157 | tag.tlb_entry = entry; |
159 | tag.tlb_entry = entry; |
158 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
160 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
159 | } |
161 | } |
- | 162 | ||
- | 163 | /** Write IMMU TLB Tag Access Register. |
|
- | 164 | * |
|
- | 165 | * @param v Value to be written. |
|
- | 166 | */ |
|
- | 167 | static inline void itlb_tag_access_write(__u64 v) |
|
- | 168 | { |
|
- | 169 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
|
- | 170 | flush(); |
|
- | 171 | } |
|
- | 172 | ||
- | 173 | /** Write DMMU TLB Tag Access Register. |
|
- | 174 | * |
|
- | 175 | * @param v Value to be written. |
|
- | 176 | */ |
|
- | 177 | static inline void dtlb_tag_access_write(__u64 v) |
|
- | 178 | { |
|
- | 179 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
|
- | 180 | flush(); |
|
- | 181 | } |
|
- | 182 | ||
- | 183 | /** Write IMMU TLB Data in Register. |
|
- | 184 | * |
|
- | 185 | * @param v Value to be written. |
|
- | 186 | */ |
|
- | 187 | static inline void itlb_data_in_write(__u64 v) |
|
- | 188 | { |
|
- | 189 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
|
- | 190 | flush(); |
|
- | 191 | } |
|
- | 192 | ||
- | 193 | /** Write DMMU TLB Data in Register. |
|
- | 194 | * |
|
- | 195 | * @param v Value to be written. |
|
- | 196 | */ |
|
- | 197 | static inline void dtlb_data_in_write(__u64 v) |
|
- | 198 | { |
|
- | 199 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
|
- | 200 | flush(); |
|
- | 201 | } |
|
160 | 202 | ||
161 | #endif |
203 | #endif |
162 | 204 |