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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __sparc64_TLB_H__ |
29 | #ifndef __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
31 | 31 | ||
32 | #include <arch/mm/tte.h> |
32 | #include <arch/mm/tte.h> |
33 | #include <arch/mm/mmu.h> |
33 | #include <arch/mm/mmu.h> |
34 | #include <arch/mm/page.h> |
34 | #include <arch/mm/page.h> |
35 | #include <arch/asm.h> |
35 | #include <arch/asm.h> |
36 | #include <arch/barrier.h> |
36 | #include <arch/barrier.h> |
37 | #include <arch/types.h> |
37 | #include <arch/types.h> |
38 | #include <typedefs.h> |
38 | #include <typedefs.h> |
39 | 39 | ||
40 | #define ITLB_ENTRY_COUNT 64 |
40 | #define ITLB_ENTRY_COUNT 64 |
41 | #define DTLB_ENTRY_COUNT 64 |
41 | #define DTLB_ENTRY_COUNT 64 |
42 | 42 | ||
43 | /** Page sizes. */ |
43 | /** Page sizes. */ |
44 | #define PAGESIZE_8K 0 |
44 | #define PAGESIZE_8K 0 |
45 | #define PAGESIZE_64K 1 |
45 | #define PAGESIZE_64K 1 |
46 | #define PAGESIZE_512K 2 |
46 | #define PAGESIZE_512K 2 |
47 | #define PAGESIZE_4M 3 |
47 | #define PAGESIZE_4M 3 |
48 | 48 | ||
- | 49 | /** Bit width of the TLB-locked portion of kernel address space. */ |
|
- | 50 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
|
- | 51 | ||
49 | union tlb_context_reg { |
52 | union tlb_context_reg { |
50 | __u64 v; |
53 | __u64 v; |
51 | struct { |
54 | struct { |
52 | unsigned long : 51; |
55 | unsigned long : 51; |
53 | unsigned context : 13; /**< Context/ASID. */ |
56 | unsigned context : 13; /**< Context/ASID. */ |
54 | } __attribute__ ((packed)); |
57 | } __attribute__ ((packed)); |
55 | }; |
58 | }; |
56 | typedef union tlb_context_reg tlb_context_reg_t; |
59 | typedef union tlb_context_reg tlb_context_reg_t; |
57 | 60 | ||
58 | /** I-/D-TLB Data In/Access Register type. */ |
61 | /** I-/D-TLB Data In/Access Register type. */ |
59 | typedef tte_data_t tlb_data_t; |
62 | typedef tte_data_t tlb_data_t; |
60 | 63 | ||
61 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
64 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
62 | union tlb_data_access_addr { |
65 | union tlb_data_access_addr { |
63 | __u64 value; |
66 | __u64 value; |
64 | struct { |
67 | struct { |
65 | __u64 : 55; |
68 | __u64 : 55; |
66 | unsigned tlb_entry : 6; |
69 | unsigned tlb_entry : 6; |
67 | unsigned : 3; |
70 | unsigned : 3; |
68 | } __attribute__ ((packed)); |
71 | } __attribute__ ((packed)); |
69 | }; |
72 | }; |
70 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
73 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
71 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
74 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
72 | 75 | ||
73 | /** I-/D-TLB Tag Read Register. */ |
76 | /** I-/D-TLB Tag Read Register. */ |
74 | union tlb_tag_read_reg { |
77 | union tlb_tag_read_reg { |
75 | __u64 value; |
78 | __u64 value; |
76 | struct { |
79 | struct { |
77 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
80 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
78 | unsigned context : 13; /**< Context identifier. */ |
81 | unsigned context : 13; /**< Context identifier. */ |
79 | } __attribute__ ((packed)); |
82 | } __attribute__ ((packed)); |
80 | }; |
83 | }; |
81 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
84 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
82 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
85 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
83 | 86 | ||
84 | /** TLB Demap Operation types. */ |
87 | /** TLB Demap Operation types. */ |
85 | #define TLB_DEMAP_PAGE 0 |
88 | #define TLB_DEMAP_PAGE 0 |
86 | #define TLB_DEMAP_CONTEXT 1 |
89 | #define TLB_DEMAP_CONTEXT 1 |
87 | 90 | ||
88 | /** TLB Demap Operation Context register encodings. */ |
91 | /** TLB Demap Operation Context register encodings. */ |
89 | #define TLB_DEMAP_PRIMARY 0 |
92 | #define TLB_DEMAP_PRIMARY 0 |
90 | #define TLB_DEMAP_SECONDARY 1 |
93 | #define TLB_DEMAP_SECONDARY 1 |
91 | #define TLB_DEMAP_NUCLEUS 2 |
94 | #define TLB_DEMAP_NUCLEUS 2 |
92 | 95 | ||
93 | /** TLB Demap Operation Address. */ |
96 | /** TLB Demap Operation Address. */ |
94 | union tlb_demap_addr { |
97 | union tlb_demap_addr { |
95 | __u64 value; |
98 | __u64 value; |
96 | struct { |
99 | struct { |
97 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
100 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
98 | unsigned : 6; /**< Ignored. */ |
101 | unsigned : 6; /**< Ignored. */ |
99 | unsigned type : 1; /**< The type of demap operation. */ |
102 | unsigned type : 1; /**< The type of demap operation. */ |
100 | unsigned context : 2; /**< Context register selection. */ |
103 | unsigned context : 2; /**< Context register selection. */ |
101 | unsigned : 4; /**< Zero. */ |
104 | unsigned : 4; /**< Zero. */ |
102 | } __attribute__ ((packed)); |
105 | } __attribute__ ((packed)); |
103 | }; |
106 | }; |
104 | typedef union tlb_demap_addr tlb_demap_addr_t; |
107 | typedef union tlb_demap_addr tlb_demap_addr_t; |
105 | 108 | ||
106 | /** TLB Synchronous Fault Status Register. */ |
109 | /** TLB Synchronous Fault Status Register. */ |
107 | union tlb_sfsr_reg { |
110 | union tlb_sfsr_reg { |
108 | __u64 value; |
111 | __u64 value; |
109 | struct { |
112 | struct { |
110 | unsigned long : 39; /**< Implementation dependent. */ |
113 | unsigned long : 39; /**< Implementation dependent. */ |
111 | unsigned nf : 1; /**< Nonfaulting load. */ |
114 | unsigned nf : 1; /**< Nonfaulting load. */ |
112 | unsigned asi : 8; /**< ASI. */ |
115 | unsigned asi : 8; /**< ASI. */ |
113 | unsigned tm : 1; /**< TLB miss. */ |
116 | unsigned tm : 1; /**< TLB miss. */ |
114 | unsigned : 1; |
117 | unsigned : 1; |
115 | unsigned ft : 7; /**< Fault type. */ |
118 | unsigned ft : 7; /**< Fault type. */ |
116 | unsigned e : 1; /**< Side-effect bit. */ |
119 | unsigned e : 1; /**< Side-effect bit. */ |
117 | unsigned ct : 2; /**< Context Register selection. */ |
120 | unsigned ct : 2; /**< Context Register selection. */ |
118 | unsigned pr : 1; /**< Privilege bit. */ |
121 | unsigned pr : 1; /**< Privilege bit. */ |
119 | unsigned w : 1; /**< Write bit. */ |
122 | unsigned w : 1; /**< Write bit. */ |
120 | unsigned ow : 1; /**< Overwrite bit. */ |
123 | unsigned ow : 1; /**< Overwrite bit. */ |
121 | unsigned fv : 1; /**< Fault Valid bit. */ |
124 | unsigned fv : 1; /**< Fault Valid bit. */ |
122 | } __attribute__ ((packed)); |
125 | } __attribute__ ((packed)); |
123 | }; |
126 | }; |
124 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
127 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
125 | 128 | ||
126 | /** Read MMU Primary Context Register. |
129 | /** Read MMU Primary Context Register. |
127 | * |
130 | * |
128 | * @return Current value of Primary Context Register. |
131 | * @return Current value of Primary Context Register. |
129 | */ |
132 | */ |
130 | static inline __u64 mmu_primary_context_read(void) |
133 | static inline __u64 mmu_primary_context_read(void) |
131 | { |
134 | { |
132 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
135 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
133 | } |
136 | } |
134 | 137 | ||
135 | /** Write MMU Primary Context Register. |
138 | /** Write MMU Primary Context Register. |
136 | * |
139 | * |
137 | * @param v New value of Primary Context Register. |
140 | * @param v New value of Primary Context Register. |
138 | */ |
141 | */ |
139 | static inline void mmu_primary_context_write(__u64 v) |
142 | static inline void mmu_primary_context_write(__u64 v) |
140 | { |
143 | { |
141 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
144 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
142 | flush(); |
145 | flush(); |
143 | } |
146 | } |
144 | 147 | ||
145 | /** Read MMU Secondary Context Register. |
148 | /** Read MMU Secondary Context Register. |
146 | * |
149 | * |
147 | * @return Current value of Secondary Context Register. |
150 | * @return Current value of Secondary Context Register. |
148 | */ |
151 | */ |
149 | static inline __u64 mmu_secondary_context_read(void) |
152 | static inline __u64 mmu_secondary_context_read(void) |
150 | { |
153 | { |
151 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
154 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
152 | } |
155 | } |
153 | 156 | ||
154 | /** Write MMU Primary Context Register. |
157 | /** Write MMU Primary Context Register. |
155 | * |
158 | * |
156 | * @param v New value of Primary Context Register. |
159 | * @param v New value of Primary Context Register. |
157 | */ |
160 | */ |
158 | static inline void mmu_secondary_context_write(__u64 v) |
161 | static inline void mmu_secondary_context_write(__u64 v) |
159 | { |
162 | { |
160 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
163 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
161 | flush(); |
164 | flush(); |
162 | } |
165 | } |
163 | 166 | ||
164 | /** Read IMMU TLB Data Access Register. |
167 | /** Read IMMU TLB Data Access Register. |
165 | * |
168 | * |
166 | * @param entry TLB Entry index. |
169 | * @param entry TLB Entry index. |
167 | * |
170 | * |
168 | * @return Current value of specified IMMU TLB Data Access Register. |
171 | * @return Current value of specified IMMU TLB Data Access Register. |
169 | */ |
172 | */ |
170 | static inline __u64 itlb_data_access_read(index_t entry) |
173 | static inline __u64 itlb_data_access_read(index_t entry) |
171 | { |
174 | { |
172 | tlb_data_access_addr_t reg; |
175 | tlb_data_access_addr_t reg; |
173 | 176 | ||
174 | reg.value = 0; |
177 | reg.value = 0; |
175 | reg.tlb_entry = entry; |
178 | reg.tlb_entry = entry; |
176 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
179 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
177 | } |
180 | } |
178 | 181 | ||
179 | /** Write IMMU TLB Data Access Register. |
182 | /** Write IMMU TLB Data Access Register. |
180 | * |
183 | * |
181 | * @param entry TLB Entry index. |
184 | * @param entry TLB Entry index. |
182 | * @param value Value to be written. |
185 | * @param value Value to be written. |
183 | */ |
186 | */ |
184 | static inline void itlb_data_access_write(index_t entry, __u64 value) |
187 | static inline void itlb_data_access_write(index_t entry, __u64 value) |
185 | { |
188 | { |
186 | tlb_data_access_addr_t reg; |
189 | tlb_data_access_addr_t reg; |
187 | 190 | ||
188 | reg.value = 0; |
191 | reg.value = 0; |
189 | reg.tlb_entry = entry; |
192 | reg.tlb_entry = entry; |
190 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
193 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
191 | flush(); |
194 | flush(); |
192 | } |
195 | } |
193 | 196 | ||
194 | /** Read DMMU TLB Data Access Register. |
197 | /** Read DMMU TLB Data Access Register. |
195 | * |
198 | * |
196 | * @param entry TLB Entry index. |
199 | * @param entry TLB Entry index. |
197 | * |
200 | * |
198 | * @return Current value of specified DMMU TLB Data Access Register. |
201 | * @return Current value of specified DMMU TLB Data Access Register. |
199 | */ |
202 | */ |
200 | static inline __u64 dtlb_data_access_read(index_t entry) |
203 | static inline __u64 dtlb_data_access_read(index_t entry) |
201 | { |
204 | { |
202 | tlb_data_access_addr_t reg; |
205 | tlb_data_access_addr_t reg; |
203 | 206 | ||
204 | reg.value = 0; |
207 | reg.value = 0; |
205 | reg.tlb_entry = entry; |
208 | reg.tlb_entry = entry; |
206 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
209 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
207 | } |
210 | } |
208 | 211 | ||
209 | /** Write DMMU TLB Data Access Register. |
212 | /** Write DMMU TLB Data Access Register. |
210 | * |
213 | * |
211 | * @param entry TLB Entry index. |
214 | * @param entry TLB Entry index. |
212 | * @param value Value to be written. |
215 | * @param value Value to be written. |
213 | */ |
216 | */ |
214 | static inline void dtlb_data_access_write(index_t entry, __u64 value) |
217 | static inline void dtlb_data_access_write(index_t entry, __u64 value) |
215 | { |
218 | { |
216 | tlb_data_access_addr_t reg; |
219 | tlb_data_access_addr_t reg; |
217 | 220 | ||
218 | reg.value = 0; |
221 | reg.value = 0; |
219 | reg.tlb_entry = entry; |
222 | reg.tlb_entry = entry; |
220 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
223 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
221 | flush(); |
224 | flush(); |
222 | } |
225 | } |
223 | 226 | ||
224 | /** Read IMMU TLB Tag Read Register. |
227 | /** Read IMMU TLB Tag Read Register. |
225 | * |
228 | * |
226 | * @param entry TLB Entry index. |
229 | * @param entry TLB Entry index. |
227 | * |
230 | * |
228 | * @return Current value of specified IMMU TLB Tag Read Register. |
231 | * @return Current value of specified IMMU TLB Tag Read Register. |
229 | */ |
232 | */ |
230 | static inline __u64 itlb_tag_read_read(index_t entry) |
233 | static inline __u64 itlb_tag_read_read(index_t entry) |
231 | { |
234 | { |
232 | tlb_tag_read_addr_t tag; |
235 | tlb_tag_read_addr_t tag; |
233 | 236 | ||
234 | tag.value = 0; |
237 | tag.value = 0; |
235 | tag.tlb_entry = entry; |
238 | tag.tlb_entry = entry; |
236 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
239 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
237 | } |
240 | } |
238 | 241 | ||
239 | /** Read DMMU TLB Tag Read Register. |
242 | /** Read DMMU TLB Tag Read Register. |
240 | * |
243 | * |
241 | * @param entry TLB Entry index. |
244 | * @param entry TLB Entry index. |
242 | * |
245 | * |
243 | * @return Current value of specified DMMU TLB Tag Read Register. |
246 | * @return Current value of specified DMMU TLB Tag Read Register. |
244 | */ |
247 | */ |
245 | static inline __u64 dtlb_tag_read_read(index_t entry) |
248 | static inline __u64 dtlb_tag_read_read(index_t entry) |
246 | { |
249 | { |
247 | tlb_tag_read_addr_t tag; |
250 | tlb_tag_read_addr_t tag; |
248 | 251 | ||
249 | tag.value = 0; |
252 | tag.value = 0; |
250 | tag.tlb_entry = entry; |
253 | tag.tlb_entry = entry; |
251 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
254 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
252 | } |
255 | } |
253 | 256 | ||
254 | /** Write IMMU TLB Tag Access Register. |
257 | /** Write IMMU TLB Tag Access Register. |
255 | * |
258 | * |
256 | * @param v Value to be written. |
259 | * @param v Value to be written. |
257 | */ |
260 | */ |
258 | static inline void itlb_tag_access_write(__u64 v) |
261 | static inline void itlb_tag_access_write(__u64 v) |
259 | { |
262 | { |
260 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
263 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
261 | flush(); |
264 | flush(); |
262 | } |
265 | } |
263 | 266 | ||
264 | /** Read IMMU TLB Tag Access Register. |
267 | /** Read IMMU TLB Tag Access Register. |
265 | * |
268 | * |
266 | * @return Current value of IMMU TLB Tag Access Register. |
269 | * @return Current value of IMMU TLB Tag Access Register. |
267 | */ |
270 | */ |
268 | static inline __u64 itlb_tag_access_read(void) |
271 | static inline __u64 itlb_tag_access_read(void) |
269 | { |
272 | { |
270 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
273 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
271 | } |
274 | } |
272 | 275 | ||
273 | /** Write DMMU TLB Tag Access Register. |
276 | /** Write DMMU TLB Tag Access Register. |
274 | * |
277 | * |
275 | * @param v Value to be written. |
278 | * @param v Value to be written. |
276 | */ |
279 | */ |
277 | static inline void dtlb_tag_access_write(__u64 v) |
280 | static inline void dtlb_tag_access_write(__u64 v) |
278 | { |
281 | { |
279 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
282 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
280 | flush(); |
283 | flush(); |
281 | } |
284 | } |
282 | 285 | ||
283 | /** Read DMMU TLB Tag Access Register. |
286 | /** Read DMMU TLB Tag Access Register. |
284 | * |
287 | * |
285 | * @return Current value of DMMU TLB Tag Access Register. |
288 | * @return Current value of DMMU TLB Tag Access Register. |
286 | */ |
289 | */ |
287 | static inline __u64 dtlb_tag_access_read(void) |
290 | static inline __u64 dtlb_tag_access_read(void) |
288 | { |
291 | { |
289 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
292 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
290 | } |
293 | } |
291 | 294 | ||
292 | 295 | ||
293 | /** Write IMMU TLB Data in Register. |
296 | /** Write IMMU TLB Data in Register. |
294 | * |
297 | * |
295 | * @param v Value to be written. |
298 | * @param v Value to be written. |
296 | */ |
299 | */ |
297 | static inline void itlb_data_in_write(__u64 v) |
300 | static inline void itlb_data_in_write(__u64 v) |
298 | { |
301 | { |
299 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
302 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
300 | flush(); |
303 | flush(); |
301 | } |
304 | } |
302 | 305 | ||
303 | /** Write DMMU TLB Data in Register. |
306 | /** Write DMMU TLB Data in Register. |
304 | * |
307 | * |
305 | * @param v Value to be written. |
308 | * @param v Value to be written. |
306 | */ |
309 | */ |
307 | static inline void dtlb_data_in_write(__u64 v) |
310 | static inline void dtlb_data_in_write(__u64 v) |
308 | { |
311 | { |
309 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
312 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
310 | flush(); |
313 | flush(); |
311 | } |
314 | } |
312 | 315 | ||
313 | /** Read ITLB Synchronous Fault Status Register. |
316 | /** Read ITLB Synchronous Fault Status Register. |
314 | * |
317 | * |
315 | * @return Current content of I-SFSR register. |
318 | * @return Current content of I-SFSR register. |
316 | */ |
319 | */ |
317 | static inline __u64 itlb_sfsr_read(void) |
320 | static inline __u64 itlb_sfsr_read(void) |
318 | { |
321 | { |
319 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
322 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
320 | } |
323 | } |
321 | 324 | ||
322 | /** Write ITLB Synchronous Fault Status Register. |
325 | /** Write ITLB Synchronous Fault Status Register. |
323 | * |
326 | * |
324 | * @param v New value of I-SFSR register. |
327 | * @param v New value of I-SFSR register. |
325 | */ |
328 | */ |
326 | static inline void itlb_sfsr_write(__u64 v) |
329 | static inline void itlb_sfsr_write(__u64 v) |
327 | { |
330 | { |
328 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
331 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
329 | flush(); |
332 | flush(); |
330 | } |
333 | } |
331 | 334 | ||
332 | /** Read DTLB Synchronous Fault Status Register. |
335 | /** Read DTLB Synchronous Fault Status Register. |
333 | * |
336 | * |
334 | * @return Current content of D-SFSR register. |
337 | * @return Current content of D-SFSR register. |
335 | */ |
338 | */ |
336 | static inline __u64 dtlb_sfsr_read(void) |
339 | static inline __u64 dtlb_sfsr_read(void) |
337 | { |
340 | { |
338 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
341 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
339 | } |
342 | } |
340 | 343 | ||
341 | /** Write DTLB Synchronous Fault Status Register. |
344 | /** Write DTLB Synchronous Fault Status Register. |
342 | * |
345 | * |
343 | * @param v New value of D-SFSR register. |
346 | * @param v New value of D-SFSR register. |
344 | */ |
347 | */ |
345 | static inline void dtlb_sfsr_write(__u64 v) |
348 | static inline void dtlb_sfsr_write(__u64 v) |
346 | { |
349 | { |
347 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
350 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
348 | flush(); |
351 | flush(); |
349 | } |
352 | } |
350 | 353 | ||
351 | /** Read DTLB Synchronous Fault Address Register. |
354 | /** Read DTLB Synchronous Fault Address Register. |
352 | * |
355 | * |
353 | * @return Current content of D-SFAR register. |
356 | * @return Current content of D-SFAR register. |
354 | */ |
357 | */ |
355 | static inline __u64 dtlb_sfar_read(void) |
358 | static inline __u64 dtlb_sfar_read(void) |
356 | { |
359 | { |
357 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
360 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
358 | } |
361 | } |
359 | 362 | ||
360 | /** Perform IMMU TLB Demap Operation. |
363 | /** Perform IMMU TLB Demap Operation. |
361 | * |
364 | * |
362 | * @param type Selects between context and page demap. |
365 | * @param type Selects between context and page demap. |
363 | * @param context_encoding Specifies which Context register has Context ID for demap. |
366 | * @param context_encoding Specifies which Context register has Context ID for demap. |
364 | * @param page Address which is on the page to be demapped. |
367 | * @param page Address which is on the page to be demapped. |
365 | */ |
368 | */ |
366 | static inline void itlb_demap(int type, int context_encoding, __address page) |
369 | static inline void itlb_demap(int type, int context_encoding, __address page) |
367 | { |
370 | { |
368 | tlb_demap_addr_t da; |
371 | tlb_demap_addr_t da; |
369 | page_address_t pg; |
372 | page_address_t pg; |
370 | 373 | ||
371 | da.value = 0; |
374 | da.value = 0; |
372 | pg.address = page; |
375 | pg.address = page; |
373 | 376 | ||
374 | da.type = type; |
377 | da.type = type; |
375 | da.context = context_encoding; |
378 | da.context = context_encoding; |
376 | da.vpn = pg.vpn; |
379 | da.vpn = pg.vpn; |
377 | 380 | ||
378 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
381 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
379 | flush(); |
382 | flush(); |
380 | } |
383 | } |
381 | 384 | ||
382 | /** Perform DMMU TLB Demap Operation. |
385 | /** Perform DMMU TLB Demap Operation. |
383 | * |
386 | * |
384 | * @param type Selects between context and page demap. |
387 | * @param type Selects between context and page demap. |
385 | * @param context_encoding Specifies which Context register has Context ID for demap. |
388 | * @param context_encoding Specifies which Context register has Context ID for demap. |
386 | * @param page Address which is on the page to be demapped. |
389 | * @param page Address which is on the page to be demapped. |
387 | */ |
390 | */ |
388 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
391 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
389 | { |
392 | { |
390 | tlb_demap_addr_t da; |
393 | tlb_demap_addr_t da; |
391 | page_address_t pg; |
394 | page_address_t pg; |
392 | 395 | ||
393 | da.value = 0; |
396 | da.value = 0; |
394 | pg.address = page; |
397 | pg.address = page; |
395 | 398 | ||
396 | da.type = type; |
399 | da.type = type; |
397 | da.context = context_encoding; |
400 | da.context = context_encoding; |
398 | da.vpn = pg.vpn; |
401 | da.vpn = pg.vpn; |
399 | 402 | ||
400 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
403 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
401 | flush(); |
404 | flush(); |
402 | } |
405 | } |
403 | 406 | ||
404 | extern void fast_instruction_access_mmu_miss(void); |
407 | extern void fast_instruction_access_mmu_miss(void); |
405 | extern void fast_data_access_mmu_miss(void); |
408 | extern void fast_data_access_mmu_miss(void); |
406 | extern void fast_data_access_protection(void); |
409 | extern void fast_data_access_protection(void); |
407 | 410 | ||
408 | extern void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable); |
411 | extern void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable); |
409 | 412 | ||
410 | #endif |
413 | #endif |
411 | 414 |