WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __sparc64_ASM_H__
#define __sparc64_ASM_H__
 
#include <typedefs.h>
#include <arch/types.h>
#include <arch/register.h>
#include <config.h>
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline __u64 pstate_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param New value of PSTATE register.
 */
static inline void pstate_write(__u64 v)
{
    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline __u64 tick_compare_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param New value of TICK_comapre register.
 */
static inline void tick_compare_write(__u64 v)
{
    __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline __u64 tick_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param New value of TICK register.
 */
static inline void tick_write(__u64 v)
{
    __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline __u64 softint_read(void)
{
    __u64 v;
 
    __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param New value of SOFTINT register.
 */
static inline void softint_write(__u64 v)
{
    __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(__u64 v)
{
    __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    __u64 value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    __u64 value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
   
    return v;
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline __u64 ver_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline __u64 tba_read(void)
{
    __u64 v;
   
    __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param New value of TBA.
 */
static inline void tba_write(__u64 v)
{
    __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load __u64 from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline __u64 asi_u64_read(asi_t asi, __address va)
{
    __u64 v;
   
    __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
   
    return v;
}
 
/** Store __u64 to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
{
    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
}
 
 
 
void cpu_halt(void);
void cpu_sleep(void);
void asm_delay_loop(__u32 t);
 
#endif
 

Rev 664	Rev 665
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __sparc64_ASM_H__	29	#ifndef __sparc64_ASM_H__
30	#define __sparc64_ASM_H__	30	#define __sparc64_ASM_H__
31		31
32	#include <typedefs.h>	32	#include <typedefs.h>
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#include <arch/register.h>	34	#include <arch/register.h>
35	#include <config.h>	35	#include <config.h>
36		36
37	/** Read Processor State register.	37	/** Read Processor State register.
38	*	38	*
39	* @return Value of PSTATE register.	39	* @return Value of PSTATE register.
40	*/	40	*/
41	static inline __u64 pstate_read(void)	41	static inline __u64 pstate_read(void)
42	{	42	{
43	__u64 v;	43	__u64 v;
44		44
45	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));	45	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
46		46
47	return v;	47	return v;
48	}	48	}
49		49
50	/** Write Processor State register.	50	/** Write Processor State register.
51	*	51	*
52	* @param New value of PSTATE register.	52	* @param New value of PSTATE register.
53	*/	53	*/
54	static inline void pstate_write(__u64 v)	54	static inline void pstate_write(__u64 v)
55	{	55	{
56	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	56	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
57	}	57	}
58		58
59	/** Read TICK_compare Register.	59	/** Read TICK_compare Register.
60	*	60	*
61	* @return Value of TICK_comapre register.	61	* @return Value of TICK_comapre register.
62	*/	62	*/
63	static inline __u64 tick_compare_read(void)	63	static inline __u64 tick_compare_read(void)
64	{	64	{
65	__u64 v;	65	__u64 v;
66		66
67	__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	67	__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
68		68
69	return v;	69	return v;
70	}	70	}
71		71
72	/** Write TICK_compare Register.	72	/** Write TICK_compare Register.
73	*	73	*
74	* @param New value of TICK_comapre register.	74	* @param New value of TICK_comapre register.
75	*/	75	*/
76	static inline void tick_compare_write(__u64 v)	76	static inline void tick_compare_write(__u64 v)
77	{	77	{
78	__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	78	__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
79	}	79	}
80		80
81	/** Read TICK Register.	81	/** Read TICK Register.
82	*	82	*
83	* @return Value of TICK register.	83	* @return Value of TICK register.
84	*/	84	*/
85	static inline __u64 tick_read(void)	85	static inline __u64 tick_read(void)
86	{	86	{
87	__u64 v;	87	__u64 v;
88		88
89	__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));	89	__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
90		90
91	return v;	91	return v;
92	}	92	}
93		93
94	/** Write TICK Register.	94	/** Write TICK Register.
95	*	95	*
96	* @param New value of TICK register.	96	* @param New value of TICK register.
97	*/	97	*/
98	static inline void tick_write(__u64 v)	98	static inline void tick_write(__u64 v)
99	{	99	{
100	__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	100	__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
101	}	101	}
102		102
103	/** Read SOFTINT Register.	103	/** Read SOFTINT Register.
104	*	104	*
105	* @return Value of SOFTINT register.	105	* @return Value of SOFTINT register.
106	*/	106	*/
107	static inline __u64 softint_read(void)	107	static inline __u64 softint_read(void)
108	{	108	{
109	__u64 v;	109	__u64 v;
110		110
111	__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));	111	__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
112		112
113	return v;	113	return v;
114	}	114	}
115		115
116	/** Write SOFTINT Register.	116	/** Write SOFTINT Register.
117	*	117	*
118	* @param New value of SOFTINT register.	118	* @param New value of SOFTINT register.
119	*/	119	*/
120	static inline void softint_write(__u64 v)	120	static inline void softint_write(__u64 v)
121	{	121	{
122	__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	122	__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
123	}	123	}
124		124
-		125	/** Write CLEAR_SOFTINT Register.
-		126	*
-		127	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
-		128	*
-		129	* @param New value of CLEAR_SOFTINT register.
-		130	*/
-		131	static inline void clear_softint_write(__u64 v)
-		132	{
-		133	__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
-		134	}
-		135
125	/** Enable interrupts.	136	/** Enable interrupts.
126	*	137	*
127	* Enable interrupts and return previous	138	* Enable interrupts and return previous
128	* value of IPL.	139	* value of IPL.
129	*	140	*
130	* @return Old interrupt priority level.	141	* @return Old interrupt priority level.
131	*/	142	*/
132	static inline ipl_t interrupts_enable(void) {	143	static inline ipl_t interrupts_enable(void) {
133	pstate_reg_t pstate;	144	pstate_reg_t pstate;
134	__u64 value;	145	__u64 value;
135		146
136	value = pstate_read();	147	value = pstate_read();
137	pstate.value = value;	148	pstate.value = value;
138	pstate.ie = true;	149	pstate.ie = true;
139	pstate_write(pstate.value);	150	pstate_write(pstate.value);
140		151
141	return (ipl_t) value;	152	return (ipl_t) value;
142	}	153	}
143		154
144	/** Disable interrupts.	155	/** Disable interrupts.
145	*	156	*
146	* Disable interrupts and return previous	157	* Disable interrupts and return previous
147	* value of IPL.	158	* value of IPL.
148	*	159	*
149	* @return Old interrupt priority level.	160	* @return Old interrupt priority level.
150	*/	161	*/
151	static inline ipl_t interrupts_disable(void) {	162	static inline ipl_t interrupts_disable(void) {
152	pstate_reg_t pstate;	163	pstate_reg_t pstate;
153	__u64 value;	164	__u64 value;
154		165
155	value = pstate_read();	166	value = pstate_read();
156	pstate.value = value;	167	pstate.value = value;
157	pstate.ie = false;	168	pstate.ie = false;
158	pstate_write(pstate.value);	169	pstate_write(pstate.value);
159		170
160	return (ipl_t) value;	171	return (ipl_t) value;
161	}	172	}
162		173
163	/** Restore interrupt priority level.	174	/** Restore interrupt priority level.
164	*	175	*
165	* Restore IPL.	176	* Restore IPL.
166	*	177	*
167	* @param ipl Saved interrupt priority level.	178	* @param ipl Saved interrupt priority level.
168	*/	179	*/
169	static inline void interrupts_restore(ipl_t ipl) {	180	static inline void interrupts_restore(ipl_t ipl) {
170	pstate_reg_t pstate;	181	pstate_reg_t pstate;
171		182
172	pstate.value = pstate_read();	183	pstate.value = pstate_read();
173	pstate.ie = ((pstate_reg_t) ipl).ie;	184	pstate.ie = ((pstate_reg_t) ipl).ie;
174	pstate_write(pstate.value);	185	pstate_write(pstate.value);
175	}	186	}
176		187
177	/** Return interrupt priority level.	188	/** Return interrupt priority level.
178	*	189	*
179	* Return IPL.	190	* Return IPL.
180	*	191	*
181	* @return Current interrupt priority level.	192	* @return Current interrupt priority level.
182	*/	193	*/
183	static inline ipl_t interrupts_read(void) {	194	static inline ipl_t interrupts_read(void) {
184	return (ipl_t) pstate_read();	195	return (ipl_t) pstate_read();
185	}	196	}
186		197
187	/** Return base address of current stack.	198	/** Return base address of current stack.
188	*	199	*
189	* Return the base address of the current stack.	200	* Return the base address of the current stack.
190	* The stack is assumed to be STACK_SIZE bytes long.	201	* The stack is assumed to be STACK_SIZE bytes long.
191	* The stack must start on page boundary.	202	* The stack must start on page boundary.
192	*/	203	*/
193	static inline __address get_stack_base(void)	204	static inline __address get_stack_base(void)
194	{	205	{
195	__address v;	206	__address v;
196		207
197	__asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));	208	__asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
198		209
199	return v;	210	return v;
200	}	211	}
201		212
202	/** Read Version Register.	213	/** Read Version Register.
203	*	214	*
204	* @return Value of VER register.	215	* @return Value of VER register.
205	*/	216	*/
206	static inline __u64 ver_read(void)	217	static inline __u64 ver_read(void)
207	{	218	{
208	__u64 v;	219	__u64 v;
209		220
210	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));	221	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
211		222
212	return v;	223	return v;
213	}	224	}
214		225
215	/** Read Trap Base Address register.	226	/** Read Trap Base Address register.
216	*	227	*
217	* @return Current value in TBA.	228	* @return Current value in TBA.
218	*/	229	*/
219	static inline __u64 tba_read(void)	230	static inline __u64 tba_read(void)
220	{	231	{
221	__u64 v;	232	__u64 v;
222		233
223	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));	234	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
224		235
225	return v;	236	return v;
226	}	237	}
227		238
228	/** Write Trap Base Address register.	239	/** Write Trap Base Address register.
229	*	240	*
230	* @param New value of TBA.	241	* @param New value of TBA.
231	*/	242	*/
232	static inline void tba_write(__u64 v)	243	static inline void tba_write(__u64 v)
233	{	244	{
234	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	245	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
235	}	246	}
236		247
237	/** Load __u64 from alternate space.	248	/** Load __u64 from alternate space.
238	*	249	*
239	* @param asi ASI determining the alternate space.	250	* @param asi ASI determining the alternate space.
240	* @param va Virtual address within the ASI.	251	* @param va Virtual address within the ASI.
241	*	252	*
242	* @return Value read from the virtual address in the specified address space.	253	* @return Value read from the virtual address in the specified address space.
243	*/	254	*/
244	static inline __u64 asi_u64_read(asi_t asi, __address va)	255	static inline __u64 asi_u64_read(asi_t asi, __address va)
245	{	256	{
246	__u64 v;	257	__u64 v;
247		258
248	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));	259	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
249		260
250	return v;	261	return v;
251	}	262	}
252		263
253	/** Store __u64 to alternate space.	264	/** Store __u64 to alternate space.
254	*	265	*
255	* @param asi ASI determining the alternate space.	266	* @param asi ASI determining the alternate space.
256	* @param va Virtual address within the ASI.	267	* @param va Virtual address within the ASI.
257	* @param v Value to be written.	268	* @param v Value to be written.
258	*/	269	*/
259	static inline void asi_u64_write(asi_t asi, __address va, __u64 v)	270	static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
260	{	271	{
261	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");	272	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");
262	}	273	}
263		274
264		275
265		276
266	void cpu_halt(void);	277	void cpu_halt(void);
267	void cpu_sleep(void);	278	void cpu_sleep(void);
268	void asm_delay_loop(__u32 t);	279	void asm_delay_loop(__u32 t);
269		280
270	#endif	281	#endif
271		282

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/sparc64/include/asm.h – Rev 664 → 665