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1 | # |
1 | # |
2 | # Copyright (C) 2005 Martin Decky |
2 | # Copyright (C) 2005 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
30 | 30 | ||
31 | .text |
31 | .text |
32 | 32 | ||
33 | .global userspace_asm |
33 | .global userspace_asm |
34 | .global iret |
34 | .global iret |
35 | .global iret_syscall |
35 | .global iret_syscall |
36 | .global invalidate_bat |
- | |
37 | .global memsetb |
36 | .global memsetb |
38 | .global memcpy |
37 | .global memcpy |
39 | .global memcpy_from_uspace |
38 | .global memcpy_from_uspace |
40 | .global memcpy_to_uspace |
39 | .global memcpy_to_uspace |
41 | .global memcpy_from_uspace_failover_address |
40 | .global memcpy_from_uspace_failover_address |
42 | .global memcpy_to_uspace_failover_address |
41 | .global memcpy_to_uspace_failover_address |
43 | 42 | ||
44 | userspace_asm: |
43 | userspace_asm: |
45 | 44 | ||
46 | # r3 = uspace_uarg |
45 | # r3 = uspace_uarg |
47 | # r4 = stack |
46 | # r4 = stack |
48 | # r5 = entry |
47 | # r5 = entry |
49 | 48 | ||
50 | # disable interrupts |
49 | # disable interrupts |
51 | 50 | ||
52 | mfmsr r31 |
51 | mfmsr r31 |
53 | rlwinm r31, r31, 0, 17, 15 |
52 | rlwinm r31, r31, 0, 17, 15 |
54 | mtmsr r31 |
53 | mtmsr r31 |
55 | 54 | ||
56 | # set entry point |
55 | # set entry point |
57 | 56 | ||
58 | mtsrr0 r5 |
57 | mtsrr0 r5 |
59 | 58 | ||
60 | # set problem state, enable interrupts |
59 | # set problem state, enable interrupts |
61 | 60 | ||
62 | ori r31, r31, msr_pr |
61 | ori r31, r31, msr_pr |
63 | ori r31, r31, msr_ee |
62 | ori r31, r31, msr_ee |
64 | mtsrr1 r31 |
63 | mtsrr1 r31 |
65 | 64 | ||
66 | # set stack |
65 | # set stack |
67 | 66 | ||
68 | mr sp, r4 |
67 | mr sp, r4 |
69 | 68 | ||
70 | # jump to userspace |
69 | # jump to userspace |
71 | 70 | ||
72 | rfi |
71 | rfi |
73 | 72 | ||
74 | iret: |
73 | iret: |
75 | 74 | ||
76 | # disable interrupts |
75 | # disable interrupts |
77 | 76 | ||
78 | mfmsr r31 |
77 | mfmsr r31 |
79 | rlwinm r31, r31, 0, 17, 15 |
78 | rlwinm r31, r31, 0, 17, 15 |
80 | mtmsr r31 |
79 | mtmsr r31 |
81 | 80 | ||
82 | lwz r0, 8(sp) |
81 | lwz r0, 8(sp) |
83 | lwz r2, 12(sp) |
82 | lwz r2, 12(sp) |
84 | lwz r3, 16(sp) |
83 | lwz r3, 16(sp) |
85 | lwz r4, 20(sp) |
84 | lwz r4, 20(sp) |
86 | lwz r5, 24(sp) |
85 | lwz r5, 24(sp) |
87 | lwz r6, 28(sp) |
86 | lwz r6, 28(sp) |
88 | lwz r7, 32(sp) |
87 | lwz r7, 32(sp) |
89 | lwz r8, 36(sp) |
88 | lwz r8, 36(sp) |
90 | lwz r9, 40(sp) |
89 | lwz r9, 40(sp) |
91 | lwz r10, 44(sp) |
90 | lwz r10, 44(sp) |
92 | lwz r11, 48(sp) |
91 | lwz r11, 48(sp) |
93 | lwz r13, 52(sp) |
92 | lwz r13, 52(sp) |
94 | lwz r14, 56(sp) |
93 | lwz r14, 56(sp) |
95 | lwz r15, 60(sp) |
94 | lwz r15, 60(sp) |
96 | lwz r16, 64(sp) |
95 | lwz r16, 64(sp) |
97 | lwz r17, 68(sp) |
96 | lwz r17, 68(sp) |
98 | lwz r18, 72(sp) |
97 | lwz r18, 72(sp) |
99 | lwz r19, 76(sp) |
98 | lwz r19, 76(sp) |
100 | lwz r20, 80(sp) |
99 | lwz r20, 80(sp) |
101 | lwz r21, 84(sp) |
100 | lwz r21, 84(sp) |
102 | lwz r22, 88(sp) |
101 | lwz r22, 88(sp) |
103 | lwz r23, 92(sp) |
102 | lwz r23, 92(sp) |
104 | lwz r24, 96(sp) |
103 | lwz r24, 96(sp) |
105 | lwz r25, 100(sp) |
104 | lwz r25, 100(sp) |
106 | lwz r26, 104(sp) |
105 | lwz r26, 104(sp) |
107 | lwz r27, 108(sp) |
106 | lwz r27, 108(sp) |
108 | lwz r28, 112(sp) |
107 | lwz r28, 112(sp) |
109 | lwz r29, 116(sp) |
108 | lwz r29, 116(sp) |
110 | lwz r30, 120(sp) |
109 | lwz r30, 120(sp) |
111 | lwz r31, 124(sp) |
110 | lwz r31, 124(sp) |
112 | 111 | ||
113 | lwz r12, 128(sp) |
112 | lwz r12, 128(sp) |
114 | mtcr r12 |
113 | mtcr r12 |
115 | 114 | ||
116 | lwz r12, 132(sp) |
115 | lwz r12, 132(sp) |
117 | mtsrr0 r12 |
116 | mtsrr0 r12 |
118 | 117 | ||
119 | lwz r12, 136(sp) |
118 | lwz r12, 136(sp) |
120 | mtsrr1 r12 |
119 | mtsrr1 r12 |
121 | 120 | ||
122 | lwz r12, 140(sp) |
121 | lwz r12, 140(sp) |
123 | mtlr r12 |
122 | mtlr r12 |
124 | 123 | ||
125 | lwz r12, 144(sp) |
124 | lwz r12, 144(sp) |
126 | mtctr r12 |
125 | mtctr r12 |
127 | 126 | ||
128 | lwz r12, 148(sp) |
127 | lwz r12, 148(sp) |
129 | mtxer r12 |
128 | mtxer r12 |
130 | 129 | ||
131 | lwz r12, 152(sp) |
130 | lwz r12, 152(sp) |
132 | lwz sp, 156(sp) |
131 | lwz sp, 156(sp) |
133 | 132 | ||
134 | rfi |
133 | rfi |
135 | 134 | ||
136 | iret_syscall: |
135 | iret_syscall: |
137 | 136 | ||
138 | # disable interrupts |
137 | # disable interrupts |
139 | 138 | ||
140 | mfmsr r31 |
139 | mfmsr r31 |
141 | rlwinm r31, r31, 0, 17, 15 |
140 | rlwinm r31, r31, 0, 17, 15 |
142 | mtmsr r31 |
141 | mtmsr r31 |
143 | 142 | ||
144 | lwz r0, 8(sp) |
143 | lwz r0, 8(sp) |
145 | lwz r2, 12(sp) |
144 | lwz r2, 12(sp) |
146 | lwz r4, 20(sp) |
145 | lwz r4, 20(sp) |
147 | lwz r5, 24(sp) |
146 | lwz r5, 24(sp) |
148 | lwz r6, 28(sp) |
147 | lwz r6, 28(sp) |
149 | lwz r7, 32(sp) |
148 | lwz r7, 32(sp) |
150 | lwz r8, 36(sp) |
149 | lwz r8, 36(sp) |
151 | lwz r9, 40(sp) |
150 | lwz r9, 40(sp) |
152 | lwz r10, 44(sp) |
151 | lwz r10, 44(sp) |
153 | lwz r11, 48(sp) |
152 | lwz r11, 48(sp) |
154 | lwz r13, 52(sp) |
153 | lwz r13, 52(sp) |
155 | lwz r14, 56(sp) |
154 | lwz r14, 56(sp) |
156 | lwz r15, 60(sp) |
155 | lwz r15, 60(sp) |
157 | lwz r16, 64(sp) |
156 | lwz r16, 64(sp) |
158 | lwz r17, 68(sp) |
157 | lwz r17, 68(sp) |
159 | lwz r18, 72(sp) |
158 | lwz r18, 72(sp) |
160 | lwz r19, 76(sp) |
159 | lwz r19, 76(sp) |
161 | lwz r20, 80(sp) |
160 | lwz r20, 80(sp) |
162 | lwz r21, 84(sp) |
161 | lwz r21, 84(sp) |
163 | lwz r22, 88(sp) |
162 | lwz r22, 88(sp) |
164 | lwz r23, 92(sp) |
163 | lwz r23, 92(sp) |
165 | lwz r24, 96(sp) |
164 | lwz r24, 96(sp) |
166 | lwz r25, 100(sp) |
165 | lwz r25, 100(sp) |
167 | lwz r26, 104(sp) |
166 | lwz r26, 104(sp) |
168 | lwz r27, 108(sp) |
167 | lwz r27, 108(sp) |
169 | lwz r28, 112(sp) |
168 | lwz r28, 112(sp) |
170 | lwz r29, 116(sp) |
169 | lwz r29, 116(sp) |
171 | lwz r30, 120(sp) |
170 | lwz r30, 120(sp) |
172 | lwz r31, 124(sp) |
171 | lwz r31, 124(sp) |
173 | 172 | ||
174 | lwz r12, 128(sp) |
173 | lwz r12, 128(sp) |
175 | mtcr r12 |
174 | mtcr r12 |
176 | 175 | ||
177 | lwz r12, 132(sp) |
176 | lwz r12, 132(sp) |
178 | mtsrr0 r12 |
177 | mtsrr0 r12 |
179 | 178 | ||
180 | lwz r12, 136(sp) |
179 | lwz r12, 136(sp) |
181 | mtsrr1 r12 |
180 | mtsrr1 r12 |
182 | 181 | ||
183 | lwz r12, 140(sp) |
182 | lwz r12, 140(sp) |
184 | mtlr r12 |
183 | mtlr r12 |
185 | 184 | ||
186 | lwz r12, 144(sp) |
185 | lwz r12, 144(sp) |
187 | mtctr r12 |
186 | mtctr r12 |
188 | 187 | ||
189 | lwz r12, 148(sp) |
188 | lwz r12, 148(sp) |
190 | mtxer r12 |
189 | mtxer r12 |
191 | 190 | ||
192 | lwz r12, 152(sp) |
191 | lwz r12, 152(sp) |
193 | lwz sp, 156(sp) |
192 | lwz sp, 156(sp) |
194 | 193 | ||
195 | rfi |
194 | rfi |
196 | 195 | ||
197 | invalidate_bat: |
- | |
198 | - | ||
199 | # invalidate block address translation registers |
- | |
200 | - | ||
201 | li r14, 0 |
- | |
202 | - | ||
203 | mtspr ibat0u, r14 |
- | |
204 | mtspr ibat0l, r14 |
- | |
205 | - | ||
206 | mtspr ibat1u, r14 |
- | |
207 | mtspr ibat1l, r14 |
- | |
208 | - | ||
209 | mtspr ibat2u, r14 |
- | |
210 | mtspr ibat2l, r14 |
- | |
211 | - | ||
212 | mtspr ibat3u, r14 |
- | |
213 | mtspr ibat3l, r14 |
- | |
214 | - | ||
215 | mtspr dbat0u, r14 |
- | |
216 | mtspr dbat0l, r14 |
- | |
217 | - | ||
218 | mtspr dbat1u, r14 |
- | |
219 | mtspr dbat1l, r14 |
- | |
220 | - | ||
221 | mtspr dbat2u, r14 |
- | |
222 | mtspr dbat2l, r14 |
- | |
223 | - | ||
224 | mtspr dbat3u, r14 |
- | |
225 | mtspr dbat3l, r14 |
- | |
226 | - | ||
227 | blr |
- | |
228 | - | ||
229 | memsetb: |
196 | memsetb: |
230 | rlwimi r5, r5, 8, 16, 23 |
197 | rlwimi r5, r5, 8, 16, 23 |
231 | rlwimi r5, r5, 16, 0, 15 |
198 | rlwimi r5, r5, 16, 0, 15 |
232 | 199 | ||
233 | addi r14, r3, -4 |
200 | addi r14, r3, -4 |
234 | 201 | ||
235 | cmplwi 0, r4, 4 |
202 | cmplwi 0, r4, 4 |
236 | blt 7f |
203 | blt 7f |
237 | 204 | ||
238 | stwu r5, 4(r14) |
205 | stwu r5, 4(r14) |
239 | beqlr |
206 | beqlr |
240 | 207 | ||
241 | andi. r15, r14, 3 |
208 | andi. r15, r14, 3 |
242 | add r4, r15, r4 |
209 | add r4, r15, r4 |
243 | subf r14, r15, r14 |
210 | subf r14, r15, r14 |
244 | srwi r15, r4, 2 |
211 | srwi r15, r4, 2 |
245 | mtctr r15 |
212 | mtctr r15 |
246 | 213 | ||
247 | bdz 6f |
214 | bdz 6f |
248 | 215 | ||
249 | 1: |
216 | 1: |
250 | stwu r5, 4(r14) |
217 | stwu r5, 4(r14) |
251 | bdnz 1b |
218 | bdnz 1b |
252 | 219 | ||
253 | 6: |
220 | 6: |
254 | 221 | ||
255 | andi. r4, r4, 3 |
222 | andi. r4, r4, 3 |
256 | 223 | ||
257 | 7: |
224 | 7: |
258 | 225 | ||
259 | cmpwi 0, r4, 0 |
226 | cmpwi 0, r4, 0 |
260 | beqlr |
227 | beqlr |
261 | 228 | ||
262 | mtctr r4 |
229 | mtctr r4 |
263 | addi r6, r6, 3 |
230 | addi r6, r6, 3 |
264 | 231 | ||
265 | 8: |
232 | 8: |
266 | 233 | ||
267 | stbu r5, 1(r14) |
234 | stbu r5, 1(r14) |
268 | bdnz 8b |
235 | bdnz 8b |
269 | 236 | ||
270 | blr |
237 | blr |
271 | 238 | ||
272 | memcpy: |
239 | memcpy: |
273 | memcpy_from_uspace: |
240 | memcpy_from_uspace: |
274 | memcpy_to_uspace: |
241 | memcpy_to_uspace: |
275 | 242 | ||
276 | srwi. r7, r5, 3 |
243 | srwi. r7, r5, 3 |
277 | addi r6, r3, -4 |
244 | addi r6, r3, -4 |
278 | addi r4, r4, -4 |
245 | addi r4, r4, -4 |
279 | beq 2f |
246 | beq 2f |
280 | 247 | ||
281 | andi. r0, r6, 3 |
248 | andi. r0, r6, 3 |
282 | mtctr r7 |
249 | mtctr r7 |
283 | bne 5f |
250 | bne 5f |
284 | 251 | ||
285 | 1: |
252 | 1: |
286 | 253 | ||
287 | lwz r7, 4(r4) |
254 | lwz r7, 4(r4) |
288 | lwzu r8, 8(r4) |
255 | lwzu r8, 8(r4) |
289 | stw r7, 4(r6) |
256 | stw r7, 4(r6) |
290 | stwu r8, 8(r6) |
257 | stwu r8, 8(r6) |
291 | bdnz 1b |
258 | bdnz 1b |
292 | 259 | ||
293 | andi. r5, r5, 7 |
260 | andi. r5, r5, 7 |
294 | 261 | ||
295 | 2: |
262 | 2: |
296 | 263 | ||
297 | cmplwi 0, r5, 4 |
264 | cmplwi 0, r5, 4 |
298 | blt 3f |
265 | blt 3f |
299 | 266 | ||
300 | lwzu r0, 4(r4) |
267 | lwzu r0, 4(r4) |
301 | addi r5, r5, -4 |
268 | addi r5, r5, -4 |
302 | stwu r0, 4(r6) |
269 | stwu r0, 4(r6) |
303 | 270 | ||
304 | 3: |
271 | 3: |
305 | 272 | ||
306 | cmpwi 0, r5, 0 |
273 | cmpwi 0, r5, 0 |
307 | beqlr |
274 | beqlr |
308 | mtctr r5 |
275 | mtctr r5 |
309 | addi r4, r4, 3 |
276 | addi r4, r4, 3 |
310 | addi r6, r6, 3 |
277 | addi r6, r6, 3 |
311 | 278 | ||
312 | 4: |
279 | 4: |
313 | 280 | ||
314 | lbzu r0, 1(r4) |
281 | lbzu r0, 1(r4) |
315 | stbu r0, 1(r6) |
282 | stbu r0, 1(r6) |
316 | bdnz 4b |
283 | bdnz 4b |
317 | blr |
284 | blr |
318 | 285 | ||
319 | 5: |
286 | 5: |
320 | 287 | ||
321 | subfic r0, r0, 4 |
288 | subfic r0, r0, 4 |
322 | mtctr r0 |
289 | mtctr r0 |
323 | 290 | ||
324 | 6: |
291 | 6: |
325 | 292 | ||
326 | lbz r7, 4(r4) |
293 | lbz r7, 4(r4) |
327 | addi r4, r4, 1 |
294 | addi r4, r4, 1 |
328 | stb r7, 4(r6) |
295 | stb r7, 4(r6) |
329 | addi r6, r6, 1 |
296 | addi r6, r6, 1 |
330 | bdnz 6b |
297 | bdnz 6b |
331 | subf r5, r0, r5 |
298 | subf r5, r0, r5 |
332 | rlwinm. r7, r5, 32-3, 3, 31 |
299 | rlwinm. r7, r5, 32-3, 3, 31 |
333 | beq 2b |
300 | beq 2b |
334 | mtctr r7 |
301 | mtctr r7 |
335 | b 1b |
302 | b 1b |
336 | 303 | ||
337 | memcpy_from_uspace_failover_address: |
304 | memcpy_from_uspace_failover_address: |
338 | memcpy_to_uspace_failover_address: |
305 | memcpy_to_uspace_failover_address: |
339 | b memcpy_from_uspace_failover_address |
306 | b memcpy_from_uspace_failover_address |
340 | 307 |