WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ppc32/include/asm.h


/*
 * Copyright (C) 2005 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ppc32_ASM_H__
#define __ppc32_ASM_H__
 
#include <arch/types.h>
#include <config.h>
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EE.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void)
{
    ipl_t v;
    ipl_t tmp;
   
    asm volatile (
        "mfmsr %0\n"
        "mfmsr %1\n"
        "ori %1, %1, 1 << 15\n"
        "mtmsr %1\n"
        : "=r" (v), "=r" (tmp)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EE.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void)
{
    ipl_t v;
    ipl_t tmp;
   
    asm volatile (
        "mfmsr %0\n"
        "mfmsr %1\n"
        "rlwinm %1, %1, 0, 17, 15\n"
        "mtmsr %1\n"
        : "=r" (v), "=r" (tmp)
    );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EE.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    ipl_t tmp;
   
    asm volatile (
        "mfmsr %1\n"
        "rlwimi  %0, %1, 0, 17, 15\n"
        "cmpw 0, %0, %1\n"
        "beq 0f\n"
        "mtmsr %0\n"
        "0:\n"
        : "=r" (ipl), "=r" (tmp)
        : "0" (ipl)
        : "cr0"
    );
}
 
/** Return interrupt priority level.
 *
 * Return EE.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void)
{
    ipl_t v;
   
    asm volatile (
        "mfmsr %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline __address get_stack_base(void)
{
    __address v;
   
    asm volatile (
        "and %0, %%sp, %1\n"
        : "=r" (v)
        : "r" (~(STACK_SIZE - 1))
    );
    return v;
}
 
static inline void cpu_sleep(void)
{
}
 
void cpu_halt(void);
void asm_delay_loop(__u32 t);
 
 
extern void userspace_asm(__address uspace_uarg, __address stack, __address entry);
 
#endif
 

Rev 1374	Rev 1378
1	/*	1	/*
2	* Copyright (C) 2005 Martin Decky	2	* Copyright (C) 2005 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ppc32_ASM_H__	29	#ifndef __ppc32_ASM_H__
30	#define __ppc32_ASM_H__	30	#define __ppc32_ASM_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <config.h>	33	#include <config.h>
34		34
35	/** Enable interrupts.	35	/** Enable interrupts.
36	*	36	*
37	* Enable interrupts and return previous	37	* Enable interrupts and return previous
38	* value of EE.	38	* value of EE.
39	*	39	*
40	* @return Old interrupt priority level.	40	* @return Old interrupt priority level.
41	*/	41	*/
42	static inline ipl_t interrupts_enable(void)	42	static inline ipl_t interrupts_enable(void)
43	{	43	{
44	ipl_t v;	44	ipl_t v;
45	ipl_t tmp;	45	ipl_t tmp;
46		46
47	asm volatile (	47	asm volatile (
48	"mfmsr %0\n"	48	"mfmsr %0\n"
49	"mfmsr %1\n"	49	"mfmsr %1\n"
50	"ori %1, %1, 1 << 15\n"	50	"ori %1, %1, 1 << 15\n"
51	"mtmsr %1\n"	51	"mtmsr %1\n"
52	: "=r" (v), "=r" (tmp)	52	: "=r" (v), "=r" (tmp)
53	);	53	);
54	return v;	54	return v;
55	}	55	}
56		56
57	/** Disable interrupts.	57	/** Disable interrupts.
58	*	58	*
59	* Disable interrupts and return previous	59	* Disable interrupts and return previous
60	* value of EE.	60	* value of EE.
61	*	61	*
62	* @return Old interrupt priority level.	62	* @return Old interrupt priority level.
63	*/	63	*/
64	static inline ipl_t interrupts_disable(void)	64	static inline ipl_t interrupts_disable(void)
65	{	65	{
66	ipl_t v;	66	ipl_t v;
67	ipl_t tmp;	67	ipl_t tmp;
68		68
69	asm volatile (	69	asm volatile (
70	"mfmsr %0\n"	70	"mfmsr %0\n"
71	"mfmsr %1\n"	71	"mfmsr %1\n"
72	"rlwinm %1, %1, 0, 17, 15\n"	72	"rlwinm %1, %1, 0, 17, 15\n"
73	"mtmsr %1\n"	73	"mtmsr %1\n"
74	: "=r" (v), "=r" (tmp)	74	: "=r" (v), "=r" (tmp)
75	);	75	);
76	return v;	76	return v;
77	}	77	}
78		78
79	/** Restore interrupt priority level.	79	/** Restore interrupt priority level.
80	*	80	*
81	* Restore EE.	81	* Restore EE.
82	*	82	*
83	* @param ipl Saved interrupt priority level.	83	* @param ipl Saved interrupt priority level.
84	*/	84	*/
85	static inline void interrupts_restore(ipl_t ipl)	85	static inline void interrupts_restore(ipl_t ipl)
86	{	86	{
87	ipl_t tmp;	87	ipl_t tmp;
88		88
89	asm volatile (	89	asm volatile (
90	"mfmsr %1\n"	90	"mfmsr %1\n"
91	"rlwimi %0, %1, 0, 17, 15\n"	91	"rlwimi %0, %1, 0, 17, 15\n"
92	"cmpw 0, %0, %1\n"	92	"cmpw 0, %0, %1\n"
93	"beq 0f\n"	93	"beq 0f\n"
94	"mtmsr %0\n"	94	"mtmsr %0\n"
95	"0:\n"	95	"0:\n"
96	: "=r" (ipl), "=r" (tmp)	96	: "=r" (ipl), "=r" (tmp)
97	: "0" (ipl)	97	: "0" (ipl)
98	: "cr0"	98	: "cr0"
99	);	99	);
100	}	100	}
101		101
102	/** Return interrupt priority level.	102	/** Return interrupt priority level.
103	*	103	*
104	* Return EE.	104	* Return EE.
105	*	105	*
106	* @return Current interrupt priority level.	106	* @return Current interrupt priority level.
107	*/	107	*/
108	static inline ipl_t interrupts_read(void)	108	static inline ipl_t interrupts_read(void)
109	{	109	{
110	ipl_t v;	110	ipl_t v;
111		111
112	asm volatile (	112	asm volatile (
113	"mfmsr %0\n"	113	"mfmsr %0\n"
114	: "=r" (v)	114	: "=r" (v)
115	);	115	);
116	return v;	116	return v;
117	}	117	}
118		118
119	/** Return base address of current stack.	119	/** Return base address of current stack.
120	*	120	*
121	* Return the base address of the current stack.	121	* Return the base address of the current stack.
122	* The stack is assumed to be STACK_SIZE bytes long.	122	* The stack is assumed to be STACK_SIZE bytes long.
123	* The stack must start on page boundary.	123	* The stack must start on page boundary.
124	*/	124	*/
125	static inline __address get_stack_base(void)	125	static inline __address get_stack_base(void)
126	{	126	{
127	__address v;	127	__address v;
128		128
129	asm volatile (	129	asm volatile (
130	"and %0, %%sp, %1\n"	130	"and %0, %%sp, %1\n"
131	: "=r" (v)	131	: "=r" (v)
132	: "r" (~(STACK_SIZE - 1))	132	: "r" (~(STACK_SIZE - 1))
133	);	133	);
134	return v;	134	return v;
135	}	135	}
136		136
137	static inline void cpu_sleep(void)	137	static inline void cpu_sleep(void)
138	{	138	{
139	}	139	}
140		140
141	void cpu_halt(void);	141	void cpu_halt(void);
142	void asm_delay_loop(__u32 t);	142	void asm_delay_loop(__u32 t);
143	void invalidate_bat(void);	-
144		143
145	extern void userspace_asm(__address uspace_uarg, __address stack, __address entry);	144	extern void userspace_asm(__address uspace_uarg, __address stack, __address entry);
146		145
147	#endif	146	#endif
148		147

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ppc32/include/asm.h – Rev 1374 → 1378