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1 | # |
1 | # |
2 | # Copyright (C) 2003-2004 Jakub Jermar |
2 | # Copyright (C) 2003-2004 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
30 | #include <arch/mm/page.h> |
30 | #include <arch/mm/page.h> |
31 | #include <arch/asm/boot.h> |
31 | #include <arch/asm/boot.h> |
32 | #include <arch/context_offset.h> |
32 | #include <arch/context_offset.h> |
33 | 33 | ||
34 | .text |
34 | .text |
35 | 35 | ||
36 | .set noat |
36 | .set noat |
37 | .set noreorder |
37 | .set noreorder |
38 | .set nomacro |
38 | .set nomacro |
39 | 39 | ||
40 | .global kernel_image_start |
40 | .global kernel_image_start |
41 | .global tlb_refill_entry |
41 | .global tlb_refill_entry |
42 | .global cache_error_entry |
42 | .global cache_error_entry |
43 | .global exception_entry |
43 | .global exception_entry |
44 | .global userspace_asm |
44 | .global userspace_asm |
45 | 45 | ||
46 | # Which status bits should are thread-local |
46 | # Which status bits should are thread-local |
47 | #define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE |
47 | #define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE |
48 | 48 | ||
49 | # Save registers to space defined by \r |
49 | # Save registers to space defined by \r |
50 | # We will change status: Disable ERL,EXL,UM,IE |
50 | # We will change status: Disable ERL,EXL,UM,IE |
51 | # These changes will be automatically reversed in REGISTER_LOAD |
51 | # These changes will be automatically reversed in REGISTER_LOAD |
- | 52 | # SP is NOT saved as part of these registers |
|
52 | .macro REGISTERS_STORE_AND_EXC_RESET r |
53 | .macro REGISTERS_STORE_AND_EXC_RESET r |
53 | sw $at,EOFFSET_AT(\r) |
54 | sw $at,EOFFSET_AT(\r) |
54 | sw $v0,EOFFSET_V0(\r) |
55 | sw $v0,EOFFSET_V0(\r) |
55 | sw $v1,EOFFSET_V1(\r) |
56 | sw $v1,EOFFSET_V1(\r) |
56 | sw $a0,EOFFSET_A0(\r) |
57 | sw $a0,EOFFSET_A0(\r) |
57 | sw $a1,EOFFSET_A1(\r) |
58 | sw $a1,EOFFSET_A1(\r) |
58 | sw $a2,EOFFSET_A2(\r) |
59 | sw $a2,EOFFSET_A2(\r) |
59 | sw $a3,EOFFSET_A3(\r) |
60 | sw $a3,EOFFSET_A3(\r) |
60 | sw $t0,EOFFSET_T0(\r) |
61 | sw $t0,EOFFSET_T0(\r) |
61 | sw $t1,EOFFSET_T1(\r) |
62 | sw $t1,EOFFSET_T1(\r) |
62 | sw $t2,EOFFSET_T2(\r) |
63 | sw $t2,EOFFSET_T2(\r) |
63 | sw $t3,EOFFSET_T3(\r) |
64 | sw $t3,EOFFSET_T3(\r) |
64 | sw $t4,EOFFSET_T4(\r) |
65 | sw $t4,EOFFSET_T4(\r) |
65 | sw $t5,EOFFSET_T5(\r) |
66 | sw $t5,EOFFSET_T5(\r) |
66 | sw $t6,EOFFSET_T6(\r) |
67 | sw $t6,EOFFSET_T6(\r) |
67 | sw $t7,EOFFSET_T7(\r) |
68 | sw $t7,EOFFSET_T7(\r) |
68 | sw $t8,EOFFSET_T8(\r) |
69 | sw $t8,EOFFSET_T8(\r) |
69 | sw $t9,EOFFSET_T9(\r) |
70 | sw $t9,EOFFSET_T9(\r) |
70 | 71 | ||
71 | mflo $at |
72 | mflo $at |
72 | sw $at, EOFFSET_LO(\r) |
73 | sw $at, EOFFSET_LO(\r) |
73 | mfhi $at |
74 | mfhi $at |
74 | sw $at, EOFFSET_HI(\r) |
75 | sw $at, EOFFSET_HI(\r) |
75 | 76 | ||
76 | #ifdef CONFIG_DEBUG_ALLREGS |
77 | #ifdef CONFIG_DEBUG_ALLREGS |
77 | sw $s0,EOFFSET_S0(\r) |
78 | sw $s0,EOFFSET_S0(\r) |
78 | sw $s1,EOFFSET_S1(\r) |
79 | sw $s1,EOFFSET_S1(\r) |
79 | sw $s2,EOFFSET_S2(\r) |
80 | sw $s2,EOFFSET_S2(\r) |
80 | sw $s3,EOFFSET_S3(\r) |
81 | sw $s3,EOFFSET_S3(\r) |
81 | sw $s4,EOFFSET_S4(\r) |
82 | sw $s4,EOFFSET_S4(\r) |
82 | sw $s5,EOFFSET_S5(\r) |
83 | sw $s5,EOFFSET_S5(\r) |
83 | sw $s6,EOFFSET_S6(\r) |
84 | sw $s6,EOFFSET_S6(\r) |
84 | sw $s7,EOFFSET_S7(\r) |
85 | sw $s7,EOFFSET_S7(\r) |
85 | sw $s8,EOFFSET_S8(\r) |
86 | sw $s8,EOFFSET_S8(\r) |
86 | #endif |
87 | #endif |
87 | 88 | ||
88 | sw $gp,EOFFSET_GP(\r) |
89 | sw $gp,EOFFSET_GP(\r) |
89 | sw $ra,EOFFSET_RA(\r) |
90 | sw $ra,EOFFSET_RA(\r) |
90 | sw $sp,EOFFSET_SP(\r) |
91 | sw $k1,EOFFSET_K1(\r) |
91 | 92 | ||
92 | mfc0 $t0, $status |
93 | mfc0 $t0, $status |
93 | mfc0 $t1, $epc |
94 | mfc0 $t1, $epc |
94 | 95 | ||
95 | and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE |
96 | and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE |
96 | li $t3, ~(0x1f) |
97 | li $t3, ~(0x1f) |
97 | and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE |
98 | and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE |
98 | 99 | ||
99 | sw $t2,EOFFSET_STATUS(\r) |
100 | sw $t2,EOFFSET_STATUS(\r) |
100 | sw $t1,EOFFSET_EPC(\r) |
101 | sw $t1,EOFFSET_EPC(\r) |
101 | mtc0 $t0, $status |
102 | mtc0 $t0, $status |
102 | .endm |
103 | .endm |
103 | 104 | ||
104 | .macro REGISTERS_LOAD r |
105 | .macro REGISTERS_LOAD r |
105 | # Update only UM,EXR,IE from status, the rest |
106 | # Update only UM,EXR,IE from status, the rest |
106 | # is controlled by OS and not bound to task |
107 | # is controlled by OS and not bound to task |
107 | mfc0 $t0, $status |
108 | mfc0 $t0, $status |
108 | lw $t1,EOFFSET_STATUS(\r) |
109 | lw $t1,EOFFSET_STATUS(\r) |
109 | 110 | ||
110 | li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE |
111 | li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE |
111 | and $t0, $t0, $t2 |
112 | and $t0, $t0, $t2 |
112 | 113 | ||
113 | or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status |
114 | or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status |
114 | mtc0 $t0, $status |
115 | mtc0 $t0, $status |
115 | 116 | ||
116 | lw $v0,EOFFSET_V0(\r) |
117 | lw $v0,EOFFSET_V0(\r) |
117 | lw $v1,EOFFSET_V1(\r) |
118 | lw $v1,EOFFSET_V1(\r) |
118 | lw $a0,EOFFSET_A0(\r) |
119 | lw $a0,EOFFSET_A0(\r) |
119 | lw $a1,EOFFSET_A1(\r) |
120 | lw $a1,EOFFSET_A1(\r) |
120 | lw $a2,EOFFSET_A2(\r) |
121 | lw $a2,EOFFSET_A2(\r) |
121 | lw $a3,EOFFSET_A3(\r) |
122 | lw $a3,EOFFSET_A3(\r) |
122 | lw $t0,EOFFSET_T0(\r) |
123 | lw $t0,EOFFSET_T0(\r) |
123 | lw $t1,EOFFSET_T1(\r) |
124 | lw $t1,EOFFSET_T1(\r) |
124 | lw $t2,EOFFSET_T2(\r) |
125 | lw $t2,EOFFSET_T2(\r) |
125 | lw $t3,EOFFSET_T3(\r) |
126 | lw $t3,EOFFSET_T3(\r) |
126 | lw $t4,EOFFSET_T4(\r) |
127 | lw $t4,EOFFSET_T4(\r) |
127 | lw $t5,EOFFSET_T5(\r) |
128 | lw $t5,EOFFSET_T5(\r) |
128 | lw $t6,EOFFSET_T6(\r) |
129 | lw $t6,EOFFSET_T6(\r) |
129 | lw $t7,EOFFSET_T7(\r) |
130 | lw $t7,EOFFSET_T7(\r) |
130 | lw $t8,EOFFSET_T8(\r) |
131 | lw $t8,EOFFSET_T8(\r) |
131 | lw $t9,EOFFSET_T9(\r) |
132 | lw $t9,EOFFSET_T9(\r) |
132 | 133 | ||
133 | #ifdef CONFIG_DEBUG_ALLREGS |
134 | #ifdef CONFIG_DEBUG_ALLREGS |
134 | lw $s0,EOFFSET_S0(\r) |
135 | lw $s0,EOFFSET_S0(\r) |
135 | lw $s1,EOFFSET_S1(\r) |
136 | lw $s1,EOFFSET_S1(\r) |
136 | lw $s2,EOFFSET_S2(\r) |
137 | lw $s2,EOFFSET_S2(\r) |
137 | lw $s3,EOFFSET_S3(\r) |
138 | lw $s3,EOFFSET_S3(\r) |
138 | lw $s4,EOFFSET_S4(\r) |
139 | lw $s4,EOFFSET_S4(\r) |
139 | lw $s5,EOFFSET_S5(\r) |
140 | lw $s5,EOFFSET_S5(\r) |
140 | lw $s6,EOFFSET_S6(\r) |
141 | lw $s6,EOFFSET_S6(\r) |
141 | lw $s7,EOFFSET_S7(\r) |
142 | lw $s7,EOFFSET_S7(\r) |
142 | lw $s8,EOFFSET_S8(\r) |
143 | lw $s8,EOFFSET_S8(\r) |
143 | #endif |
144 | #endif |
144 | lw $gp,EOFFSET_GP(\r) |
145 | lw $gp,EOFFSET_GP(\r) |
145 | lw $ra,EOFFSET_RA(\r) |
146 | lw $ra,EOFFSET_RA(\r) |
- | 147 | lw $k1,EOFFSET_K1(\r) |
|
146 | 148 | ||
147 | lw $at,EOFFSET_LO(\r) |
149 | lw $at,EOFFSET_LO(\r) |
148 | mtlo $at |
150 | mtlo $at |
149 | lw $at,EOFFSET_HI(\r) |
151 | lw $at,EOFFSET_HI(\r) |
150 | mthi $at |
152 | mthi $at |
151 | 153 | ||
152 | lw $at,EOFFSET_EPC(\r) |
154 | lw $at,EOFFSET_EPC(\r) |
153 | mtc0 $at, $epc |
155 | mtc0 $at, $epc |
154 | 156 | ||
155 | lw $at,EOFFSET_AT(\r) |
157 | lw $at,EOFFSET_AT(\r) |
156 | lw $sp,EOFFSET_SP(\r) |
158 | lw $sp,EOFFSET_SP(\r) |
157 | .endm |
159 | .endm |
158 | 160 | ||
159 | # Move kernel stack pointer address to register K0 |
161 | # Move kernel stack pointer address to register K0 |
160 | # - if we are in user mode, load the appropriate stack |
162 | # - if we are in user mode, load the appropriate stack |
161 | # address |
163 | # address |
162 | .macro KERNEL_STACK_TO_K0 |
164 | .macro KERNEL_STACK_TO_K0 |
163 | # If we are in user mode |
165 | # If we are in user mode |
164 | mfc0 $k0, $status |
166 | mfc0 $k0, $status |
165 | andi $k0, 0x10 |
167 | andi $k0, 0x10 |
166 | 168 | ||
167 | beq $k0, $0, 1f |
169 | beq $k0, $0, 1f |
168 | add $k0, $sp, 0 |
170 | add $k0, $sp, 0 |
169 | 171 | ||
170 | # Move $k0 pointer to kernel stack |
172 | # Move $k0 pointer to kernel stack |
171 | lui $k0, %hi(supervisor_sp) |
173 | lui $k0, %hi(supervisor_sp) |
172 | ori $k0, $k0, %lo(supervisor_sp) |
174 | ori $k0, $k0, %lo(supervisor_sp) |
173 | # Move $k0 (superveisor_sp) |
175 | # Move $k0 (superveisor_sp) |
174 | lw $k0, 0($k0) |
176 | lw $k0, 0($k0) |
175 | 1: |
177 | 1: |
176 | .endm |
178 | .endm |
177 | 179 | ||
178 | .org 0x0 |
180 | .org 0x0 |
179 | kernel_image_start: |
181 | kernel_image_start: |
180 | /* Load temporary stack */ |
182 | /* Load temporary stack */ |
181 | lui $sp, %hi(end_stack) |
183 | lui $sp, %hi(end_stack) |
182 | ori $sp, $sp, %lo(end_stack) |
184 | ori $sp, $sp, %lo(end_stack) |
183 | 185 | ||
184 | /* Not sure about this, but might be needed for PIC code???? */ |
186 | /* Not sure about this, but might be needed for PIC code???? */ |
185 | lui $gp, 0x8000 |
187 | lui $gp, 0x8000 |
186 | 188 | ||
187 | jal main_bsp |
189 | jal main_bsp |
188 | nop |
190 | nop |
189 | 191 | ||
190 | 192 | ||
191 | .space TEMP_STACK_SIZE |
193 | .space TEMP_STACK_SIZE |
192 | end_stack: |
194 | end_stack: |
193 | 195 | ||
194 | tlb_refill_entry: |
196 | tlb_refill_entry: |
195 | j tlb_refill_handler |
197 | j tlb_refill_handler |
196 | nop |
198 | nop |
197 | 199 | ||
198 | cache_error_entry: |
200 | cache_error_entry: |
199 | j cache_error_handler |
201 | j cache_error_handler |
200 | nop |
202 | nop |
201 | 203 | ||
202 | exception_entry: |
204 | exception_entry: |
203 | j exception_handler |
205 | j exception_handler |
204 | nop |
206 | nop |
205 | 207 | ||
206 | 208 | ||
207 | 209 | ||
208 | exception_handler: |
210 | exception_handler: |
209 | KERNEL_STACK_TO_K0 |
211 | KERNEL_STACK_TO_K0 |
210 | - | ||
211 | mfc0 $k1, $cause |
- | |
212 | sub $k0, REGISTER_SPACE |
212 | sub $k0, REGISTER_SPACE |
- | 213 | sw $sp,EOFFSET_SP($k0) |
|
- | 214 | move $sp, $k0 |
|
213 | 215 | ||
214 | sra $k1, $k1, 0x2 # cp0_exc_cause() part 1 |
- | |
215 | andi $k1, $k1, 0x1f # cp0_exc_cause() part 2 |
216 | mfc0 $k0, $cause |
216 | sub $k1, 8 # 8=SYSCALL |
- | |
217 | 217 | ||
218 | beqz $k1, syscall_shortcut |
218 | sra $k0, $k0, 0x2 # cp0_exc_cause() part 1 |
219 | add $k1, 8 # Revert $k1 back to correct exc number |
219 | andi $k0, $k0, 0x1f # cp0_exc_cause() part 2 |
- | 220 | sub $k0, 8 # 8=SYSCALL |
|
220 | 221 | ||
- | 222 | beqz $k0, syscall_shortcut |
|
- | 223 | add $k0, 8 # Revert $k1 back to correct exc number |
|
- | 224 | ||
221 | REGISTERS_STORE_AND_EXC_RESET $k0 |
225 | REGISTERS_STORE_AND_EXC_RESET $sp |
222 | move $sp, $k0 |
- | |
223 | 226 | ||
224 | move $a1, $sp |
227 | move $a1, $sp |
225 | jal exc_dispatch # exc_dispatch(excno, register_space) |
228 | jal exc_dispatch # exc_dispatch(excno, register_space) |
226 | move $a0, $k1 |
229 | move $a0, $k0 |
227 | 230 | ||
228 | REGISTERS_LOAD $sp |
231 | REGISTERS_LOAD $sp |
229 | # The $sp is automatically restored to former value |
232 | # The $sp is automatically restored to former value |
230 | eret |
233 | eret |
231 | 234 | ||
232 | # it seems that mips reserves some space on stack for varfuncs??? |
235 | # it seems that mips reserves some space on stack for varfuncs??? |
233 | #define SS_ARG4 16 |
236 | #define SS_ARG4 16 |
234 | #define SS_SP 20 |
237 | #define SS_SP EOFFSET_SP |
235 | #define SS_STATUS 24 |
238 | #define SS_STATUS EOFFSET_STATUS |
236 | #define SS_EPC 28 |
239 | #define SS_EPC EOFFSET_EPC |
237 | syscall_shortcut: |
240 | syscall_shortcut: |
238 | # We have a lot of space on the stack, with free use |
241 | # We have a lot of space on the stack, with free use |
239 | sw $sp, SS_SP($k0) |
- | |
240 | move $sp, $k0 |
- | |
241 | - | ||
242 | mfc0 $t1, $epc |
242 | mfc0 $t1, $epc |
243 | mfc0 $t0, $status |
243 | mfc0 $t0, $status |
244 | sw $t1,SS_EPC($sp) # Save EPC |
244 | sw $t1,SS_EPC($sp) # Save EPC |
245 | 245 | ||
246 | and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE |
246 | and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE |
247 | li $t3, ~(0x1f) |
247 | li $t3, ~(0x1f) |
248 | and $t0, $t0, $t3 # Clear KSU,EXL,ERL |
248 | and $t0, $t0, $t3 # Clear KSU,EXL,ERL |
249 | ori $t0, $t0, 0x1 # Set IE |
249 | ori $t0, $t0, 0x1 # Set IE |
250 | 250 | ||
251 | sw $t2,SS_STATUS($sp) |
251 | sw $t2,SS_STATUS($sp) |
252 | mtc0 $t0, $status |
252 | mtc0 $t0, $status |
253 | 253 | ||
254 | jal syscall_handler |
254 | jal syscall_handler |
255 | sw $v0, SS_ARG4($sp) # save v0 - arg4 to stack |
255 | sw $v0, SS_ARG4($sp) # save v0 - arg4 to stack |
256 | 256 | ||
257 | # restore epc+4 |
257 | # restore epc+4 |
258 | lw $t0,SS_EPC($sp) |
258 | lw $t0,SS_EPC($sp) |
259 | addi $t0, $t0, 4 |
259 | addi $t0, $t0, 4 |
260 | mtc0 $t0, $epc |
260 | mtc0 $t0, $epc |
261 | 261 | ||
262 | # restore status |
262 | # restore status |
263 | mfc0 $t0, $status |
263 | mfc0 $t0, $status |
264 | lw $t1,SS_STATUS($sp) |
264 | lw $t1,SS_STATUS($sp) |
265 | 265 | ||
266 | li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE |
266 | li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE |
267 | and $t0, $t0, $t2 |
267 | and $t0, $t0, $t2 |
268 | or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status |
268 | or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status |
269 | mtc0 $t0, $status |
269 | mtc0 $t0, $status |
270 | 270 | ||
271 | lw $sp,SS_SP($sp) # restore sp |
271 | lw $sp,SS_SP($sp) # restore sp |
272 | 272 | ||
273 | eret |
273 | eret |
274 | 274 | ||
275 | tlb_refill_handler: |
275 | tlb_refill_handler: |
276 | KERNEL_STACK_TO_K0 |
276 | KERNEL_STACK_TO_K0 |
277 | sub $k0, REGISTER_SPACE |
277 | sub $k0, REGISTER_SPACE |
278 | REGISTERS_STORE_AND_EXC_RESET $k0 |
278 | REGISTERS_STORE_AND_EXC_RESET $k0 |
- | 279 | sw $sp,EOFFSET_SP($k0) |
|
279 | add $sp, $k0, 0 |
280 | add $sp, $k0, 0 |
280 | 281 | ||
281 | add $a0, $sp, 0 |
282 | add $a0, $sp, 0 |
282 | jal tlb_refill /* tlb_refill(register_space) */ |
283 | jal tlb_refill /* tlb_refill(register_space) */ |
283 | nop |
284 | nop |
284 | 285 | ||
285 | REGISTERS_LOAD $sp |
286 | REGISTERS_LOAD $sp |
286 | 287 | ||
287 | eret |
288 | eret |
288 | 289 | ||
289 | cache_error_handler: |
290 | cache_error_handler: |
290 | KERNEL_STACK_TO_K0 |
291 | KERNEL_STACK_TO_K0 |
291 | sub $sp, REGISTER_SPACE |
292 | sub $k0, REGISTER_SPACE |
292 | REGISTERS_STORE_AND_EXC_RESET $sp |
293 | REGISTERS_STORE_AND_EXC_RESET $k0 |
- | 294 | sw $sp,EOFFSET_SP($k0) |
|
293 | add $sp, $k0, 0 |
295 | add $sp, $k0, 0 |
294 | 296 | ||
295 | jal cache_error |
297 | jal cache_error |
296 | nop |
298 | nop |
297 | 299 | ||
298 | REGISTERS_LOAD $sp |
300 | REGISTERS_LOAD $sp |
299 | 301 | ||
300 | eret |
302 | eret |
301 | 303 | ||
302 | userspace_asm: |
304 | userspace_asm: |
303 | add $sp, $a0, 0 |
305 | add $sp, $a0, 0 |
304 | add $v0, $a1, 0 |
306 | add $v0, $a1, 0 |
305 | eret |
307 | eret |
306 | 308 | ||
307 | 309 |