WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/start.S


#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
#include <arch/mm/page.h>
#include <arch/asm/boot.h>
#include <arch/context_offset.h>
	
.text
 
.set noat
.set noreorder
.set nomacro
 
.global kernel_image_start
.global tlb_refill_entry
.global cache_error_entry
.global exception_entry
.global userspace_asm
 
# Which status bits should are thread-local
#define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE
	
# Save registers to space defined by \r
# We will change status: Disable ERL,EXL,UM,IE
# These changes will be automatically reversed in REGISTER_LOAD
.macro REGISTERS_STORE_AND_EXC_RESET r
	sw $at,EOFFSET_AT(\r)
	sw $v0,EOFFSET_V0(\r)
	sw $v1,EOFFSET_V1(\r)
	sw $a0,EOFFSET_A0(\r)
	sw $a1,EOFFSET_A1(\r)
	sw $a2,EOFFSET_A2(\r)
	sw $a3,EOFFSET_A3(\r)
	sw $t0,EOFFSET_T0(\r)
	sw $t1,EOFFSET_T1(\r)
	sw $t2,EOFFSET_T2(\r)
	sw $t3,EOFFSET_T3(\r)
	sw $t4,EOFFSET_T4(\r)
	sw $t5,EOFFSET_T5(\r)
	sw $t6,EOFFSET_T6(\r)
	sw $t7,EOFFSET_T7(\r)
	sw $t8,EOFFSET_T8(\r)
	sw $t9,EOFFSET_T9(\r)
 
	mflo $at
	sw $at, EOFFSET_LO(\r)
	mfhi $at
	sw $at, EOFFSET_HI(\r)
	
#ifdef CONFIG_DEBUG_ALLREGS	
	sw $s0,EOFFSET_S0(\r)
	sw $s1,EOFFSET_S1(\r)
	sw $s2,EOFFSET_S2(\r)
	sw $s3,EOFFSET_S3(\r)
	sw $s4,EOFFSET_S4(\r)
	sw $s5,EOFFSET_S5(\r)
	sw $s6,EOFFSET_S6(\r)
	sw $s7,EOFFSET_S7(\r)
	sw $s8,EOFFSET_S8(\r)
#endif
	
	sw $gp,EOFFSET_GP(\r)
	sw $ra,EOFFSET_RA(\r)
	sw $sp,EOFFSET_SP(\r)
 
	mfc0 $t0, $status
	mfc0 $t1, $epc
	
	and $t2, $t0, REG_SAVE_MASK  # Save only KSU,EXL,ERL,IE
	li $t3, ~(0x1f)
	and $t0, $t0, $t3           # Clear KSU,EXL,ERL,IE
	
	sw $t2,EOFFSET_STATUS(\r)
	sw $t1,EOFFSET_EPC(\r)
	mtc0 $t0, $status
.endm
 
.macro REGISTERS_LOAD r
	# Update only UM,EXR,IE from status, the rest
	# is controlled by OS and not bound to task
	mfc0 $t0, $status
	lw $t1,EOFFSET_STATUS(\r)
 
	li $t2, ~REG_SAVE_MASK    # Mask UM,EXL,ERL,IE
	and $t0, $t0, $t2
	
	or $t0, $t0, $t1   # Copy UM,EXL,ERL,IE from saved status
	mtc0 $t0, $status
	
	lw $v0,EOFFSET_V0(\r)
	lw $v1,EOFFSET_V1(\r)
	lw $a0,EOFFSET_A0(\r)
	lw $a1,EOFFSET_A1(\r)
	lw $a2,EOFFSET_A2(\r)
	lw $a3,EOFFSET_A3(\r)
	lw $t0,EOFFSET_T0(\r)
	lw $t1,EOFFSET_T1(\r)
	lw $t2,EOFFSET_T2(\r)
	lw $t3,EOFFSET_T3(\r)
	lw $t4,EOFFSET_T4(\r)
	lw $t5,EOFFSET_T5(\r)
	lw $t6,EOFFSET_T6(\r)
	lw $t7,EOFFSET_T7(\r)
	lw $t8,EOFFSET_T8(\r)
	lw $t9,EOFFSET_T9(\r)
	
#ifdef CONFIG_DEBUG_ALLREGS	
	lw $s0,EOFFSET_S0(\r)
	lw $s1,EOFFSET_S1(\r)
	lw $s2,EOFFSET_S2(\r)
	lw $s3,EOFFSET_S3(\r)
	lw $s4,EOFFSET_S4(\r)
	lw $s5,EOFFSET_S5(\r)
	lw $s6,EOFFSET_S6(\r)
	lw $s7,EOFFSET_S7(\r)
	lw $s8,EOFFSET_S8(\r)
#endif
	lw $gp,EOFFSET_GP(\r)
	lw $ra,EOFFSET_RA(\r)
	
	lw $at,EOFFSET_LO(\r)
	mtlo $at
	lw $at,EOFFSET_HI(\r)
	mthi $at
 
	lw $at,EOFFSET_EPC(\r)
	mtc0 $at, $epc
	
	lw $at,EOFFSET_AT(\r)
	lw $sp,EOFFSET_SP(\r)
.endm
 
# Move kernel stack pointer address to register K0
# - if we are in user mode, load the appropriate stack
# address
.macro KERNEL_STACK_TO_K0
	# If we are in user mode
	mfc0 $k0, $status
	andi $k0, 0x10
	
	beq $k0, $0, 1f
	add $k0, $sp, 0
	
	# Move $k0 pointer to kernel stack
	lui $k0, %hi(supervisor_sp)
	ori $k0, $k0, %lo(supervisor_sp)
	# Move $k0 (superveisor_sp)
	lw $k0, 0($k0)
1:		
.endm
		
.org 0x0
kernel_image_start:
	/* Load temporary stack */
	lui $sp, %hi(end_stack)
	ori $sp, $sp, %lo(end_stack)
 
	/* Not sure about this, but might be needed for PIC code???? */
	lui $gp, 0x8000
	
	jal main_bsp
	nop
 
 
	.space TEMP_STACK_SIZE
end_stack:
 
tlb_refill_entry:
	j tlb_refill_handler
	nop
 
cache_error_entry:
	j cache_error_handler
	nop
 
exception_entry:
	j exception_handler
	nop	
 
	
	
exception_handler:
	KERNEL_STACK_TO_K0
	
	mfc0 $k1, $cause
	sub $k0, REGISTER_SPACE
	
	sra $k1, $k1, 0x2     # cp0_exc_cause() part 1
	andi $k1, $k1, 0x1f   # cp0_exc_cause() part 2
	sub $k1, 8            # 8=SYSCALL
	
	beqz $k1, uspace_shortcut
	add $k1, 8            # Revert $k1 back to correct exc number
	
	REGISTERS_STORE_AND_EXC_RESET $k0
	move $sp, $k0
	
	move $a1, $sp
	jal exc_dispatch      # exc_dispatch(excno, register_space)
	move $a0, $k1
 
	REGISTERS_LOAD $sp
	# The $sp is automatically restored to former value
	eret
	nop
 
# it seems that mips reserves some space on stack for varfuncs???
#define SS_ARG4   16
#define SS_SP     20
#define SS_STATUS 24
#define SS_EPC    28
 
uspace_shortcut:
	# We have a lot of space on the stack, with free use
	sw $sp, SS_SP($k0)
	move $sp, $k0
 
 
	mfc0 $t1, $epc
	mfc0 $t0, $status
	sw $t1,SS_EPC($sp)  # Save EPC
	
	and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE
	li $t3, ~(0x1f)
	and $t0, $t0, $t3           # Clear KSU,EXL,ERL
	ori $t0, $t0, 0x1           # Set IE
 
	sw $t2,SS_STATUS($sp)
	mtc0 $t0, $status
 
	jal syscall_handler
	sw $v0, SS_ARG4($sp)        # save v0 - arg4 to stack
 
 
 
 
	# restore epc+4
	lw $t0,SS_EPC($sp)
	addi $t0, $t0, 4
	mtc0 $t0, $epc
	
	# restore status
	mfc0 $t0, $status
	lw $t1,SS_STATUS($sp)
 
	li $t2, ~REG_SAVE_MASK      # Mask UM,EXL,ERL,IE
	and $t0, $t0, $t2
	or $t0, $t0, $t1            # Copy UM,EXL,ERL,IE from saved status
	mtc0 $t0, $status
			
	lw $sp,SS_SP($sp) # restore sp
	
	eret
	
tlb_refill_handler:
	KERNEL_STACK_TO_K0
	sub $k0, REGISTER_SPACE
	REGISTERS_STORE_AND_EXC_RESET $k0
	add $sp, $k0, 0
 
	add $a0, $sp, 0 
	jal tlb_refill /* tlb_refill(register_space) */
	nop
 
	REGISTERS_LOAD $sp
 
	eret
 
cache_error_handler:
	KERNEL_STACK_TO_K0
	sub $sp, REGISTER_SPACE
	REGISTERS_STORE_AND_EXC_RESET $sp
	add $sp, $k0, 0
 
	jal cache_error
	nop
 
	REGISTERS_LOAD $sp
 
	eret
 
userspace_asm:
	add $sp, $a0, 0
	add $v0, $a1, 0
	eret
 
 

Rev 1096	Rev 1097
1	#	1	#
2	# Copyright (C) 2003-2004 Jakub Jermar	2	# Copyright (C) 2003-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30	#include <arch/mm/page.h>	30	#include <arch/mm/page.h>
31	#include <arch/asm/boot.h>	31	#include <arch/asm/boot.h>
32	#include <arch/context_offset.h>	32	#include <arch/context_offset.h>
33		33
34	.text	34	.text
35		35
36	.set noat	36	.set noat
37	.set noreorder	37	.set noreorder
38	.set nomacro	38	.set nomacro
39		39
40	.global kernel_image_start	40	.global kernel_image_start
41	.global tlb_refill_entry	41	.global tlb_refill_entry
42	.global cache_error_entry	42	.global cache_error_entry
43	.global exception_entry	43	.global exception_entry
44	.global userspace_asm	44	.global userspace_asm
45		45
46	# Which status bits should are thread-local	46	# Which status bits should are thread-local
47	#define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE	47	#define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE
48		48
49	# Save registers to space defined by \r	49	# Save registers to space defined by \r
50	# We will change status: Disable ERL,EXL,UM,IE	50	# We will change status: Disable ERL,EXL,UM,IE
51	# These changes will be automatically reversed in REGISTER_LOAD	51	# These changes will be automatically reversed in REGISTER_LOAD
52	.macro REGISTERS_STORE_AND_EXC_RESET r	52	.macro REGISTERS_STORE_AND_EXC_RESET r
53	sw $at,EOFFSET_AT(\r)	53	sw $at,EOFFSET_AT(\r)
54	sw $v0,EOFFSET_V0(\r)	54	sw $v0,EOFFSET_V0(\r)
55	sw $v1,EOFFSET_V1(\r)	55	sw $v1,EOFFSET_V1(\r)
56	sw $a0,EOFFSET_A0(\r)	56	sw $a0,EOFFSET_A0(\r)
57	sw $a1,EOFFSET_A1(\r)	57	sw $a1,EOFFSET_A1(\r)
58	sw $a2,EOFFSET_A2(\r)	58	sw $a2,EOFFSET_A2(\r)
59	sw $a3,EOFFSET_A3(\r)	59	sw $a3,EOFFSET_A3(\r)
60	sw $t0,EOFFSET_T0(\r)	60	sw $t0,EOFFSET_T0(\r)
61	sw $t1,EOFFSET_T1(\r)	61	sw $t1,EOFFSET_T1(\r)
62	sw $t2,EOFFSET_T2(\r)	62	sw $t2,EOFFSET_T2(\r)
63	sw $t3,EOFFSET_T3(\r)	63	sw $t3,EOFFSET_T3(\r)
64	sw $t4,EOFFSET_T4(\r)	64	sw $t4,EOFFSET_T4(\r)
65	sw $t5,EOFFSET_T5(\r)	65	sw $t5,EOFFSET_T5(\r)
66	sw $t6,EOFFSET_T6(\r)	66	sw $t6,EOFFSET_T6(\r)
67	sw $t7,EOFFSET_T7(\r)	67	sw $t7,EOFFSET_T7(\r)
68	sw $t8,EOFFSET_T8(\r)	68	sw $t8,EOFFSET_T8(\r)
69	sw $t9,EOFFSET_T9(\r)	69	sw $t9,EOFFSET_T9(\r)
70		70
71	mflo $at	71	mflo $at
72	sw $at, EOFFSET_LO(\r)	72	sw $at, EOFFSET_LO(\r)
73	mfhi $at	73	mfhi $at
74	sw $at, EOFFSET_HI(\r)	74	sw $at, EOFFSET_HI(\r)
75		75
76	#ifdef CONFIG_DEBUG_ALLREGS	76	#ifdef CONFIG_DEBUG_ALLREGS
77	sw $s0,EOFFSET_S0(\r)	77	sw $s0,EOFFSET_S0(\r)
78	sw $s1,EOFFSET_S1(\r)	78	sw $s1,EOFFSET_S1(\r)
79	sw $s2,EOFFSET_S2(\r)	79	sw $s2,EOFFSET_S2(\r)
80	sw $s3,EOFFSET_S3(\r)	80	sw $s3,EOFFSET_S3(\r)
81	sw $s4,EOFFSET_S4(\r)	81	sw $s4,EOFFSET_S4(\r)
82	sw $s5,EOFFSET_S5(\r)	82	sw $s5,EOFFSET_S5(\r)
83	sw $s6,EOFFSET_S6(\r)	83	sw $s6,EOFFSET_S6(\r)
84	sw $s7,EOFFSET_S7(\r)	84	sw $s7,EOFFSET_S7(\r)
85	sw $s8,EOFFSET_S8(\r)	85	sw $s8,EOFFSET_S8(\r)
86	#endif	86	#endif
87		87
88	sw $gp,EOFFSET_GP(\r)	88	sw $gp,EOFFSET_GP(\r)
89	sw $ra,EOFFSET_RA(\r)	89	sw $ra,EOFFSET_RA(\r)
90	sw $sp,EOFFSET_SP(\r)	90	sw $sp,EOFFSET_SP(\r)
91		91
92	mfc0 $t0, $status	92	mfc0 $t0, $status
93	mfc0 $t1, $epc	93	mfc0 $t1, $epc
94		94
95	and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE	95	and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE
96	li $t3, ~(0x1f)	96	li $t3, ~(0x1f)
97	and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE	97	and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE
98		98
99	sw $t2,EOFFSET_STATUS(\r)	99	sw $t2,EOFFSET_STATUS(\r)
100	sw $t1,EOFFSET_EPC(\r)	100	sw $t1,EOFFSET_EPC(\r)
101	mtc0 $t0, $status	101	mtc0 $t0, $status
102	.endm	102	.endm
103		103
104	.macro REGISTERS_LOAD r	104	.macro REGISTERS_LOAD r
105	# Update only UM,EXR,IE from status, the rest	105	# Update only UM,EXR,IE from status, the rest
106	# is controlled by OS and not bound to task	106	# is controlled by OS and not bound to task
107	mfc0 $t0, $status	107	mfc0 $t0, $status
108	lw $t1,EOFFSET_STATUS(\r)	108	lw $t1,EOFFSET_STATUS(\r)
109		109
110	li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE	110	li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE
111	and $t0, $t0, $t2	111	and $t0, $t0, $t2
112		112
113	or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status	113	or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status
114	mtc0 $t0, $status	114	mtc0 $t0, $status
115		115
116	lw $v0,EOFFSET_V0(\r)	116	lw $v0,EOFFSET_V0(\r)
117	lw $v1,EOFFSET_V1(\r)	117	lw $v1,EOFFSET_V1(\r)
118	lw $a0,EOFFSET_A0(\r)	118	lw $a0,EOFFSET_A0(\r)
119	lw $a1,EOFFSET_A1(\r)	119	lw $a1,EOFFSET_A1(\r)
120	lw $a2,EOFFSET_A2(\r)	120	lw $a2,EOFFSET_A2(\r)
121	lw $a3,EOFFSET_A3(\r)	121	lw $a3,EOFFSET_A3(\r)
122	lw $t0,EOFFSET_T0(\r)	122	lw $t0,EOFFSET_T0(\r)
123	lw $t1,EOFFSET_T1(\r)	123	lw $t1,EOFFSET_T1(\r)
124	lw $t2,EOFFSET_T2(\r)	124	lw $t2,EOFFSET_T2(\r)
125	lw $t3,EOFFSET_T3(\r)	125	lw $t3,EOFFSET_T3(\r)
126	lw $t4,EOFFSET_T4(\r)	126	lw $t4,EOFFSET_T4(\r)
127	lw $t5,EOFFSET_T5(\r)	127	lw $t5,EOFFSET_T5(\r)
128	lw $t6,EOFFSET_T6(\r)	128	lw $t6,EOFFSET_T6(\r)
129	lw $t7,EOFFSET_T7(\r)	129	lw $t7,EOFFSET_T7(\r)
130	lw $t8,EOFFSET_T8(\r)	130	lw $t8,EOFFSET_T8(\r)
131	lw $t9,EOFFSET_T9(\r)	131	lw $t9,EOFFSET_T9(\r)
132		132
133	#ifdef CONFIG_DEBUG_ALLREGS	133	#ifdef CONFIG_DEBUG_ALLREGS
134	lw $s0,EOFFSET_S0(\r)	134	lw $s0,EOFFSET_S0(\r)
135	lw $s1,EOFFSET_S1(\r)	135	lw $s1,EOFFSET_S1(\r)
136	lw $s2,EOFFSET_S2(\r)	136	lw $s2,EOFFSET_S2(\r)
137	lw $s3,EOFFSET_S3(\r)	137	lw $s3,EOFFSET_S3(\r)
138	lw $s4,EOFFSET_S4(\r)	138	lw $s4,EOFFSET_S4(\r)
139	lw $s5,EOFFSET_S5(\r)	139	lw $s5,EOFFSET_S5(\r)
140	lw $s6,EOFFSET_S6(\r)	140	lw $s6,EOFFSET_S6(\r)
141	lw $s7,EOFFSET_S7(\r)	141	lw $s7,EOFFSET_S7(\r)
142	lw $s8,EOFFSET_S8(\r)	142	lw $s8,EOFFSET_S8(\r)
143	#endif	143	#endif
144	lw $gp,EOFFSET_GP(\r)	144	lw $gp,EOFFSET_GP(\r)
145	lw $ra,EOFFSET_RA(\r)	145	lw $ra,EOFFSET_RA(\r)
146		146
147	lw $at,EOFFSET_LO(\r)	147	lw $at,EOFFSET_LO(\r)
148	mtlo $at	148	mtlo $at
149	lw $at,EOFFSET_HI(\r)	149	lw $at,EOFFSET_HI(\r)
150	mthi $at	150	mthi $at
151		151
152	lw $at,EOFFSET_EPC(\r)	152	lw $at,EOFFSET_EPC(\r)
153	mtc0 $at, $epc	153	mtc0 $at, $epc
154		154
155	lw $at,EOFFSET_AT(\r)	155	lw $at,EOFFSET_AT(\r)
156	lw $sp,EOFFSET_SP(\r)	156	lw $sp,EOFFSET_SP(\r)
157	.endm	157	.endm
158		158
159	# Move kernel stack pointer address to register K0	159	# Move kernel stack pointer address to register K0
160	# - if we are in user mode, load the appropriate stack	160	# - if we are in user mode, load the appropriate stack
161	# address	161	# address
162	.macro KERNEL_STACK_TO_K0	162	.macro KERNEL_STACK_TO_K0
163	# If we are in user mode	163	# If we are in user mode
164	mfc0 $k0, $status	164	mfc0 $k0, $status
165	andi $k0, 0x10	165	andi $k0, 0x10
166		166
167	beq $k0, $0, 1f	167	beq $k0, $0, 1f
168	add $k0, $sp, 0	168	add $k0, $sp, 0
169		169
170	# Move $k0 pointer to kernel stack	170	# Move $k0 pointer to kernel stack
171	lui $k0, %hi(supervisor_sp)	171	lui $k0, %hi(supervisor_sp)
172	ori $k0, $k0, %lo(supervisor_sp)	172	ori $k0, $k0, %lo(supervisor_sp)
173	# Move $k0 (superveisor_sp)	173	# Move $k0 (superveisor_sp)
174	lw $k0, 0($k0)	174	lw $k0, 0($k0)
175	1:	175	1:
176	.endm	176	.endm
177		177
178	.org 0x0	178	.org 0x0
179	kernel_image_start:	179	kernel_image_start:
180	/* Load temporary stack */	180	/* Load temporary stack */
181	lui $sp, %hi(end_stack)	181	lui $sp, %hi(end_stack)
182	ori $sp, $sp, %lo(end_stack)	182	ori $sp, $sp, %lo(end_stack)
183		183
184	/* Not sure about this, but might be needed for PIC code???? */	184	/* Not sure about this, but might be needed for PIC code???? */
185	lui $gp, 0x8000	185	lui $gp, 0x8000
186		186
187	jal main_bsp	187	jal main_bsp
188	nop	188	nop
189		189
190		190
191	.space TEMP_STACK_SIZE	191	.space TEMP_STACK_SIZE
192	end_stack:	192	end_stack:
193		193
194	tlb_refill_entry:	194	tlb_refill_entry:
195	j tlb_refill_handler	195	j tlb_refill_handler
196	nop	196	nop
197		197
198	cache_error_entry:	198	cache_error_entry:
199	j cache_error_handler	199	j cache_error_handler
200	nop	200	nop
201		201
202	exception_entry:	202	exception_entry:
203	j exception_handler	203	j exception_handler
204	nop	204	nop
205		205
206		206
207		207
208	exception_handler:	208	exception_handler:
209	KERNEL_STACK_TO_K0	209	KERNEL_STACK_TO_K0
210		210
211	mfc0 $k1, $cause	211	mfc0 $k1, $cause
212	sub $k0, REGISTER_SPACE	212	sub $k0, REGISTER_SPACE
213		213
214	sra $k1, $k1, 0x2 # cp0_exc_cause() part 1	214	sra $k1, $k1, 0x2 # cp0_exc_cause() part 1
215	andi $k1, $k1, 0x1f # cp0_exc_cause() part 2	215	andi $k1, $k1, 0x1f # cp0_exc_cause() part 2
216	sub $k1, 8 # 8=SYSCALL	216	sub $k1, 8 # 8=SYSCALL
217		217
218	beqz $k1, uspace_shortcut	218	beqz $k1, uspace_shortcut
219	add $k1, 8 # Revert $k1 back to correct exc number	219	add $k1, 8 # Revert $k1 back to correct exc number
220		220
221	REGISTERS_STORE_AND_EXC_RESET $k0	221	REGISTERS_STORE_AND_EXC_RESET $k0
222	move $sp, $k0	222	move $sp, $k0
223		223
224	move $a1, $sp	224	move $a1, $sp
225	jal exc_dispatch # exc_dispatch(excno, register_space)	225	jal exc_dispatch # exc_dispatch(excno, register_space)
226	move $a0, $k1	226	move $a0, $k1
227		227
228	REGISTERS_LOAD $sp	228	REGISTERS_LOAD $sp
229	# The $sp is automatically restored to former value	229	# The $sp is automatically restored to former value
230	eret	230	eret
231	nop	231	nop
232		232
233	# it seems that mips reserves some space on stack for varfuncs???	233	# it seems that mips reserves some space on stack for varfuncs???
234	#define SS_ARG4 16	234	#define SS_ARG4 16
235	#define SS_SP 20	235	#define SS_SP 20
236	#define SS_STATUS 24	236	#define SS_STATUS 24
237	#define SS_EPC 28	237	#define SS_EPC 28
238	#define SS_RA 32	-
239	uspace_shortcut:	238	uspace_shortcut:
240	# We have a lot of space on the stack, with free use	239	# We have a lot of space on the stack, with free use
241	sw $sp, SS_SP($k0)	240	sw $sp, SS_SP($k0)
242	move $sp, $k0	241	move $sp, $k0
243	sw $ra, SS_RA($k0)	-
244		242
245	mfc0 $t1, $epc	243	mfc0 $t1, $epc
246	mfc0 $t0, $status	244	mfc0 $t0, $status
247	sw $t1,SS_EPC($sp) # Save EPC	245	sw $t1,SS_EPC($sp) # Save EPC
248		246
249	and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE	247	and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE
250	li $t3, ~(0x1f)	248	li $t3, ~(0x1f)
251	and $t0, $t0, $t3 # Clear KSU,EXL,ERL	249	and $t0, $t0, $t3 # Clear KSU,EXL,ERL
252	ori $t0, $t0, 0x1 # Set IE	250	ori $t0, $t0, 0x1 # Set IE
253		251
254	sw $t2,SS_STATUS($sp)	252	sw $t2,SS_STATUS($sp)
255	mtc0 $t0, $status	253	mtc0 $t0, $status
256		254
257	jal syscall_handler	255	jal syscall_handler
258	sw $v0, SS_ARG4($sp) # save v0 - arg4 to stack	256	sw $v0, SS_ARG4($sp) # save v0 - arg4 to stack
259		257
260	# Restore RA	-
261	lw $ra, SS_RA($sp)	-
262		-
263	# restore epc+4	258	# restore epc+4
264	lw $t0,SS_EPC($sp)	259	lw $t0,SS_EPC($sp)
265	addi $t0, $t0, 4	260	addi $t0, $t0, 4
266	mtc0 $t0, $epc	261	mtc0 $t0, $epc
267		262
268	# restore status	263	# restore status
269	mfc0 $t0, $status	264	mfc0 $t0, $status
270	lw $t1,SS_STATUS($sp)	265	lw $t1,SS_STATUS($sp)
271		266
272	li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE	267	li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE
273	and $t0, $t0, $t2	268	and $t0, $t0, $t2
274	or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status	269	or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status
275	mtc0 $t0, $status	270	mtc0 $t0, $status
276		271
277	lw $sp,SS_SP($sp) # restore sp	272	lw $sp,SS_SP($sp) # restore sp
278		273
279	eret	274	eret
280		275
281	tlb_refill_handler:	276	tlb_refill_handler:
282	KERNEL_STACK_TO_K0	277	KERNEL_STACK_TO_K0
283	sub $k0, REGISTER_SPACE	278	sub $k0, REGISTER_SPACE
284	REGISTERS_STORE_AND_EXC_RESET $k0	279	REGISTERS_STORE_AND_EXC_RESET $k0
285	add $sp, $k0, 0	280	add $sp, $k0, 0
286		281
287	add $a0, $sp, 0	282	add $a0, $sp, 0
288	jal tlb_refill /* tlb_refill(register_space) */	283	jal tlb_refill /* tlb_refill(register_space) */
289	nop	284	nop
290		285
291	REGISTERS_LOAD $sp	286	REGISTERS_LOAD $sp
292		287
293	eret	288	eret
294		289
295	cache_error_handler:	290	cache_error_handler:
296	KERNEL_STACK_TO_K0	291	KERNEL_STACK_TO_K0
297	sub $sp, REGISTER_SPACE	292	sub $sp, REGISTER_SPACE
298	REGISTERS_STORE_AND_EXC_RESET $sp	293	REGISTERS_STORE_AND_EXC_RESET $sp
299	add $sp, $k0, 0	294	add $sp, $k0, 0
300		295
301	jal cache_error	296	jal cache_error
302	nop	297	nop
303		298
304	REGISTERS_LOAD $sp	299	REGISTERS_LOAD $sp
305		300
306	eret	301	eret
307		302
308	userspace_asm:	303	userspace_asm:
309	add $sp, $a0, 0	304	add $sp, $a0, 0
310	add $v0, $a1, 0	305	add $v0, $a1, 0
311	eret	306	eret
312		307
313		308

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(root)/kernel/trunk/arch/mips32/src/start.S – Rev 1096 → 1097