Rev 1411 | Rev 1702 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1411 | Rev 1595 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
30 | #include <mm/asid.h> |
30 | #include <mm/asid.h> |
31 | #include <mm/tlb.h> |
31 | #include <mm/tlb.h> |
32 | #include <mm/page.h> |
32 | #include <mm/page.h> |
33 | #include <mm/as.h> |
33 | #include <mm/as.h> |
34 | #include <arch/cp0.h> |
34 | #include <arch/cp0.h> |
35 | #include <panic.h> |
35 | #include <panic.h> |
36 | #include <arch.h> |
36 | #include <arch.h> |
37 | #include <symtab.h> |
37 | #include <symtab.h> |
38 | #include <synch/spinlock.h> |
38 | #include <synch/spinlock.h> |
39 | #include <print.h> |
39 | #include <print.h> |
40 | #include <debug.h> |
40 | #include <debug.h> |
41 | #include <align.h> |
41 | #include <align.h> |
- | 42 | #include <interrupt.h> |
|
42 | 43 | ||
43 | static void tlb_refill_fail(istate_t *istate); |
44 | static void tlb_refill_fail(istate_t *istate); |
44 | static void tlb_invalid_fail(istate_t *istate); |
45 | static void tlb_invalid_fail(istate_t *istate); |
45 | static void tlb_modified_fail(istate_t *istate); |
46 | static void tlb_modified_fail(istate_t *istate); |
46 | 47 | ||
47 | static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc); |
48 | static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc); |
48 | 49 | ||
49 | static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn); |
50 | static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn); |
50 | static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); |
51 | static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); |
51 | 52 | ||
52 | /** Initialize TLB |
53 | /** Initialize TLB |
53 | * |
54 | * |
54 | * Initialize TLB. |
55 | * Initialize TLB. |
55 | * Invalidate all entries and mark wired entries. |
56 | * Invalidate all entries and mark wired entries. |
56 | */ |
57 | */ |
57 | void tlb_arch_init(void) |
58 | void tlb_arch_init(void) |
58 | { |
59 | { |
59 | int i; |
60 | int i; |
60 | 61 | ||
61 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
62 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
62 | cp0_entry_hi_write(0); |
63 | cp0_entry_hi_write(0); |
63 | cp0_entry_lo0_write(0); |
64 | cp0_entry_lo0_write(0); |
64 | cp0_entry_lo1_write(0); |
65 | cp0_entry_lo1_write(0); |
65 | 66 | ||
66 | /* Clear and initialize TLB. */ |
67 | /* Clear and initialize TLB. */ |
67 | 68 | ||
68 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
69 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
69 | cp0_index_write(i); |
70 | cp0_index_write(i); |
70 | tlbwi(); |
71 | tlbwi(); |
71 | } |
72 | } |
72 | 73 | ||
73 | 74 | ||
74 | /* |
75 | /* |
75 | * The kernel is going to make use of some wired |
76 | * The kernel is going to make use of some wired |
76 | * entries (e.g. mapping kernel stacks in kseg3). |
77 | * entries (e.g. mapping kernel stacks in kseg3). |
77 | */ |
78 | */ |
78 | cp0_wired_write(TLB_WIRED); |
79 | cp0_wired_write(TLB_WIRED); |
79 | } |
80 | } |
80 | 81 | ||
81 | /** Process TLB Refill Exception |
82 | /** Process TLB Refill Exception |
82 | * |
83 | * |
83 | * Process TLB Refill Exception. |
84 | * Process TLB Refill Exception. |
84 | * |
85 | * |
85 | * @param istate Interrupted register context. |
86 | * @param istate Interrupted register context. |
86 | */ |
87 | */ |
87 | void tlb_refill(istate_t *istate) |
88 | void tlb_refill(istate_t *istate) |
88 | { |
89 | { |
89 | entry_lo_t lo; |
90 | entry_lo_t lo; |
90 | entry_hi_t hi; |
91 | entry_hi_t hi; |
91 | asid_t asid; |
92 | asid_t asid; |
92 | __address badvaddr; |
93 | __address badvaddr; |
93 | pte_t *pte; |
94 | pte_t *pte; |
94 | int pfrc; |
95 | int pfrc; |
95 | 96 | ||
96 | badvaddr = cp0_badvaddr_read(); |
97 | badvaddr = cp0_badvaddr_read(); |
97 | 98 | ||
98 | spinlock_lock(&AS->lock); |
99 | spinlock_lock(&AS->lock); |
99 | asid = AS->asid; |
100 | asid = AS->asid; |
100 | spinlock_unlock(&AS->lock); |
101 | spinlock_unlock(&AS->lock); |
101 | 102 | ||
102 | page_table_lock(AS, true); |
103 | page_table_lock(AS, true); |
103 | 104 | ||
104 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
105 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
105 | if (!pte) { |
106 | if (!pte) { |
106 | switch (pfrc) { |
107 | switch (pfrc) { |
107 | case AS_PF_FAULT: |
108 | case AS_PF_FAULT: |
108 | goto fail; |
109 | goto fail; |
109 | break; |
110 | break; |
110 | case AS_PF_DEFER: |
111 | case AS_PF_DEFER: |
111 | /* |
112 | /* |
112 | * The page fault came during copy_from_uspace() |
113 | * The page fault came during copy_from_uspace() |
113 | * or copy_to_uspace(). |
114 | * or copy_to_uspace(). |
114 | */ |
115 | */ |
115 | page_table_unlock(AS, true); |
116 | page_table_unlock(AS, true); |
116 | return; |
117 | return; |
117 | default: |
118 | default: |
118 | panic("unexpected pfrc (%d)\n", pfrc); |
119 | panic("unexpected pfrc (%d)\n", pfrc); |
119 | } |
120 | } |
120 | } |
121 | } |
121 | 122 | ||
122 | /* |
123 | /* |
123 | * Record access to PTE. |
124 | * Record access to PTE. |
124 | */ |
125 | */ |
125 | pte->a = 1; |
126 | pte->a = 1; |
126 | 127 | ||
127 | prepare_entry_hi(&hi, asid, badvaddr); |
128 | prepare_entry_hi(&hi, asid, badvaddr); |
128 | prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
129 | prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
129 | 130 | ||
130 | /* |
131 | /* |
131 | * New entry is to be inserted into TLB |
132 | * New entry is to be inserted into TLB |
132 | */ |
133 | */ |
133 | cp0_entry_hi_write(hi.value); |
134 | cp0_entry_hi_write(hi.value); |
134 | if ((badvaddr/PAGE_SIZE) % 2 == 0) { |
135 | if ((badvaddr/PAGE_SIZE) % 2 == 0) { |
135 | cp0_entry_lo0_write(lo.value); |
136 | cp0_entry_lo0_write(lo.value); |
136 | cp0_entry_lo1_write(0); |
137 | cp0_entry_lo1_write(0); |
137 | } |
138 | } |
138 | else { |
139 | else { |
139 | cp0_entry_lo0_write(0); |
140 | cp0_entry_lo0_write(0); |
140 | cp0_entry_lo1_write(lo.value); |
141 | cp0_entry_lo1_write(lo.value); |
141 | } |
142 | } |
142 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
143 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
143 | tlbwr(); |
144 | tlbwr(); |
144 | 145 | ||
145 | page_table_unlock(AS, true); |
146 | page_table_unlock(AS, true); |
146 | return; |
147 | return; |
147 | 148 | ||
148 | fail: |
149 | fail: |
149 | page_table_unlock(AS, true); |
150 | page_table_unlock(AS, true); |
150 | tlb_refill_fail(istate); |
151 | tlb_refill_fail(istate); |
151 | } |
152 | } |
152 | 153 | ||
153 | /** Process TLB Invalid Exception |
154 | /** Process TLB Invalid Exception |
154 | * |
155 | * |
155 | * Process TLB Invalid Exception. |
156 | * Process TLB Invalid Exception. |
156 | * |
157 | * |
157 | * @param istate Interrupted register context. |
158 | * @param istate Interrupted register context. |
158 | */ |
159 | */ |
159 | void tlb_invalid(istate_t *istate) |
160 | void tlb_invalid(istate_t *istate) |
160 | { |
161 | { |
161 | tlb_index_t index; |
162 | tlb_index_t index; |
162 | __address badvaddr; |
163 | __address badvaddr; |
163 | entry_lo_t lo; |
164 | entry_lo_t lo; |
164 | entry_hi_t hi; |
165 | entry_hi_t hi; |
165 | pte_t *pte; |
166 | pte_t *pte; |
166 | int pfrc; |
167 | int pfrc; |
167 | 168 | ||
168 | badvaddr = cp0_badvaddr_read(); |
169 | badvaddr = cp0_badvaddr_read(); |
169 | 170 | ||
170 | /* |
171 | /* |
171 | * Locate the faulting entry in TLB. |
172 | * Locate the faulting entry in TLB. |
172 | */ |
173 | */ |
173 | hi.value = cp0_entry_hi_read(); |
174 | hi.value = cp0_entry_hi_read(); |
174 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
175 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
175 | cp0_entry_hi_write(hi.value); |
176 | cp0_entry_hi_write(hi.value); |
176 | tlbp(); |
177 | tlbp(); |
177 | index.value = cp0_index_read(); |
178 | index.value = cp0_index_read(); |
178 | 179 | ||
179 | page_table_lock(AS, true); |
180 | page_table_lock(AS, true); |
180 | 181 | ||
181 | /* |
182 | /* |
182 | * Fail if the entry is not in TLB. |
183 | * Fail if the entry is not in TLB. |
183 | */ |
184 | */ |
184 | if (index.p) { |
185 | if (index.p) { |
185 | printf("TLB entry not found.\n"); |
186 | printf("TLB entry not found.\n"); |
186 | goto fail; |
187 | goto fail; |
187 | } |
188 | } |
188 | 189 | ||
189 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
190 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
190 | if (!pte) { |
191 | if (!pte) { |
191 | switch (pfrc) { |
192 | switch (pfrc) { |
192 | case AS_PF_FAULT: |
193 | case AS_PF_FAULT: |
193 | goto fail; |
194 | goto fail; |
194 | break; |
195 | break; |
195 | case AS_PF_DEFER: |
196 | case AS_PF_DEFER: |
196 | /* |
197 | /* |
197 | * The page fault came during copy_from_uspace() |
198 | * The page fault came during copy_from_uspace() |
198 | * or copy_to_uspace(). |
199 | * or copy_to_uspace(). |
199 | */ |
200 | */ |
200 | page_table_unlock(AS, true); |
201 | page_table_unlock(AS, true); |
201 | return; |
202 | return; |
202 | default: |
203 | default: |
203 | panic("unexpected pfrc (%d)\n", pfrc); |
204 | panic("unexpected pfrc (%d)\n", pfrc); |
204 | } |
205 | } |
205 | } |
206 | } |
206 | 207 | ||
207 | /* |
208 | /* |
208 | * Read the faulting TLB entry. |
209 | * Read the faulting TLB entry. |
209 | */ |
210 | */ |
210 | tlbr(); |
211 | tlbr(); |
211 | 212 | ||
212 | /* |
213 | /* |
213 | * Record access to PTE. |
214 | * Record access to PTE. |
214 | */ |
215 | */ |
215 | pte->a = 1; |
216 | pte->a = 1; |
216 | 217 | ||
217 | prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
218 | prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
218 | 219 | ||
219 | /* |
220 | /* |
220 | * The entry is to be updated in TLB. |
221 | * The entry is to be updated in TLB. |
221 | */ |
222 | */ |
222 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
223 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
223 | cp0_entry_lo0_write(lo.value); |
224 | cp0_entry_lo0_write(lo.value); |
224 | else |
225 | else |
225 | cp0_entry_lo1_write(lo.value); |
226 | cp0_entry_lo1_write(lo.value); |
226 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
227 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
227 | tlbwi(); |
228 | tlbwi(); |
228 | 229 | ||
229 | page_table_unlock(AS, true); |
230 | page_table_unlock(AS, true); |
230 | return; |
231 | return; |
231 | 232 | ||
232 | fail: |
233 | fail: |
233 | page_table_unlock(AS, true); |
234 | page_table_unlock(AS, true); |
234 | tlb_invalid_fail(istate); |
235 | tlb_invalid_fail(istate); |
235 | } |
236 | } |
236 | 237 | ||
237 | /** Process TLB Modified Exception |
238 | /** Process TLB Modified Exception |
238 | * |
239 | * |
239 | * Process TLB Modified Exception. |
240 | * Process TLB Modified Exception. |
240 | * |
241 | * |
241 | * @param istate Interrupted register context. |
242 | * @param istate Interrupted register context. |
242 | */ |
243 | */ |
243 | void tlb_modified(istate_t *istate) |
244 | void tlb_modified(istate_t *istate) |
244 | { |
245 | { |
245 | tlb_index_t index; |
246 | tlb_index_t index; |
246 | __address badvaddr; |
247 | __address badvaddr; |
247 | entry_lo_t lo; |
248 | entry_lo_t lo; |
248 | entry_hi_t hi; |
249 | entry_hi_t hi; |
249 | pte_t *pte; |
250 | pte_t *pte; |
250 | int pfrc; |
251 | int pfrc; |
251 | 252 | ||
252 | badvaddr = cp0_badvaddr_read(); |
253 | badvaddr = cp0_badvaddr_read(); |
253 | 254 | ||
254 | /* |
255 | /* |
255 | * Locate the faulting entry in TLB. |
256 | * Locate the faulting entry in TLB. |
256 | */ |
257 | */ |
257 | hi.value = cp0_entry_hi_read(); |
258 | hi.value = cp0_entry_hi_read(); |
258 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
259 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
259 | cp0_entry_hi_write(hi.value); |
260 | cp0_entry_hi_write(hi.value); |
260 | tlbp(); |
261 | tlbp(); |
261 | index.value = cp0_index_read(); |
262 | index.value = cp0_index_read(); |
262 | 263 | ||
263 | page_table_lock(AS, true); |
264 | page_table_lock(AS, true); |
264 | 265 | ||
265 | /* |
266 | /* |
266 | * Fail if the entry is not in TLB. |
267 | * Fail if the entry is not in TLB. |
267 | */ |
268 | */ |
268 | if (index.p) { |
269 | if (index.p) { |
269 | printf("TLB entry not found.\n"); |
270 | printf("TLB entry not found.\n"); |
270 | goto fail; |
271 | goto fail; |
271 | } |
272 | } |
272 | 273 | ||
273 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
274 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
274 | if (!pte) { |
275 | if (!pte) { |
275 | switch (pfrc) { |
276 | switch (pfrc) { |
276 | case AS_PF_FAULT: |
277 | case AS_PF_FAULT: |
277 | goto fail; |
278 | goto fail; |
278 | break; |
279 | break; |
279 | case AS_PF_DEFER: |
280 | case AS_PF_DEFER: |
280 | /* |
281 | /* |
281 | * The page fault came during copy_from_uspace() |
282 | * The page fault came during copy_from_uspace() |
282 | * or copy_to_uspace(). |
283 | * or copy_to_uspace(). |
283 | */ |
284 | */ |
284 | page_table_unlock(AS, true); |
285 | page_table_unlock(AS, true); |
285 | return; |
286 | return; |
286 | default: |
287 | default: |
287 | panic("unexpected pfrc (%d)\n", pfrc); |
288 | panic("unexpected pfrc (%d)\n", pfrc); |
288 | } |
289 | } |
289 | } |
290 | } |
290 | 291 | ||
291 | /* |
292 | /* |
292 | * Fail if the page is not writable. |
293 | * Fail if the page is not writable. |
293 | */ |
294 | */ |
294 | if (!pte->w) |
295 | if (!pte->w) |
295 | goto fail; |
296 | goto fail; |
296 | 297 | ||
297 | /* |
298 | /* |
298 | * Read the faulting TLB entry. |
299 | * Read the faulting TLB entry. |
299 | */ |
300 | */ |
300 | tlbr(); |
301 | tlbr(); |
301 | 302 | ||
302 | /* |
303 | /* |
303 | * Record access and write to PTE. |
304 | * Record access and write to PTE. |
304 | */ |
305 | */ |
305 | pte->a = 1; |
306 | pte->a = 1; |
306 | pte->d = 1; |
307 | pte->d = 1; |
307 | 308 | ||
308 | prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); |
309 | prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); |
309 | 310 | ||
310 | /* |
311 | /* |
311 | * The entry is to be updated in TLB. |
312 | * The entry is to be updated in TLB. |
312 | */ |
313 | */ |
313 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
314 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
314 | cp0_entry_lo0_write(lo.value); |
315 | cp0_entry_lo0_write(lo.value); |
315 | else |
316 | else |
316 | cp0_entry_lo1_write(lo.value); |
317 | cp0_entry_lo1_write(lo.value); |
317 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
318 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
318 | tlbwi(); |
319 | tlbwi(); |
319 | 320 | ||
320 | page_table_unlock(AS, true); |
321 | page_table_unlock(AS, true); |
321 | return; |
322 | return; |
322 | 323 | ||
323 | fail: |
324 | fail: |
324 | page_table_unlock(AS, true); |
325 | page_table_unlock(AS, true); |
325 | tlb_modified_fail(istate); |
326 | tlb_modified_fail(istate); |
326 | } |
327 | } |
327 | 328 | ||
328 | void tlb_refill_fail(istate_t *istate) |
329 | void tlb_refill_fail(istate_t *istate) |
329 | { |
330 | { |
330 | char *symbol = ""; |
331 | char *symbol = ""; |
331 | char *sym2 = ""; |
332 | char *sym2 = ""; |
332 | 333 | ||
333 | char *s = get_symtab_entry(istate->epc); |
334 | char *s = get_symtab_entry(istate->epc); |
334 | if (s) |
335 | if (s) |
335 | symbol = s; |
336 | symbol = s; |
336 | s = get_symtab_entry(istate->ra); |
337 | s = get_symtab_entry(istate->ra); |
337 | if (s) |
338 | if (s) |
338 | sym2 = s; |
339 | sym2 = s; |
- | 340 | ||
- | 341 | fault_if_from_uspace(istate, "TLB Refill Exception on %P", cp0_badvaddr_read()); |
|
339 | panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2); |
342 | panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2); |
340 | } |
343 | } |
341 | 344 | ||
342 | 345 | ||
343 | void tlb_invalid_fail(istate_t *istate) |
346 | void tlb_invalid_fail(istate_t *istate) |
344 | { |
347 | { |
345 | char *symbol = ""; |
348 | char *symbol = ""; |
346 | 349 | ||
347 | char *s = get_symtab_entry(istate->epc); |
350 | char *s = get_symtab_entry(istate->epc); |
348 | if (s) |
351 | if (s) |
349 | symbol = s; |
352 | symbol = s; |
- | 353 | fault_if_from_uspace(istate, "TLB Invalid Exception on %P", cp0_badvaddr_read()); |
|
350 | panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
354 | panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
351 | } |
355 | } |
352 | 356 | ||
353 | void tlb_modified_fail(istate_t *istate) |
357 | void tlb_modified_fail(istate_t *istate) |
354 | { |
358 | { |
355 | char *symbol = ""; |
359 | char *symbol = ""; |
356 | 360 | ||
357 | char *s = get_symtab_entry(istate->epc); |
361 | char *s = get_symtab_entry(istate->epc); |
358 | if (s) |
362 | if (s) |
359 | symbol = s; |
363 | symbol = s; |
- | 364 | fault_if_from_uspace(istate, "TLB Modified Exception on %P", cp0_badvaddr_read()); |
|
360 | panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
365 | panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
361 | } |
366 | } |
362 | 367 | ||
363 | /** Try to find PTE for faulting address |
368 | /** Try to find PTE for faulting address |
364 | * |
369 | * |
365 | * Try to find PTE for faulting address. |
370 | * Try to find PTE for faulting address. |
366 | * The AS->lock must be held on entry to this function. |
371 | * The AS->lock must be held on entry to this function. |
367 | * |
372 | * |
368 | * @param badvaddr Faulting virtual address. |
373 | * @param badvaddr Faulting virtual address. |
369 | * @param access Access mode that caused the fault. |
374 | * @param access Access mode that caused the fault. |
370 | * @param istate Pointer to interrupted state. |
375 | * @param istate Pointer to interrupted state. |
371 | * @param pfrc Pointer to variable where as_page_fault() return code will be stored. |
376 | * @param pfrc Pointer to variable where as_page_fault() return code will be stored. |
372 | * |
377 | * |
373 | * @return PTE on success, NULL otherwise. |
378 | * @return PTE on success, NULL otherwise. |
374 | */ |
379 | */ |
375 | pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc) |
380 | pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc) |
376 | { |
381 | { |
377 | entry_hi_t hi; |
382 | entry_hi_t hi; |
378 | pte_t *pte; |
383 | pte_t *pte; |
379 | 384 | ||
380 | hi.value = cp0_entry_hi_read(); |
385 | hi.value = cp0_entry_hi_read(); |
381 | 386 | ||
382 | /* |
387 | /* |
383 | * Handler cannot succeed if the ASIDs don't match. |
388 | * Handler cannot succeed if the ASIDs don't match. |
384 | */ |
389 | */ |
385 | if (hi.asid != AS->asid) { |
390 | if (hi.asid != AS->asid) { |
386 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
391 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
387 | return NULL; |
392 | return NULL; |
388 | } |
393 | } |
389 | 394 | ||
390 | /* |
395 | /* |
391 | * Check if the mapping exists in page tables. |
396 | * Check if the mapping exists in page tables. |
392 | */ |
397 | */ |
393 | pte = page_mapping_find(AS, badvaddr); |
398 | pte = page_mapping_find(AS, badvaddr); |
394 | if (pte && pte->p) { |
399 | if (pte && pte->p) { |
395 | /* |
400 | /* |
396 | * Mapping found in page tables. |
401 | * Mapping found in page tables. |
397 | * Immediately succeed. |
402 | * Immediately succeed. |
398 | */ |
403 | */ |
399 | return pte; |
404 | return pte; |
400 | } else { |
405 | } else { |
401 | int rc; |
406 | int rc; |
402 | 407 | ||
403 | /* |
408 | /* |
404 | * Mapping not found in page tables. |
409 | * Mapping not found in page tables. |
405 | * Resort to higher-level page fault handler. |
410 | * Resort to higher-level page fault handler. |
406 | */ |
411 | */ |
407 | page_table_unlock(AS, true); |
412 | page_table_unlock(AS, true); |
408 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
413 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
409 | case AS_PF_OK: |
414 | case AS_PF_OK: |
410 | /* |
415 | /* |
411 | * The higher-level page fault handler succeeded, |
416 | * The higher-level page fault handler succeeded, |
412 | * The mapping ought to be in place. |
417 | * The mapping ought to be in place. |
413 | */ |
418 | */ |
414 | page_table_lock(AS, true); |
419 | page_table_lock(AS, true); |
415 | pte = page_mapping_find(AS, badvaddr); |
420 | pte = page_mapping_find(AS, badvaddr); |
416 | ASSERT(pte && pte->p); |
421 | ASSERT(pte && pte->p); |
417 | return pte; |
422 | return pte; |
418 | break; |
423 | break; |
419 | case AS_PF_DEFER: |
424 | case AS_PF_DEFER: |
420 | page_table_lock(AS, true); |
425 | page_table_lock(AS, true); |
421 | *pfrc = AS_PF_DEFER; |
426 | *pfrc = AS_PF_DEFER; |
422 | return NULL; |
427 | return NULL; |
423 | break; |
428 | break; |
424 | case AS_PF_FAULT: |
429 | case AS_PF_FAULT: |
425 | page_table_lock(AS, true); |
430 | page_table_lock(AS, true); |
426 | printf("Page fault.\n"); |
431 | printf("Page fault.\n"); |
427 | *pfrc = AS_PF_FAULT; |
432 | *pfrc = AS_PF_FAULT; |
428 | return NULL; |
433 | return NULL; |
429 | break; |
434 | break; |
430 | default: |
435 | default: |
431 | panic("unexpected rc (%d)\n", rc); |
436 | panic("unexpected rc (%d)\n", rc); |
432 | } |
437 | } |
433 | 438 | ||
434 | } |
439 | } |
435 | } |
440 | } |
436 | 441 | ||
437 | void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn) |
442 | void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn) |
438 | { |
443 | { |
439 | lo->value = 0; |
444 | lo->value = 0; |
440 | lo->g = g; |
445 | lo->g = g; |
441 | lo->v = v; |
446 | lo->v = v; |
442 | lo->d = d; |
447 | lo->d = d; |
443 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
448 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
444 | lo->pfn = pfn; |
449 | lo->pfn = pfn; |
445 | } |
450 | } |
446 | 451 | ||
447 | void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr) |
452 | void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr) |
448 | { |
453 | { |
449 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
454 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
450 | hi->asid = asid; |
455 | hi->asid = asid; |
451 | } |
456 | } |
452 | 457 | ||
453 | /** Print contents of TLB. */ |
458 | /** Print contents of TLB. */ |
454 | void tlb_print(void) |
459 | void tlb_print(void) |
455 | { |
460 | { |
456 | page_mask_t mask; |
461 | page_mask_t mask; |
457 | entry_lo_t lo0, lo1; |
462 | entry_lo_t lo0, lo1; |
458 | entry_hi_t hi, hi_save; |
463 | entry_hi_t hi, hi_save; |
459 | int i; |
464 | int i; |
460 | 465 | ||
461 | hi_save.value = cp0_entry_hi_read(); |
466 | hi_save.value = cp0_entry_hi_read(); |
462 | 467 | ||
463 | printf("TLB:\n"); |
468 | printf("TLB:\n"); |
464 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
469 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
465 | cp0_index_write(i); |
470 | cp0_index_write(i); |
466 | tlbr(); |
471 | tlbr(); |
467 | 472 | ||
468 | mask.value = cp0_pagemask_read(); |
473 | mask.value = cp0_pagemask_read(); |
469 | hi.value = cp0_entry_hi_read(); |
474 | hi.value = cp0_entry_hi_read(); |
470 | lo0.value = cp0_entry_lo0_read(); |
475 | lo0.value = cp0_entry_lo0_read(); |
471 | lo1.value = cp0_entry_lo1_read(); |
476 | lo1.value = cp0_entry_lo1_read(); |
472 | 477 | ||
473 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n" |
478 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n" |
474 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n", |
479 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n", |
475 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
480 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
476 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
481 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
477 | } |
482 | } |
478 | 483 | ||
479 | cp0_entry_hi_write(hi_save.value); |
484 | cp0_entry_hi_write(hi_save.value); |
480 | } |
485 | } |
481 | 486 | ||
482 | /** Invalidate all not wired TLB entries. */ |
487 | /** Invalidate all not wired TLB entries. */ |
483 | void tlb_invalidate_all(void) |
488 | void tlb_invalidate_all(void) |
484 | { |
489 | { |
485 | ipl_t ipl; |
490 | ipl_t ipl; |
486 | entry_lo_t lo0, lo1; |
491 | entry_lo_t lo0, lo1; |
487 | entry_hi_t hi_save; |
492 | entry_hi_t hi_save; |
488 | int i; |
493 | int i; |
489 | 494 | ||
490 | hi_save.value = cp0_entry_hi_read(); |
495 | hi_save.value = cp0_entry_hi_read(); |
491 | ipl = interrupts_disable(); |
496 | ipl = interrupts_disable(); |
492 | 497 | ||
493 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
498 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
494 | cp0_index_write(i); |
499 | cp0_index_write(i); |
495 | tlbr(); |
500 | tlbr(); |
496 | 501 | ||
497 | lo0.value = cp0_entry_lo0_read(); |
502 | lo0.value = cp0_entry_lo0_read(); |
498 | lo1.value = cp0_entry_lo1_read(); |
503 | lo1.value = cp0_entry_lo1_read(); |
499 | 504 | ||
500 | lo0.v = 0; |
505 | lo0.v = 0; |
501 | lo1.v = 0; |
506 | lo1.v = 0; |
502 | 507 | ||
503 | cp0_entry_lo0_write(lo0.value); |
508 | cp0_entry_lo0_write(lo0.value); |
504 | cp0_entry_lo1_write(lo1.value); |
509 | cp0_entry_lo1_write(lo1.value); |
505 | 510 | ||
506 | tlbwi(); |
511 | tlbwi(); |
507 | } |
512 | } |
508 | 513 | ||
509 | interrupts_restore(ipl); |
514 | interrupts_restore(ipl); |
510 | cp0_entry_hi_write(hi_save.value); |
515 | cp0_entry_hi_write(hi_save.value); |
511 | } |
516 | } |
512 | 517 | ||
513 | /** Invalidate all TLB entries belonging to specified address space. |
518 | /** Invalidate all TLB entries belonging to specified address space. |
514 | * |
519 | * |
515 | * @param asid Address space identifier. |
520 | * @param asid Address space identifier. |
516 | */ |
521 | */ |
517 | void tlb_invalidate_asid(asid_t asid) |
522 | void tlb_invalidate_asid(asid_t asid) |
518 | { |
523 | { |
519 | ipl_t ipl; |
524 | ipl_t ipl; |
520 | entry_lo_t lo0, lo1; |
525 | entry_lo_t lo0, lo1; |
521 | entry_hi_t hi, hi_save; |
526 | entry_hi_t hi, hi_save; |
522 | int i; |
527 | int i; |
523 | 528 | ||
524 | ASSERT(asid != ASID_INVALID); |
529 | ASSERT(asid != ASID_INVALID); |
525 | 530 | ||
526 | hi_save.value = cp0_entry_hi_read(); |
531 | hi_save.value = cp0_entry_hi_read(); |
527 | ipl = interrupts_disable(); |
532 | ipl = interrupts_disable(); |
528 | 533 | ||
529 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
534 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
530 | cp0_index_write(i); |
535 | cp0_index_write(i); |
531 | tlbr(); |
536 | tlbr(); |
532 | 537 | ||
533 | hi.value = cp0_entry_hi_read(); |
538 | hi.value = cp0_entry_hi_read(); |
534 | 539 | ||
535 | if (hi.asid == asid) { |
540 | if (hi.asid == asid) { |
536 | lo0.value = cp0_entry_lo0_read(); |
541 | lo0.value = cp0_entry_lo0_read(); |
537 | lo1.value = cp0_entry_lo1_read(); |
542 | lo1.value = cp0_entry_lo1_read(); |
538 | 543 | ||
539 | lo0.v = 0; |
544 | lo0.v = 0; |
540 | lo1.v = 0; |
545 | lo1.v = 0; |
541 | 546 | ||
542 | cp0_entry_lo0_write(lo0.value); |
547 | cp0_entry_lo0_write(lo0.value); |
543 | cp0_entry_lo1_write(lo1.value); |
548 | cp0_entry_lo1_write(lo1.value); |
544 | 549 | ||
545 | tlbwi(); |
550 | tlbwi(); |
546 | } |
551 | } |
547 | } |
552 | } |
548 | 553 | ||
549 | interrupts_restore(ipl); |
554 | interrupts_restore(ipl); |
550 | cp0_entry_hi_write(hi_save.value); |
555 | cp0_entry_hi_write(hi_save.value); |
551 | } |
556 | } |
552 | 557 | ||
553 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
558 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
554 | * |
559 | * |
555 | * @param asid Address space identifier. |
560 | * @param asid Address space identifier. |
556 | * @param page First page whose TLB entry is to be invalidated. |
561 | * @param page First page whose TLB entry is to be invalidated. |
557 | * @param cnt Number of entries to invalidate. |
562 | * @param cnt Number of entries to invalidate. |
558 | */ |
563 | */ |
559 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
564 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
560 | { |
565 | { |
561 | int i; |
566 | int i; |
562 | ipl_t ipl; |
567 | ipl_t ipl; |
563 | entry_lo_t lo0, lo1; |
568 | entry_lo_t lo0, lo1; |
564 | entry_hi_t hi, hi_save; |
569 | entry_hi_t hi, hi_save; |
565 | tlb_index_t index; |
570 | tlb_index_t index; |
566 | 571 | ||
567 | ASSERT(asid != ASID_INVALID); |
572 | ASSERT(asid != ASID_INVALID); |
568 | 573 | ||
569 | hi_save.value = cp0_entry_hi_read(); |
574 | hi_save.value = cp0_entry_hi_read(); |
570 | ipl = interrupts_disable(); |
575 | ipl = interrupts_disable(); |
571 | 576 | ||
572 | for (i = 0; i < cnt+1; i+=2) { |
577 | for (i = 0; i < cnt+1; i+=2) { |
573 | hi.value = 0; |
578 | hi.value = 0; |
574 | prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
579 | prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
575 | cp0_entry_hi_write(hi.value); |
580 | cp0_entry_hi_write(hi.value); |
576 | 581 | ||
577 | tlbp(); |
582 | tlbp(); |
578 | index.value = cp0_index_read(); |
583 | index.value = cp0_index_read(); |
579 | 584 | ||
580 | if (!index.p) { |
585 | if (!index.p) { |
581 | /* Entry was found, index register contains valid index. */ |
586 | /* Entry was found, index register contains valid index. */ |
582 | tlbr(); |
587 | tlbr(); |
583 | 588 | ||
584 | lo0.value = cp0_entry_lo0_read(); |
589 | lo0.value = cp0_entry_lo0_read(); |
585 | lo1.value = cp0_entry_lo1_read(); |
590 | lo1.value = cp0_entry_lo1_read(); |
586 | 591 | ||
587 | lo0.v = 0; |
592 | lo0.v = 0; |
588 | lo1.v = 0; |
593 | lo1.v = 0; |
589 | 594 | ||
590 | cp0_entry_lo0_write(lo0.value); |
595 | cp0_entry_lo0_write(lo0.value); |
591 | cp0_entry_lo1_write(lo1.value); |
596 | cp0_entry_lo1_write(lo1.value); |
592 | 597 | ||
593 | tlbwi(); |
598 | tlbwi(); |
594 | } |
599 | } |
595 | } |
600 | } |
596 | 601 | ||
597 | interrupts_restore(ipl); |
602 | interrupts_restore(ipl); |
598 | cp0_entry_hi_write(hi_save.value); |
603 | cp0_entry_hi_write(hi_save.value); |
599 | } |
604 | } |
600 | 605 |