WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/mm/tlb.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <genarch/mm/asid_fifo.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
 
static void tlb_refill_fail(struct exception_regdump *pstate);
static void tlb_invalid_fail(struct exception_regdump *pstate);
static void tlb_modified_fail(struct exception_regdump *pstate);
 
static pte_t *find_mapping_and_check(__address badvaddr);
 
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    asid_fifo_init();
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception
 *
 * Process TLB Refill Exception.
 *
 * @param pstate Interrupted register context.
 */
void tlb_refill(struct exception_regdump *pstate)
{
    entry_lo_t lo;
    entry_hi_t hi; 
    __address badvaddr;
    pte_t *pte;
 
    badvaddr = cp0_badvaddr_read();
 
    spinlock_lock(&AS->lock);      
 
    pte = find_mapping_and_check(badvaddr);
    if (!pte)
        goto fail;
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_hi(&hi, AS->asid, badvaddr);
    prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    spinlock_unlock(&AS->lock);
    return;
   
fail:
    spinlock_unlock(&AS->lock);
    tlb_refill_fail(pstate);
}
 
/** Process TLB Invalid Exception
 *
 * Process TLB Invalid Exception.
 *
 * @param pstate Interrupted register context.
 */
void tlb_invalid(struct exception_regdump *pstate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
   
    spinlock_lock(&AS->lock);  
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr);
    if (!pte)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    spinlock_unlock(&AS->lock);
    return;
   
fail:
    spinlock_unlock(&AS->lock);
    tlb_invalid_fail(pstate);
}
 
/** Process TLB Modified Exception
 *
 * Process TLB Modified Exception.
 *
 * @param pstate Interrupted register context.
 */
void tlb_modified(struct exception_regdump *pstate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
   
    spinlock_lock(&AS->lock);  
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr);
    if (!pte)
        goto fail;
 
    /*
     * Fail if the page is not writable.
     */
    if (!pte->w)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->lo.d = 1;
 
    prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    spinlock_unlock(&AS->lock);
    return;
   
fail:
    spinlock_unlock(&AS->lock);
    tlb_modified_fail(pstate);
}
 
void tlb_refill_fail(struct exception_regdump *pstate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(pstate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(pstate->ra);
    if (s)
        sym2 = s;
    panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(struct exception_regdump *pstate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(pstate->epc);
    if (s)
        symbol = s;
    panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
}
 
void tlb_modified_fail(struct exception_regdump *pstate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(pstate->epc);
    if (s)
        symbol = s;
    panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
}
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr Faulting virtual address.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(__address badvaddr)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(badvaddr, AS->asid, 0);
    if (pte && pte->lo.v) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        if (as_page_fault(badvaddr)) {
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            pte = page_mapping_find(badvaddr, AS->asid, 0);
            ASSERT(pte && pte->lo.v);
            return pte;
        }
    }
 
    /*
     * Handler cannot succeed if badvaddr has no mapping.
     */
    if (!pte) {
        printf("No such mapping.\n");
        return NULL;
    }
 
    /*
     * Handler cannot succeed if the mapping is marked as invalid.
     */
    if (!pte->lo.v) {
        printf("Invalid mapping.\n");
        return NULL;
    }
 
    return pte;
}
 
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = c;
    lo->pfn = pfn;
}
 
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
{
    hi->value = (((addr/PAGE_SIZE)/2)*PAGE_SIZE*2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
 
    printf("TLB:\n");
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"
               "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",
               i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
               lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified address space.
 *
 * @param asid Address space identifier.
 * @param page First page whose TLB entry is to be invalidated.
 * @param cnt Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt; i++) {
        hi.value = 0;
        prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /* Entry was found, index register contains valid index. */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 

Rev 727	Rev 730
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <mm/asid.h>	30	#include <mm/asid.h>
-		31	#include <genarch/mm/asid_fifo.h>
31	#include <mm/tlb.h>	32	#include <mm/tlb.h>
32	#include <mm/page.h>	33	#include <mm/page.h>
33	#include <mm/as.h>	34	#include <mm/as.h>
34	#include <arch/cp0.h>	35	#include <arch/cp0.h>
35	#include <panic.h>	36	#include <panic.h>
36	#include <arch.h>	37	#include <arch.h>
37	#include <symtab.h>	38	#include <symtab.h>
38	#include <synch/spinlock.h>	39	#include <synch/spinlock.h>
39	#include <print.h>	40	#include <print.h>
40	#include <debug.h>	41	#include <debug.h>
41		42
42	static void tlb_refill_fail(struct exception_regdump *pstate);	43	static void tlb_refill_fail(struct exception_regdump *pstate);
43	static void tlb_invalid_fail(struct exception_regdump *pstate);	44	static void tlb_invalid_fail(struct exception_regdump *pstate);
44	static void tlb_modified_fail(struct exception_regdump *pstate);	45	static void tlb_modified_fail(struct exception_regdump *pstate);
45		46
46	static pte_t *find_mapping_and_check(__address badvaddr);	47	static pte_t *find_mapping_and_check(__address badvaddr);
47		48
48	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);	49	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
49	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);	50	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
50		51
51	/** Initialize TLB	52	/** Initialize TLB
52	*	53	*
53	* Initialize TLB.	54	* Initialize TLB.
54	* Invalidate all entries and mark wired entries.	55	* Invalidate all entries and mark wired entries.
55	*/	56	*/
56	void tlb_arch_init(void)	57	void tlb_arch_init(void)
57	{	58	{
58	int i;	59	int i;
59		60
-		61	asid_fifo_init();
-		62
60	cp0_pagemask_write(TLB_PAGE_MASK_16K);	63	cp0_pagemask_write(TLB_PAGE_MASK_16K);
61	cp0_entry_hi_write(0);	64	cp0_entry_hi_write(0);
62	cp0_entry_lo0_write(0);	65	cp0_entry_lo0_write(0);
63	cp0_entry_lo1_write(0);	66	cp0_entry_lo1_write(0);
64		67
65	/* Clear and initialize TLB. */	68	/* Clear and initialize TLB. */
66		69
67	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	70	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
68	cp0_index_write(i);	71	cp0_index_write(i);
69	tlbwi();	72	tlbwi();
70	}	73	}
71		74
72		75
73	/*	76	/*
74	* The kernel is going to make use of some wired	77	* The kernel is going to make use of some wired
75	* entries (e.g. mapping kernel stacks in kseg3).	78	* entries (e.g. mapping kernel stacks in kseg3).
76	*/	79	*/
77	cp0_wired_write(TLB_WIRED);	80	cp0_wired_write(TLB_WIRED);
78	}	81	}
79		82
80	/** Process TLB Refill Exception	83	/** Process TLB Refill Exception
81	*	84	*
82	* Process TLB Refill Exception.	85	* Process TLB Refill Exception.
83	*	86	*
84	* @param pstate Interrupted register context.	87	* @param pstate Interrupted register context.
85	*/	88	*/
86	void tlb_refill(struct exception_regdump *pstate)	89	void tlb_refill(struct exception_regdump *pstate)
87	{	90	{
88	entry_lo_t lo;	91	entry_lo_t lo;
89	entry_hi_t hi;	92	entry_hi_t hi;
90	__address badvaddr;	93	__address badvaddr;
91	pte_t *pte;	94	pte_t *pte;
92		95
93	badvaddr = cp0_badvaddr_read();	96	badvaddr = cp0_badvaddr_read();
94		97
95	spinlock_lock(&AS->lock);	98	spinlock_lock(&AS->lock);
96		99
97	pte = find_mapping_and_check(badvaddr);	100	pte = find_mapping_and_check(badvaddr);
98	if (!pte)	101	if (!pte)
99	goto fail;	102	goto fail;
100		103
101	/*	104	/*
102	* Record access to PTE.	105	* Record access to PTE.
103	*/	106	*/
104	pte->a = 1;	107	pte->a = 1;
105		108
106	prepare_entry_hi(&hi, AS->asid, badvaddr);	109	prepare_entry_hi(&hi, AS->asid, badvaddr);
107	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);	110	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
108		111
109	/*	112	/*
110	* New entry is to be inserted into TLB	113	* New entry is to be inserted into TLB
111	*/	114	*/
112	cp0_entry_hi_write(hi.value);	115	cp0_entry_hi_write(hi.value);
113	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	116	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
114	cp0_entry_lo0_write(lo.value);	117	cp0_entry_lo0_write(lo.value);
115	cp0_entry_lo1_write(0);	118	cp0_entry_lo1_write(0);
116	}	119	}
117	else {	120	else {
118	cp0_entry_lo0_write(0);	121	cp0_entry_lo0_write(0);
119	cp0_entry_lo1_write(lo.value);	122	cp0_entry_lo1_write(lo.value);
120	}	123	}
121	cp0_pagemask_write(TLB_PAGE_MASK_16K);	124	cp0_pagemask_write(TLB_PAGE_MASK_16K);
122	tlbwr();	125	tlbwr();
123		126
124	spinlock_unlock(&AS->lock);	127	spinlock_unlock(&AS->lock);
125	return;	128	return;
126		129
127	fail:	130	fail:
128	spinlock_unlock(&AS->lock);	131	spinlock_unlock(&AS->lock);
129	tlb_refill_fail(pstate);	132	tlb_refill_fail(pstate);
130	}	133	}
131		134
132	/** Process TLB Invalid Exception	135	/** Process TLB Invalid Exception
133	*	136	*
134	* Process TLB Invalid Exception.	137	* Process TLB Invalid Exception.
135	*	138	*
136	* @param pstate Interrupted register context.	139	* @param pstate Interrupted register context.
137	*/	140	*/
138	void tlb_invalid(struct exception_regdump *pstate)	141	void tlb_invalid(struct exception_regdump *pstate)
139	{	142	{
140	tlb_index_t index;	143	tlb_index_t index;
141	__address badvaddr;	144	__address badvaddr;
142	entry_lo_t lo;	145	entry_lo_t lo;
143	entry_hi_t hi;	146	entry_hi_t hi;
144	pte_t *pte;	147	pte_t *pte;
145		148
146	badvaddr = cp0_badvaddr_read();	149	badvaddr = cp0_badvaddr_read();
147		150
148	/*	151	/*
149	* Locate the faulting entry in TLB.	152	* Locate the faulting entry in TLB.
150	*/	153	*/
151	hi.value = cp0_entry_hi_read();	154	hi.value = cp0_entry_hi_read();
152	prepare_entry_hi(&hi, hi.asid, badvaddr);	155	prepare_entry_hi(&hi, hi.asid, badvaddr);
153	cp0_entry_hi_write(hi.value);	156	cp0_entry_hi_write(hi.value);
154	tlbp();	157	tlbp();
155	index.value = cp0_index_read();	158	index.value = cp0_index_read();
156		159
157	spinlock_lock(&AS->lock);	160	spinlock_lock(&AS->lock);
158		161
159	/*	162	/*
160	* Fail if the entry is not in TLB.	163	* Fail if the entry is not in TLB.
161	*/	164	*/
162	if (index.p) {	165	if (index.p) {
163	printf("TLB entry not found.\n");	166	printf("TLB entry not found.\n");
164	goto fail;	167	goto fail;
165	}	168	}
166		169
167	pte = find_mapping_and_check(badvaddr);	170	pte = find_mapping_and_check(badvaddr);
168	if (!pte)	171	if (!pte)
169	goto fail;	172	goto fail;
170		173
171	/*	174	/*
172	* Read the faulting TLB entry.	175	* Read the faulting TLB entry.
173	*/	176	*/
174	tlbr();	177	tlbr();
175		178
176	/*	179	/*
177	* Record access to PTE.	180	* Record access to PTE.
178	*/	181	*/
179	pte->a = 1;	182	pte->a = 1;
180		183
181	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);	184	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
182		185
183	/*	186	/*
184	* The entry is to be updated in TLB.	187	* The entry is to be updated in TLB.
185	*/	188	*/
186	if ((badvaddr/PAGE_SIZE) % 2 == 0)	189	if ((badvaddr/PAGE_SIZE) % 2 == 0)
187	cp0_entry_lo0_write(lo.value);	190	cp0_entry_lo0_write(lo.value);
188	else	191	else
189	cp0_entry_lo1_write(lo.value);	192	cp0_entry_lo1_write(lo.value);
190	cp0_pagemask_write(TLB_PAGE_MASK_16K);	193	cp0_pagemask_write(TLB_PAGE_MASK_16K);
191	tlbwi();	194	tlbwi();
192		195
193	spinlock_unlock(&AS->lock);	196	spinlock_unlock(&AS->lock);
194	return;	197	return;
195		198
196	fail:	199	fail:
197	spinlock_unlock(&AS->lock);	200	spinlock_unlock(&AS->lock);
198	tlb_invalid_fail(pstate);	201	tlb_invalid_fail(pstate);
199	}	202	}
200		203
201	/** Process TLB Modified Exception	204	/** Process TLB Modified Exception
202	*	205	*
203	* Process TLB Modified Exception.	206	* Process TLB Modified Exception.
204	*	207	*
205	* @param pstate Interrupted register context.	208	* @param pstate Interrupted register context.
206	*/	209	*/
207	void tlb_modified(struct exception_regdump *pstate)	210	void tlb_modified(struct exception_regdump *pstate)
208	{	211	{
209	tlb_index_t index;	212	tlb_index_t index;
210	__address badvaddr;	213	__address badvaddr;
211	entry_lo_t lo;	214	entry_lo_t lo;
212	entry_hi_t hi;	215	entry_hi_t hi;
213	pte_t *pte;	216	pte_t *pte;
214		217
215	badvaddr = cp0_badvaddr_read();	218	badvaddr = cp0_badvaddr_read();
216		219
217	/*	220	/*
218	* Locate the faulting entry in TLB.	221	* Locate the faulting entry in TLB.
219	*/	222	*/
220	hi.value = cp0_entry_hi_read();	223	hi.value = cp0_entry_hi_read();
221	prepare_entry_hi(&hi, hi.asid, badvaddr);	224	prepare_entry_hi(&hi, hi.asid, badvaddr);
222	cp0_entry_hi_write(hi.value);	225	cp0_entry_hi_write(hi.value);
223	tlbp();	226	tlbp();
224	index.value = cp0_index_read();	227	index.value = cp0_index_read();
225		228
226	spinlock_lock(&AS->lock);	229	spinlock_lock(&AS->lock);
227		230
228	/*	231	/*
229	* Fail if the entry is not in TLB.	232	* Fail if the entry is not in TLB.
230	*/	233	*/
231	if (index.p) {	234	if (index.p) {
232	printf("TLB entry not found.\n");	235	printf("TLB entry not found.\n");
233	goto fail;	236	goto fail;
234	}	237	}
235		238
236	pte = find_mapping_and_check(badvaddr);	239	pte = find_mapping_and_check(badvaddr);
237	if (!pte)	240	if (!pte)
238	goto fail;	241	goto fail;
239		242
240	/*	243	/*
241	* Fail if the page is not writable.	244	* Fail if the page is not writable.
242	*/	245	*/
243	if (!pte->w)	246	if (!pte->w)
244	goto fail;	247	goto fail;
245		248
246	/*	249	/*
247	* Read the faulting TLB entry.	250	* Read the faulting TLB entry.
248	*/	251	*/
249	tlbr();	252	tlbr();
250		253
251	/*	254	/*
252	* Record access and write to PTE.	255	* Record access and write to PTE.
253	*/	256	*/
254	pte->a = 1;	257	pte->a = 1;
255	pte->lo.d = 1;	258	pte->lo.d = 1;
256		259
257	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);	260	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
258		261
259	/*	262	/*
260	* The entry is to be updated in TLB.	263	* The entry is to be updated in TLB.
261	*/	264	*/
262	if ((badvaddr/PAGE_SIZE) % 2 == 0)	265	if ((badvaddr/PAGE_SIZE) % 2 == 0)
263	cp0_entry_lo0_write(lo.value);	266	cp0_entry_lo0_write(lo.value);
264	else	267	else
265	cp0_entry_lo1_write(lo.value);	268	cp0_entry_lo1_write(lo.value);
266	cp0_pagemask_write(TLB_PAGE_MASK_16K);	269	cp0_pagemask_write(TLB_PAGE_MASK_16K);
267	tlbwi();	270	tlbwi();
268		271
269	spinlock_unlock(&AS->lock);	272	spinlock_unlock(&AS->lock);
270	return;	273	return;
271		274
272	fail:	275	fail:
273	spinlock_unlock(&AS->lock);	276	spinlock_unlock(&AS->lock);
274	tlb_modified_fail(pstate);	277	tlb_modified_fail(pstate);
275	}	278	}
276		279
277	void tlb_refill_fail(struct exception_regdump *pstate)	280	void tlb_refill_fail(struct exception_regdump *pstate)
278	{	281	{
279	char *symbol = "";	282	char *symbol = "";
280	char *sym2 = "";	283	char *sym2 = "";
281		284
282	char *s = get_symtab_entry(pstate->epc);	285	char *s = get_symtab_entry(pstate->epc);
283	if (s)	286	if (s)
284	symbol = s;	287	symbol = s;
285	s = get_symtab_entry(pstate->ra);	288	s = get_symtab_entry(pstate->ra);
286	if (s)	289	if (s)
287	sym2 = s;	290	sym2 = s;
288	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);	291	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);
289	}	292	}
290		293
291		294
292	void tlb_invalid_fail(struct exception_regdump *pstate)	295	void tlb_invalid_fail(struct exception_regdump *pstate)
293	{	296	{
294	char *symbol = "";	297	char *symbol = "";
295		298
296	char *s = get_symtab_entry(pstate->epc);	299	char *s = get_symtab_entry(pstate->epc);
297	if (s)	300	if (s)
298	symbol = s;	301	symbol = s;
299	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);	302	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
300	}	303	}
301		304
302	void tlb_modified_fail(struct exception_regdump *pstate)	305	void tlb_modified_fail(struct exception_regdump *pstate)
303	{	306	{
304	char *symbol = "";	307	char *symbol = "";
305		308
306	char *s = get_symtab_entry(pstate->epc);	309	char *s = get_symtab_entry(pstate->epc);
307	if (s)	310	if (s)
308	symbol = s;	311	symbol = s;
309	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);	312	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
310	}	313	}
311		314
312	/** Try to find PTE for faulting address	315	/** Try to find PTE for faulting address
313	*	316	*
314	* Try to find PTE for faulting address.	317	* Try to find PTE for faulting address.
315	* The AS->lock must be held on entry to this function.	318	* The AS->lock must be held on entry to this function.
316	*	319	*
317	* @param badvaddr Faulting virtual address.	320	* @param badvaddr Faulting virtual address.
318	*	321	*
319	* @return PTE on success, NULL otherwise.	322	* @return PTE on success, NULL otherwise.
320	*/	323	*/
321	pte_t *find_mapping_and_check(__address badvaddr)	324	pte_t *find_mapping_and_check(__address badvaddr)
322	{	325	{
323	entry_hi_t hi;	326	entry_hi_t hi;
324	pte_t *pte;	327	pte_t *pte;
325		328
326	hi.value = cp0_entry_hi_read();	329	hi.value = cp0_entry_hi_read();
327		330
328	/*	331	/*
329	* Handler cannot succeed if the ASIDs don't match.	332	* Handler cannot succeed if the ASIDs don't match.
330	*/	333	*/
331	if (hi.asid != AS->asid) {	334	if (hi.asid != AS->asid) {
332	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	335	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
333	return NULL;	336	return NULL;
334	}	337	}
335		338
336	/*	339	/*
337	* Check if the mapping exists in page tables.	340	* Check if the mapping exists in page tables.
338	*/	341	*/
339	pte = page_mapping_find(badvaddr, AS->asid, 0);	342	pte = page_mapping_find(badvaddr, AS->asid, 0);
340	if (pte && pte->lo.v) {	343	if (pte && pte->lo.v) {
341	/*	344	/*
342	* Mapping found in page tables.	345	* Mapping found in page tables.
343	* Immediately succeed.	346	* Immediately succeed.
344	*/	347	*/
345	return pte;	348	return pte;
346	} else {	349	} else {
347	/*	350	/*
348	* Mapping not found in page tables.	351	* Mapping not found in page tables.
349	* Resort to higher-level page fault handler.	352	* Resort to higher-level page fault handler.
350	*/	353	*/
351	if (as_page_fault(badvaddr)) {	354	if (as_page_fault(badvaddr)) {
352	/*	355	/*
353	* The higher-level page fault handler succeeded,	356	* The higher-level page fault handler succeeded,
354	* The mapping ought to be in place.	357	* The mapping ought to be in place.
355	*/	358	*/
356	pte = page_mapping_find(badvaddr, AS->asid, 0);	359	pte = page_mapping_find(badvaddr, AS->asid, 0);
357	ASSERT(pte && pte->lo.v);	360	ASSERT(pte && pte->lo.v);
358	return pte;	361	return pte;
359	}	362	}
360	}	363	}
361		364
362	/*	365	/*
363	* Handler cannot succeed if badvaddr has no mapping.	366	* Handler cannot succeed if badvaddr has no mapping.
364	*/	367	*/
365	if (!pte) {	368	if (!pte) {
366	printf("No such mapping.\n");	369	printf("No such mapping.\n");
367	return NULL;	370	return NULL;
368	}	371	}
369		372
370	/*	373	/*
371	* Handler cannot succeed if the mapping is marked as invalid.	374	* Handler cannot succeed if the mapping is marked as invalid.
372	*/	375	*/
373	if (!pte->lo.v) {	376	if (!pte->lo.v) {
374	printf("Invalid mapping.\n");	377	printf("Invalid mapping.\n");
375	return NULL;	378	return NULL;
376	}	379	}
377		380
378	return pte;	381	return pte;
379	}	382	}
380		383
381	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)	384	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
382	{	385	{
383	lo->value = 0;	386	lo->value = 0;
384	lo->g = g;	387	lo->g = g;
385	lo->v = v;	388	lo->v = v;
386	lo->d = d;	389	lo->d = d;
387	lo->c = c;	390	lo->c = c;
388	lo->pfn = pfn;	391	lo->pfn = pfn;
389	}	392	}
390		393
391	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)	394	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
392	{	395	{
393	hi->value = (((addr/PAGE_SIZE)/2)PAGE_SIZE2);	396	hi->value = (((addr/PAGE_SIZE)/2)PAGE_SIZE2);
394	hi->asid = asid;	397	hi->asid = asid;
395	}	398	}
396		399
397	/** Print contents of TLB. */	400	/** Print contents of TLB. */
398	void tlb_print(void)	401	void tlb_print(void)
399	{	402	{
400	page_mask_t mask;	403	page_mask_t mask;
401	entry_lo_t lo0, lo1;	404	entry_lo_t lo0, lo1;
402	entry_hi_t hi, hi_save;	405	entry_hi_t hi, hi_save;
403	int i;	406	int i;
404		407
405	hi_save.value = cp0_entry_hi_read();	408	hi_save.value = cp0_entry_hi_read();
406		409
407	printf("TLB:\n");	410	printf("TLB:\n");
408	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	411	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
409	cp0_index_write(i);	412	cp0_index_write(i);
410	tlbr();	413	tlbr();
411		414
412	mask.value = cp0_pagemask_read();	415	mask.value = cp0_pagemask_read();
413	hi.value = cp0_entry_hi_read();	416	hi.value = cp0_entry_hi_read();
414	lo0.value = cp0_entry_lo0_read();	417	lo0.value = cp0_entry_lo0_read();
415	lo1.value = cp0_entry_lo1_read();	418	lo1.value = cp0_entry_lo1_read();
416		419
417	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"	420	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"
418	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",	421	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",
419	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,	422	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
420	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	423	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
421	}	424	}
422		425
423	cp0_entry_hi_write(hi_save.value);	426	cp0_entry_hi_write(hi_save.value);
424	}	427	}
425		428
426	/** Invalidate all not wired TLB entries. */	429	/** Invalidate all not wired TLB entries. */
427	void tlb_invalidate_all(void)	430	void tlb_invalidate_all(void)
428	{	431	{
429	ipl_t ipl;	432	ipl_t ipl;
430	entry_lo_t lo0, lo1;	433	entry_lo_t lo0, lo1;
431	entry_hi_t hi_save;	434	entry_hi_t hi_save;
432	int i;	435	int i;
433		436
434	hi_save.value = cp0_entry_hi_read();	437	hi_save.value = cp0_entry_hi_read();
435	ipl = interrupts_disable();	438	ipl = interrupts_disable();
436		439
437	for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {	440	for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
438	cp0_index_write(i);	441	cp0_index_write(i);
439	tlbr();	442	tlbr();
440		443
441	lo0.value = cp0_entry_lo0_read();	444	lo0.value = cp0_entry_lo0_read();
442	lo1.value = cp0_entry_lo1_read();	445	lo1.value = cp0_entry_lo1_read();
443		446
444	lo0.v = 0;	447	lo0.v = 0;
445	lo1.v = 0;	448	lo1.v = 0;
446		449
447	cp0_entry_lo0_write(lo0.value);	450	cp0_entry_lo0_write(lo0.value);
448	cp0_entry_lo1_write(lo1.value);	451	cp0_entry_lo1_write(lo1.value);
449		452
450	tlbwi();	453	tlbwi();
451	}	454	}
452		455
453	interrupts_restore(ipl);	456	interrupts_restore(ipl);
454	cp0_entry_hi_write(hi_save.value);	457	cp0_entry_hi_write(hi_save.value);
455	}	458	}
456		459
457	/** Invalidate all TLB entries belonging to specified address space.	460	/** Invalidate all TLB entries belonging to specified address space.
458	*	461	*
459	* @param asid Address space identifier.	462	* @param asid Address space identifier.
460	*/	463	*/
461	void tlb_invalidate_asid(asid_t asid)	464	void tlb_invalidate_asid(asid_t asid)
462	{	465	{
463	ipl_t ipl;	466	ipl_t ipl;
464	entry_lo_t lo0, lo1;	467	entry_lo_t lo0, lo1;
465	entry_hi_t hi, hi_save;	468	entry_hi_t hi, hi_save;
466	int i;	469	int i;
467		470
468	ASSERT(asid != ASID_INVALID);	471	ASSERT(asid != ASID_INVALID);
469		472
470	hi_save.value = cp0_entry_hi_read();	473	hi_save.value = cp0_entry_hi_read();
471	ipl = interrupts_disable();	474	ipl = interrupts_disable();
472		475
473	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	476	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
474	cp0_index_write(i);	477	cp0_index_write(i);
475	tlbr();	478	tlbr();
476		479
477	hi.value = cp0_entry_hi_read();	480	hi.value = cp0_entry_hi_read();
478		481
479	if (hi.asid == asid) {	482	if (hi.asid == asid) {
480	lo0.value = cp0_entry_lo0_read();	483	lo0.value = cp0_entry_lo0_read();
481	lo1.value = cp0_entry_lo1_read();	484	lo1.value = cp0_entry_lo1_read();
482		485
483	lo0.v = 0;	486	lo0.v = 0;
484	lo1.v = 0;	487	lo1.v = 0;
485		488
486	cp0_entry_lo0_write(lo0.value);	489	cp0_entry_lo0_write(lo0.value);
487	cp0_entry_lo1_write(lo1.value);	490	cp0_entry_lo1_write(lo1.value);
488		491
489	tlbwi();	492	tlbwi();
490	}	493	}
491	}	494	}
492		495
493	interrupts_restore(ipl);	496	interrupts_restore(ipl);
494	cp0_entry_hi_write(hi_save.value);	497	cp0_entry_hi_write(hi_save.value);
495	}	498	}
496		499
497	/** Invalidate TLB entries for specified page range belonging to specified address space.	500	/** Invalidate TLB entries for specified page range belonging to specified address space.

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/mm/tlb.c @ 727 – Rev 727 → 730