WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/mm/tlb.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <arch/mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
 
static void tlb_refill_fail(struct exception_regdump *pstate);
static void tlb_invalid_fail(struct exception_regdump *pstate);
static void tlb_modified_fail(struct exception_regdump *pstate);
 
static pte_t *find_mapping_and_check(__address badvaddr);
 
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception
 *
 * Process TLB Refill Exception.
 *
 * @param pstate Interrupted register context.
 */
void tlb_refill(struct exception_regdump *pstate)
{
    entry_lo_t lo;
    entry_hi_t hi; 
    __address badvaddr;
    pte_t *pte;
 
    badvaddr = cp0_badvaddr_read();
 
    spinlock_lock(&AS->lock);      
 
    pte = find_mapping_and_check(badvaddr);
    if (!pte)
        goto fail;
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_hi(&hi, AS->asid, badvaddr);
    prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    spinlock_unlock(&AS->lock);
    return;
   
fail:
    spinlock_unlock(&AS->lock);
    tlb_refill_fail(pstate);
}
 
/** Process TLB Invalid Exception
 *
 * Process TLB Invalid Exception.
 *
 * @param pstate Interrupted register context.
 */
void tlb_invalid(struct exception_regdump *pstate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
   
    spinlock_lock(&AS->lock);  
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr);
    if (!pte)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    spinlock_unlock(&AS->lock);
    return;
   
fail:
    spinlock_unlock(&AS->lock);
    tlb_invalid_fail(pstate);
}
 
/** Process TLB Modified Exception
 *
 * Process TLB Modified Exception.
 *
 * @param pstate Interrupted register context.
 */
void tlb_modified(struct exception_regdump *pstate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
   
    spinlock_lock(&AS->lock);  
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr);
    if (!pte)
        goto fail;
 
    /*
     * Fail if the page is not writable.
     */
    if (!pte->w)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->lo.d = 1;
 
    prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    spinlock_unlock(&AS->lock);
    return;
   
fail:
    spinlock_unlock(&AS->lock);
    tlb_modified_fail(pstate);
}
 
void tlb_refill_fail(struct exception_regdump *pstate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(pstate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(pstate->ra);
    if (s)
        sym2 = s;
    panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(struct exception_regdump *pstate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(pstate->epc);
    if (s)
        symbol = s;
    panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
}
 
void tlb_modified_fail(struct exception_regdump *pstate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(pstate->epc);
    if (s)
        symbol = s;
    panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
}
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr Faulting virtual address.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(__address badvaddr)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(badvaddr, AS->asid, 0);
    if (pte && pte->lo.v) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        if (as_page_fault(badvaddr)) {
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            pte = page_mapping_find(badvaddr, AS->asid, 0);
            ASSERT(pte && pte->lo.v);
            return pte;
        }
    }
 
    /*
     * Handler cannot succeed if badvaddr has no mapping.
     */
    if (!pte) {
        printf("No such mapping.\n");
        return NULL;
    }
 
    /*
     * Handler cannot succeed if the mapping is marked as invalid.
     */
    if (!pte->lo.v) {
        printf("Invalid mapping.\n");
        return NULL;
    }
 
    return pte;
}
 
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = c;
    lo->pfn = pfn;
}
 
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
{
    hi->value = (((addr/PAGE_SIZE)/2)*PAGE_SIZE*2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
 
    printf("TLB:\n");
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"
               "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",
               i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
               lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entry for specified page belonging to specified address space.
 *
 * @param asid Address space identifier.
 * @param page Page whose TLB entry is to be invalidated.
 */
void tlb_invalidate_page(asid_t asid, __address page)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    hi.value = 0;
    prepare_entry_hi(&hi, asid, page);
    cp0_entry_hi_write(hi.value);
 
    tlbp();
    index.value = cp0_index_read();
 
    if (!index.p) {
        /* Entry was found, index register contains valid index. */
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
 
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 

Rev 703	Rev 704
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <arch/mm/asid.h>	30	#include <arch/mm/asid.h>
31	#include <mm/tlb.h>	31	#include <mm/tlb.h>
32	#include <mm/page.h>	32	#include <mm/page.h>
33	#include <mm/as.h>	33	#include <mm/as.h>
34	#include <arch/cp0.h>	34	#include <arch/cp0.h>
35	#include <panic.h>	35	#include <panic.h>
36	#include <arch.h>	36	#include <arch.h>
37	#include <symtab.h>	37	#include <symtab.h>
38	#include <synch/spinlock.h>	38	#include <synch/spinlock.h>
39	#include <print.h>	39	#include <print.h>
40	#include <debug.h>	40	#include <debug.h>
41		41
42	static void tlb_refill_fail(struct exception_regdump *pstate);	42	static void tlb_refill_fail(struct exception_regdump *pstate);
43	static void tlb_invalid_fail(struct exception_regdump *pstate);	43	static void tlb_invalid_fail(struct exception_regdump *pstate);
44	static void tlb_modified_fail(struct exception_regdump *pstate);	44	static void tlb_modified_fail(struct exception_regdump *pstate);
45		45
46	static pte_t *find_mapping_and_check(__address badvaddr);	46	static pte_t *find_mapping_and_check(__address badvaddr);
47		47
48	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);	48	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
49	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);	49	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
50		50
51	/** Initialize TLB	51	/** Initialize TLB
52	*	52	*
53	* Initialize TLB.	53	* Initialize TLB.
54	* Invalidate all entries and mark wired entries.	54	* Invalidate all entries and mark wired entries.
55	*/	55	*/
56	void tlb_arch_init(void)	56	void tlb_arch_init(void)
57	{	57	{
58	int i;	58	int i;
59		59
60	cp0_pagemask_write(TLB_PAGE_MASK_16K);	60	cp0_pagemask_write(TLB_PAGE_MASK_16K);
61	cp0_entry_hi_write(0);	61	cp0_entry_hi_write(0);
62	cp0_entry_lo0_write(0);	62	cp0_entry_lo0_write(0);
63	cp0_entry_lo1_write(0);	63	cp0_entry_lo1_write(0);
64		64
65	/* Clear and initialize TLB. */	65	/* Clear and initialize TLB. */
66		66
67	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	67	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
68	cp0_index_write(i);	68	cp0_index_write(i);
69	tlbwi();	69	tlbwi();
70	}	70	}
71		71
72		72
73	/*	73	/*
74	* The kernel is going to make use of some wired	74	* The kernel is going to make use of some wired
75	* entries (e.g. mapping kernel stacks in kseg3).	75	* entries (e.g. mapping kernel stacks in kseg3).
76	*/	76	*/
77	cp0_wired_write(TLB_WIRED);	77	cp0_wired_write(TLB_WIRED);
78	}	78	}
79		79
80	/** Process TLB Refill Exception	80	/** Process TLB Refill Exception
81	*	81	*
82	* Process TLB Refill Exception.	82	* Process TLB Refill Exception.
83	*	83	*
84	* @param pstate Interrupted register context.	84	* @param pstate Interrupted register context.
85	*/	85	*/
86	void tlb_refill(struct exception_regdump *pstate)	86	void tlb_refill(struct exception_regdump *pstate)
87	{	87	{
88	entry_lo_t lo;	88	entry_lo_t lo;
89	entry_hi_t hi;	89	entry_hi_t hi;
90	__address badvaddr;	90	__address badvaddr;
91	pte_t *pte;	91	pte_t *pte;
92		92
93	badvaddr = cp0_badvaddr_read();	93	badvaddr = cp0_badvaddr_read();
94		94
95	spinlock_lock(&AS->lock);	95	spinlock_lock(&AS->lock);
96		96
97	pte = find_mapping_and_check(badvaddr);	97	pte = find_mapping_and_check(badvaddr);
98	if (!pte)	98	if (!pte)
99	goto fail;	99	goto fail;
100		100
101	/*	101	/*
102	* Record access to PTE.	102	* Record access to PTE.
103	*/	103	*/
104	pte->a = 1;	104	pte->a = 1;
105		105
106	prepare_entry_hi(&hi, AS->asid, badvaddr);	106	prepare_entry_hi(&hi, AS->asid, badvaddr);
107	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);	107	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
108		108
109	/*	109	/*
110	* New entry is to be inserted into TLB	110	* New entry is to be inserted into TLB
111	*/	111	*/
112	cp0_entry_hi_write(hi.value);	112	cp0_entry_hi_write(hi.value);
113	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	113	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
114	cp0_entry_lo0_write(lo.value);	114	cp0_entry_lo0_write(lo.value);
115	cp0_entry_lo1_write(0);	115	cp0_entry_lo1_write(0);
116	}	116	}
117	else {	117	else {
118	cp0_entry_lo0_write(0);	118	cp0_entry_lo0_write(0);
119	cp0_entry_lo1_write(lo.value);	119	cp0_entry_lo1_write(lo.value);
120	}	120	}
121	cp0_pagemask_write(TLB_PAGE_MASK_16K);	121	cp0_pagemask_write(TLB_PAGE_MASK_16K);
122	tlbwr();	122	tlbwr();
123		123
124	spinlock_unlock(&AS->lock);	124	spinlock_unlock(&AS->lock);
125	return;	125	return;
126		126
127	fail:	127	fail:
128	spinlock_unlock(&AS->lock);	128	spinlock_unlock(&AS->lock);
129	tlb_refill_fail(pstate);	129	tlb_refill_fail(pstate);
130	}	130	}
131		131
132	/** Process TLB Invalid Exception	132	/** Process TLB Invalid Exception
133	*	133	*
134	* Process TLB Invalid Exception.	134	* Process TLB Invalid Exception.
135	*	135	*
136	* @param pstate Interrupted register context.	136	* @param pstate Interrupted register context.
137	*/	137	*/
138	void tlb_invalid(struct exception_regdump *pstate)	138	void tlb_invalid(struct exception_regdump *pstate)
139	{	139	{
140	tlb_index_t index;	140	tlb_index_t index;
141	__address badvaddr;	141	__address badvaddr;
142	entry_lo_t lo;	142	entry_lo_t lo;
143	entry_hi_t hi;	143	entry_hi_t hi;
144	pte_t *pte;	144	pte_t *pte;
145		145
146	badvaddr = cp0_badvaddr_read();	146	badvaddr = cp0_badvaddr_read();
147		147
148	/*	148	/*
149	* Locate the faulting entry in TLB.	149	* Locate the faulting entry in TLB.
150	*/	150	*/
151	hi.value = cp0_entry_hi_read();	151	hi.value = cp0_entry_hi_read();
152	prepare_entry_hi(&hi, hi.asid, badvaddr);	152	prepare_entry_hi(&hi, hi.asid, badvaddr);
153	cp0_entry_hi_write(hi.value);	153	cp0_entry_hi_write(hi.value);
154	tlbp();	154	tlbp();
155	index.value = cp0_index_read();	155	index.value = cp0_index_read();
156		156
157	spinlock_lock(&AS->lock);	157	spinlock_lock(&AS->lock);
158		158
159	/*	159	/*
160	* Fail if the entry is not in TLB.	160	* Fail if the entry is not in TLB.
161	*/	161	*/
162	if (index.p) {	162	if (index.p) {
163	printf("TLB entry not found.\n");	163	printf("TLB entry not found.\n");
164	goto fail;	164	goto fail;
165	}	165	}
166		166
167	pte = find_mapping_and_check(badvaddr);	167	pte = find_mapping_and_check(badvaddr);
168	if (!pte)	168	if (!pte)
169	goto fail;	169	goto fail;
170		170
171	/*	171	/*
172	* Read the faulting TLB entry.	172	* Read the faulting TLB entry.
173	*/	173	*/
174	tlbr();	174	tlbr();
175		175
176	/*	176	/*
177	* Record access to PTE.	177	* Record access to PTE.
178	*/	178	*/
179	pte->a = 1;	179	pte->a = 1;
180		180
181	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);	181	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn);
182		182
183	/*	183	/*
184	* The entry is to be updated in TLB.	184	* The entry is to be updated in TLB.
185	*/	185	*/
186	if ((badvaddr/PAGE_SIZE) % 2 == 0)	186	if ((badvaddr/PAGE_SIZE) % 2 == 0)
187	cp0_entry_lo0_write(lo.value);	187	cp0_entry_lo0_write(lo.value);
188	else	188	else
189	cp0_entry_lo1_write(lo.value);	189	cp0_entry_lo1_write(lo.value);
190	cp0_pagemask_write(TLB_PAGE_MASK_16K);	190	cp0_pagemask_write(TLB_PAGE_MASK_16K);
191	tlbwi();	191	tlbwi();
192		192
193	spinlock_unlock(&AS->lock);	193	spinlock_unlock(&AS->lock);
194	return;	194	return;
195		195
196	fail:	196	fail:
197	spinlock_unlock(&AS->lock);	197	spinlock_unlock(&AS->lock);
198	tlb_invalid_fail(pstate);	198	tlb_invalid_fail(pstate);
199	}	199	}
200		200
201	/** Process TLB Modified Exception	201	/** Process TLB Modified Exception
202	*	202	*
203	* Process TLB Modified Exception.	203	* Process TLB Modified Exception.
204	*	204	*
205	* @param pstate Interrupted register context.	205	* @param pstate Interrupted register context.
206	*/	206	*/
207	void tlb_modified(struct exception_regdump *pstate)	207	void tlb_modified(struct exception_regdump *pstate)
208	{	208	{
209	tlb_index_t index;	209	tlb_index_t index;
210	__address badvaddr;	210	__address badvaddr;
211	entry_lo_t lo;	211	entry_lo_t lo;
212	entry_hi_t hi;	212	entry_hi_t hi;
213	pte_t *pte;	213	pte_t *pte;
214		214
215	badvaddr = cp0_badvaddr_read();	215	badvaddr = cp0_badvaddr_read();
216		216
217	/*	217	/*
218	* Locate the faulting entry in TLB.	218	* Locate the faulting entry in TLB.
219	*/	219	*/
220	hi.value = cp0_entry_hi_read();	220	hi.value = cp0_entry_hi_read();
221	prepare_entry_hi(&hi, hi.asid, badvaddr);	221	prepare_entry_hi(&hi, hi.asid, badvaddr);
222	cp0_entry_hi_write(hi.value);	222	cp0_entry_hi_write(hi.value);
223	tlbp();	223	tlbp();
224	index.value = cp0_index_read();	224	index.value = cp0_index_read();
225		225
226	spinlock_lock(&AS->lock);	226	spinlock_lock(&AS->lock);
227		227
228	/*	228	/*
229	* Fail if the entry is not in TLB.	229	* Fail if the entry is not in TLB.
230	*/	230	*/
231	if (index.p) {	231	if (index.p) {
232	printf("TLB entry not found.\n");	232	printf("TLB entry not found.\n");
233	goto fail;	233	goto fail;
234	}	234	}
235		235
236	pte = find_mapping_and_check(badvaddr);	236	pte = find_mapping_and_check(badvaddr);
237	if (!pte)	237	if (!pte)
238	goto fail;	238	goto fail;
239		239
240	/*	240	/*
241	* Fail if the page is not writable.	241	* Fail if the page is not writable.
242	*/	242	*/
243	if (!pte->w)	243	if (!pte->w)
244	goto fail;	244	goto fail;
245		245
246	/*	246	/*
247	* Read the faulting TLB entry.	247	* Read the faulting TLB entry.
248	*/	248	*/
249	tlbr();	249	tlbr();
250		250
251	/*	251	/*
252	* Record access and write to PTE.	252	* Record access and write to PTE.
253	*/	253	*/
254	pte->a = 1;	254	pte->a = 1;
255	pte->lo.d = 1;	255	pte->lo.d = 1;
256		256
257	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);	257	prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn);
258		258
259	/*	259	/*
260	* The entry is to be updated in TLB.	260	* The entry is to be updated in TLB.
261	*/	261	*/
262	if ((badvaddr/PAGE_SIZE) % 2 == 0)	262	if ((badvaddr/PAGE_SIZE) % 2 == 0)
263	cp0_entry_lo0_write(lo.value);	263	cp0_entry_lo0_write(lo.value);
264	else	264	else
265	cp0_entry_lo1_write(lo.value);	265	cp0_entry_lo1_write(lo.value);
266	cp0_pagemask_write(TLB_PAGE_MASK_16K);	266	cp0_pagemask_write(TLB_PAGE_MASK_16K);
267	tlbwi();	267	tlbwi();
268		268
269	spinlock_unlock(&AS->lock);	269	spinlock_unlock(&AS->lock);
270	return;	270	return;
271		271
272	fail:	272	fail:
273	spinlock_unlock(&AS->lock);	273	spinlock_unlock(&AS->lock);
274	tlb_modified_fail(pstate);	274	tlb_modified_fail(pstate);
275	}	275	}
276		276
277	void tlb_refill_fail(struct exception_regdump *pstate)	277	void tlb_refill_fail(struct exception_regdump *pstate)
278	{	278	{
279	char *symbol = "";	279	char *symbol = "";
280	char *sym2 = "";	280	char *sym2 = "";
281		281
282	char *s = get_symtab_entry(pstate->epc);	282	char *s = get_symtab_entry(pstate->epc);
283	if (s)	283	if (s)
284	symbol = s;	284	symbol = s;
285	s = get_symtab_entry(pstate->ra);	285	s = get_symtab_entry(pstate->ra);
286	if (s)	286	if (s)
287	sym2 = s;	287	sym2 = s;
288	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);	288	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);
289	}	289	}
290		290
291		291
292	void tlb_invalid_fail(struct exception_regdump *pstate)	292	void tlb_invalid_fail(struct exception_regdump *pstate)
293	{	293	{
294	char *symbol = "";	294	char *symbol = "";
295		295
296	char *s = get_symtab_entry(pstate->epc);	296	char *s = get_symtab_entry(pstate->epc);
297	if (s)	297	if (s)
298	symbol = s;	298	symbol = s;
299	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);	299	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
300	}	300	}
301		301
302	void tlb_modified_fail(struct exception_regdump *pstate)	302	void tlb_modified_fail(struct exception_regdump *pstate)
303	{	303	{
304	char *symbol = "";	304	char *symbol = "";
305		305
306	char *s = get_symtab_entry(pstate->epc);	306	char *s = get_symtab_entry(pstate->epc);
307	if (s)	307	if (s)
308	symbol = s;	308	symbol = s;
309	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);	309	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
310	}	310	}
311		311
312	/** Try to find PTE for faulting address	312	/** Try to find PTE for faulting address
313	*	313	*
314	* Try to find PTE for faulting address.	314	* Try to find PTE for faulting address.
315	* The AS->lock must be held on entry to this function.	315	* The AS->lock must be held on entry to this function.
316	*	316	*
317	* @param badvaddr Faulting virtual address.	317	* @param badvaddr Faulting virtual address.
318	*	318	*
319	* @return PTE on success, NULL otherwise.	319	* @return PTE on success, NULL otherwise.
320	*/	320	*/
321	pte_t *find_mapping_and_check(__address badvaddr)	321	pte_t *find_mapping_and_check(__address badvaddr)
322	{	322	{
323	entry_hi_t hi;	323	entry_hi_t hi;
324	pte_t *pte;	324	pte_t *pte;
325		325
326	hi.value = cp0_entry_hi_read();	326	hi.value = cp0_entry_hi_read();
327		327
328	/*	328	/*
329	* Handler cannot succeed if the ASIDs don't match.	329	* Handler cannot succeed if the ASIDs don't match.
330	*/	330	*/
331	if (hi.asid != AS->asid) {	331	if (hi.asid != AS->asid) {
332	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	332	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
333	return NULL;	333	return NULL;
334	}	334	}
335		335
336	/*	336	/*
337	* Check if the mapping exists in page tables.	337	* Check if the mapping exists in page tables.
338	*/	338	*/
339	pte = page_mapping_find(badvaddr, AS->asid, 0);	339	pte = page_mapping_find(badvaddr, AS->asid, 0);
340	if (pte && pte->lo.v) {	340	if (pte && pte->lo.v) {
341	/*	341	/*
342	* Mapping found in page tables.	342	* Mapping found in page tables.
343	* Immediately succeed.	343	* Immediately succeed.
344	*/	344	*/
345	return pte;	345	return pte;
346	} else {	346	} else {
347	/*	347	/*
348	* Mapping not found in page tables.	348	* Mapping not found in page tables.
349	* Resort to higher-level page fault handler.	349	* Resort to higher-level page fault handler.
350	*/	350	*/
351	if (as_page_fault(badvaddr)) {	351	if (as_page_fault(badvaddr)) {
352	/*	352	/*
353	* The higher-level page fault handler succeeded,	353	* The higher-level page fault handler succeeded,
354	* The mapping ought to be in place.	354	* The mapping ought to be in place.
355	*/	355	*/
356	pte = page_mapping_find(badvaddr, AS->asid, 0);	356	pte = page_mapping_find(badvaddr, AS->asid, 0);
357	ASSERT(pte && pte->lo.v);	357	ASSERT(pte && pte->lo.v);
358	return pte;	358	return pte;
359	}	359	}
360	}	360	}
361		361
362	/*	362	/*
363	* Handler cannot succeed if badvaddr has no mapping.	363	* Handler cannot succeed if badvaddr has no mapping.
364	*/	364	*/
365	if (!pte) {	365	if (!pte) {
366	printf("No such mapping.\n");	366	printf("No such mapping.\n");
367	return NULL;	367	return NULL;
368	}	368	}
369		369
370	/*	370	/*
371	* Handler cannot succeed if the mapping is marked as invalid.	371	* Handler cannot succeed if the mapping is marked as invalid.
372	*/	372	*/
373	if (!pte->lo.v) {	373	if (!pte->lo.v) {
374	printf("Invalid mapping.\n");	374	printf("Invalid mapping.\n");
375	return NULL;	375	return NULL;
376	}	376	}
377		377
378	return pte;	378	return pte;
379	}	379	}
380		380
381	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)	381	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
382	{	382	{
383	lo->value = 0;	383	lo->value = 0;
384	lo->g = g;	384	lo->g = g;
385	lo->v = v;	385	lo->v = v;
386	lo->d = d;	386	lo->d = d;
387	lo->c = c;	387	lo->c = c;
388	lo->pfn = pfn;	388	lo->pfn = pfn;
389	}	389	}
390		390
391	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)	391	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
392	{	392	{
393	hi->value = (((addr/PAGE_SIZE)/2)PAGE_SIZE2);	393	hi->value = (((addr/PAGE_SIZE)/2)PAGE_SIZE2);
394	hi->asid = asid;	394	hi->asid = asid;
395	}	395	}
396		396
397	/** Print contents of TLB. */	397	/** Print contents of TLB. */
398	void tlb_print(void)	398	void tlb_print(void)
399	{	399	{
400	page_mask_t mask;	400	page_mask_t mask;
401	entry_lo_t lo0, lo1;	401	entry_lo_t lo0, lo1;
402	entry_hi_t hi;	402	entry_hi_t hi, hi_save;
403	int i;	403	int i;
404		404
-		405	hi_save.value = cp0_entry_hi_read();
-		406
405	printf("TLB:\n");	407	printf("TLB:\n");
406	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	408	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
407	cp0_index_write(i);	409	cp0_index_write(i);
408	tlbr();	410	tlbr();
409		411
410	mask.value = cp0_pagemask_read();	412	mask.value = cp0_pagemask_read();
411	hi.value = cp0_entry_hi_read();	413	hi.value = cp0_entry_hi_read();
412	lo0.value = cp0_entry_lo0_read();	414	lo0.value = cp0_entry_lo0_read();
413	lo1.value = cp0_entry_lo1_read();	415	lo1.value = cp0_entry_lo1_read();
414		416
415	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"	417	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n"
416	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",	418	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n",
417	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,	419	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
418	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	420	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
419	}	421	}
-		422
-		423	cp0_entry_hi_write(hi_save.value);
420	}	424	}
421		425
422	/** Invalidate all not wired TLB entries. */	426	/** Invalidate all not wired TLB entries. */
423	void tlb_invalidate_all(void)	427	void tlb_invalidate_all(void)
424	{	428	{
425	ipl_t ipl;	429	ipl_t ipl;
426	entry_lo_t lo0, lo1;	430	entry_lo_t lo0, lo1;
-		431	entry_hi_t hi_save;
427	int i;	432	int i;
428		433
-		434	hi_save.value = cp0_entry_hi_read();
429	ipl = interrupts_disable();	435	ipl = interrupts_disable();
430		436
431	for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {	437	for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
432	cp0_index_write(i);	438	cp0_index_write(i);
433	tlbr();	439	tlbr();
434		440
435	lo0.value = cp0_entry_lo0_read();	441	lo0.value = cp0_entry_lo0_read();
436	lo1.value = cp0_entry_lo1_read();	442	lo1.value = cp0_entry_lo1_read();
437		443
438	lo0.v = 0;	444	lo0.v = 0;
439	lo1.v = 0;	445	lo1.v = 0;
440		446
441	cp0_entry_lo0_write(lo0.value);	447	cp0_entry_lo0_write(lo0.value);
442	cp0_entry_lo1_write(lo1.value);	448	cp0_entry_lo1_write(lo1.value);
443		449
444	tlbwi();	450	tlbwi();
445	}	451	}
446		452
447	interrupts_restore(ipl);	453	interrupts_restore(ipl);
-		454	cp0_entry_hi_write(hi_save.value);
448	}	455	}
449		456
450	/** Invalidate all TLB entries belonging to specified address space.	457	/** Invalidate all TLB entries belonging to specified address space.
451	*	458	*
452	* @param asid Address space identifier.	459	* @param asid Address space identifier.
453	*/	460	*/
454	void tlb_invalidate_asid(asid_t asid)	461	void tlb_invalidate_asid(asid_t asid)
455	{	462	{
456	ipl_t ipl;	463	ipl_t ipl;
457	entry_lo_t lo0, lo1;	464	entry_lo_t lo0, lo1;
458	entry_hi_t hi;	465	entry_hi_t hi, hi_save;
459	int i;	466	int i;
460		467
461	ASSERT(asid != ASID_INVALID);	468	ASSERT(asid != ASID_INVALID);
462		469
-		470	hi_save.value = cp0_entry_hi_read();
463	ipl = interrupts_disable();	471	ipl = interrupts_disable();
464		472
465	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	473	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
466	cp0_index_write(i);	474	cp0_index_write(i);
467	tlbr();	475	tlbr();
468		476
469	hi.value = cp0_entry_hi_read();	477	hi.value = cp0_entry_hi_read();
470		478
471	if (hi.asid == asid) {	479	if (hi.asid == asid) {
472	lo0.value = cp0_entry_lo0_read();	480	lo0.value = cp0_entry_lo0_read();
473	lo1.value = cp0_entry_lo1_read();	481	lo1.value = cp0_entry_lo1_read();
474		482
475	lo0.v = 0;	483	lo0.v = 0;
476	lo1.v = 0;	484	lo1.v = 0;
477		485
478	cp0_entry_lo0_write(lo0.value);	486	cp0_entry_lo0_write(lo0.value);
479	cp0_entry_lo1_write(lo1.value);	487	cp0_entry_lo1_write(lo1.value);
480		488
481	tlbwi();	489	tlbwi();
482	}	490	}
483	}	491	}
484		492
485	interrupts_restore(ipl);	493	interrupts_restore(ipl);
-		494	cp0_entry_hi_write(hi_save.value);
486	}	495	}
487		496
488	/** Invalidate TLB entry for specified page belonging to specified address space.	497	/** Invalidate TLB entry for specified page belonging to specified address space.
489	*	498	*
490	* @param asid Address space identifier.	499	* @param asid Address space identifier.
491	* @param page Page whose TLB entry is to be invalidated.	500	* @param page Page whose TLB entry is to be invalidated.

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/mm/tlb.c – Rev 703 → 704