WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/mm/tlb.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
#include <align.h>
 
static void tlb_refill_fail(istate_t *istate);
static void tlb_invalid_fail(istate_t *istate);
static void tlb_modified_fail(istate_t *istate);
 
static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc);
 
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception
 *
 * Process TLB Refill Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    __address badvaddr;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    spinlock_lock(&AS->lock);
    asid = AS->asid;
    spinlock_unlock(&AS->lock);
 
    page_table_lock(AS, true);
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_hi(&hi, asid, badvaddr);
    prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_refill_fail(istate);
}
 
/** Process TLB Invalid Exception
 *
 * Process TLB Invalid Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_invalid_fail(istate);
}
 
/** Process TLB Modified Exception
 *
 * Process TLB Modified Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    __address badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Fail if the page is not writable.
     */
    if (!pte->w)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->d = 1;
 
    prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_modified_fail(istate);
}
 
void tlb_refill_fail(istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->ra);
    if (s)
        sym2 = s;
    panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
void tlb_modified_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr Faulting virtual address.
 * @param access Access mode that caused the fault.
 * @param istate Pointer to interrupted state.
 * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(AS, badvaddr);
    if (pte && pte->p) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
       
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(AS, true);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(AS, true);
            pte = page_mapping_find(AS, badvaddr);
            ASSERT(pte && pte->p);
            return pte;
            break;
        case AS_PF_DEFER:
            page_table_lock(AS, true);
            *pfrc = AS_PF_DEFER;
            return NULL;
            break;
        case AS_PF_FAULT:
            page_table_lock(AS, true);
            printf("Page fault.\n");
            *pfrc = AS_PF_FAULT;
            return NULL;
            break;
        default:
            panic("unexpected rc (%d)\n", rc);
        }
       
    }
}
 
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
 
    printf("TLB:\n");
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
               "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
               i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
               lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified address space.
 *
 * @param asid Address space identifier.
 * @param page First page whose TLB entry is to be invalidated.
 * @param cnt Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
    int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt+1; i+=2) {
        hi.value = 0;
        prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /* Entry was found, index register contains valid index. */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 

Rev 1288	Rev 1411
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/mm/tlb.h>	29	#include <arch/mm/tlb.h>
30	#include <mm/asid.h>	30	#include <mm/asid.h>
31	#include <mm/tlb.h>	31	#include <mm/tlb.h>
32	#include <mm/page.h>	32	#include <mm/page.h>
33	#include <mm/as.h>	33	#include <mm/as.h>
34	#include <arch/cp0.h>	34	#include <arch/cp0.h>
35	#include <panic.h>	35	#include <panic.h>
36	#include <arch.h>	36	#include <arch.h>
37	#include <symtab.h>	37	#include <symtab.h>
38	#include <synch/spinlock.h>	38	#include <synch/spinlock.h>
39	#include <print.h>	39	#include <print.h>
40	#include <debug.h>	40	#include <debug.h>
41	#include <align.h>	41	#include <align.h>
42		42
43	static void tlb_refill_fail(istate_t *istate);	43	static void tlb_refill_fail(istate_t *istate);
44	static void tlb_invalid_fail(istate_t *istate);	44	static void tlb_invalid_fail(istate_t *istate);
45	static void tlb_modified_fail(istate_t *istate);	45	static void tlb_modified_fail(istate_t *istate);
46		46
47	static pte_t find_mapping_and_check(__address badvaddr, istate_t istate, int *pfrc);	47	static pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc);
48		48
49	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);	49	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
50	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);	50	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
51		51
52	/** Initialize TLB	52	/** Initialize TLB
53	*	53	*
54	* Initialize TLB.	54	* Initialize TLB.
55	* Invalidate all entries and mark wired entries.	55	* Invalidate all entries and mark wired entries.
56	*/	56	*/
57	void tlb_arch_init(void)	57	void tlb_arch_init(void)
58	{	58	{
59	int i;	59	int i;
60		60
61	cp0_pagemask_write(TLB_PAGE_MASK_16K);	61	cp0_pagemask_write(TLB_PAGE_MASK_16K);
62	cp0_entry_hi_write(0);	62	cp0_entry_hi_write(0);
63	cp0_entry_lo0_write(0);	63	cp0_entry_lo0_write(0);
64	cp0_entry_lo1_write(0);	64	cp0_entry_lo1_write(0);
65		65
66	/* Clear and initialize TLB. */	66	/* Clear and initialize TLB. */
67		67
68	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	68	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
69	cp0_index_write(i);	69	cp0_index_write(i);
70	tlbwi();	70	tlbwi();
71	}	71	}
72		72
73		73
74	/*	74	/*
75	* The kernel is going to make use of some wired	75	* The kernel is going to make use of some wired
76	* entries (e.g. mapping kernel stacks in kseg3).	76	* entries (e.g. mapping kernel stacks in kseg3).
77	*/	77	*/
78	cp0_wired_write(TLB_WIRED);	78	cp0_wired_write(TLB_WIRED);
79	}	79	}
80		80
81	/** Process TLB Refill Exception	81	/** Process TLB Refill Exception
82	*	82	*
83	* Process TLB Refill Exception.	83	* Process TLB Refill Exception.
84	*	84	*
85	* @param istate Interrupted register context.	85	* @param istate Interrupted register context.
86	*/	86	*/
87	void tlb_refill(istate_t *istate)	87	void tlb_refill(istate_t *istate)
88	{	88	{
89	entry_lo_t lo;	89	entry_lo_t lo;
90	entry_hi_t hi;	90	entry_hi_t hi;
91	asid_t asid;	91	asid_t asid;
92	__address badvaddr;	92	__address badvaddr;
93	pte_t *pte;	93	pte_t *pte;
94	int pfrc;	94	int pfrc;
95		95
96	badvaddr = cp0_badvaddr_read();	96	badvaddr = cp0_badvaddr_read();
97		97
98	spinlock_lock(&AS->lock);	98	spinlock_lock(&AS->lock);
99	asid = AS->asid;	99	asid = AS->asid;
100	spinlock_unlock(&AS->lock);	100	spinlock_unlock(&AS->lock);
101		101
102	page_table_lock(AS, true);	102	page_table_lock(AS, true);
103		103
104	pte = find_mapping_and_check(badvaddr, istate, &pfrc);	104	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
105	if (!pte) {	105	if (!pte) {
106	switch (pfrc) {	106	switch (pfrc) {
107	case AS_PF_FAULT:	107	case AS_PF_FAULT:
108	goto fail;	108	goto fail;
109	break;	109	break;
110	case AS_PF_DEFER:	110	case AS_PF_DEFER:
111	/*	111	/*
112	* The page fault came during copy_from_uspace()	112	* The page fault came during copy_from_uspace()
113	* or copy_to_uspace().	113	* or copy_to_uspace().
114	*/	114	*/
115	page_table_unlock(AS, true);	115	page_table_unlock(AS, true);
116	return;	116	return;
117	default:	117	default:
118	panic("unexpected pfrc (%d)\n", pfrc);	118	panic("unexpected pfrc (%d)\n", pfrc);
119	}	119	}
120	}	120	}
121		121
122	/*	122	/*
123	* Record access to PTE.	123	* Record access to PTE.
124	*/	124	*/
125	pte->a = 1;	125	pte->a = 1;
126		126
127	prepare_entry_hi(&hi, asid, badvaddr);	127	prepare_entry_hi(&hi, asid, badvaddr);
128	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	128	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
129		129
130	/*	130	/*
131	* New entry is to be inserted into TLB	131	* New entry is to be inserted into TLB
132	*/	132	*/
133	cp0_entry_hi_write(hi.value);	133	cp0_entry_hi_write(hi.value);
134	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	134	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
135	cp0_entry_lo0_write(lo.value);	135	cp0_entry_lo0_write(lo.value);
136	cp0_entry_lo1_write(0);	136	cp0_entry_lo1_write(0);
137	}	137	}
138	else {	138	else {
139	cp0_entry_lo0_write(0);	139	cp0_entry_lo0_write(0);
140	cp0_entry_lo1_write(lo.value);	140	cp0_entry_lo1_write(lo.value);
141	}	141	}
142	cp0_pagemask_write(TLB_PAGE_MASK_16K);	142	cp0_pagemask_write(TLB_PAGE_MASK_16K);
143	tlbwr();	143	tlbwr();
144		144
145	page_table_unlock(AS, true);	145	page_table_unlock(AS, true);
146	return;	146	return;
147		147
148	fail:	148	fail:
149	page_table_unlock(AS, true);	149	page_table_unlock(AS, true);
150	tlb_refill_fail(istate);	150	tlb_refill_fail(istate);
151	}	151	}
152		152
153	/** Process TLB Invalid Exception	153	/** Process TLB Invalid Exception
154	*	154	*
155	* Process TLB Invalid Exception.	155	* Process TLB Invalid Exception.
156	*	156	*
157	* @param istate Interrupted register context.	157	* @param istate Interrupted register context.
158	*/	158	*/
159	void tlb_invalid(istate_t *istate)	159	void tlb_invalid(istate_t *istate)
160	{	160	{
161	tlb_index_t index;	161	tlb_index_t index;
162	__address badvaddr;	162	__address badvaddr;
163	entry_lo_t lo;	163	entry_lo_t lo;
164	entry_hi_t hi;	164	entry_hi_t hi;
165	pte_t *pte;	165	pte_t *pte;
166	int pfrc;	166	int pfrc;
167		167
168	badvaddr = cp0_badvaddr_read();	168	badvaddr = cp0_badvaddr_read();
169		169
170	/*	170	/*
171	* Locate the faulting entry in TLB.	171	* Locate the faulting entry in TLB.
172	*/	172	*/
173	hi.value = cp0_entry_hi_read();	173	hi.value = cp0_entry_hi_read();
174	prepare_entry_hi(&hi, hi.asid, badvaddr);	174	prepare_entry_hi(&hi, hi.asid, badvaddr);
175	cp0_entry_hi_write(hi.value);	175	cp0_entry_hi_write(hi.value);
176	tlbp();	176	tlbp();
177	index.value = cp0_index_read();	177	index.value = cp0_index_read();
178		178
179	page_table_lock(AS, true);	179	page_table_lock(AS, true);
180		180
181	/*	181	/*
182	* Fail if the entry is not in TLB.	182	* Fail if the entry is not in TLB.
183	*/	183	*/
184	if (index.p) {	184	if (index.p) {
185	printf("TLB entry not found.\n");	185	printf("TLB entry not found.\n");
186	goto fail;	186	goto fail;
187	}	187	}
188		188
189	pte = find_mapping_and_check(badvaddr, istate, &pfrc);	189	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
190	if (!pte) {	190	if (!pte) {
191	switch (pfrc) {	191	switch (pfrc) {
192	case AS_PF_FAULT:	192	case AS_PF_FAULT:
193	goto fail;	193	goto fail;
194	break;	194	break;
195	case AS_PF_DEFER:	195	case AS_PF_DEFER:
196	/*	196	/*
197	* The page fault came during copy_from_uspace()	197	* The page fault came during copy_from_uspace()
198	* or copy_to_uspace().	198	* or copy_to_uspace().
199	*/	199	*/
200	page_table_unlock(AS, true);	200	page_table_unlock(AS, true);
201	return;	201	return;
202	default:	202	default:
203	panic("unexpected pfrc (%d)\n", pfrc);	203	panic("unexpected pfrc (%d)\n", pfrc);
204	}	204	}
205	}	205	}
206		206
207	/*	207	/*
208	* Read the faulting TLB entry.	208	* Read the faulting TLB entry.
209	*/	209	*/
210	tlbr();	210	tlbr();
211		211
212	/*	212	/*
213	* Record access to PTE.	213	* Record access to PTE.
214	*/	214	*/
215	pte->a = 1;	215	pte->a = 1;
216		216
217	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	217	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
218		218
219	/*	219	/*
220	* The entry is to be updated in TLB.	220	* The entry is to be updated in TLB.
221	*/	221	*/
222	if ((badvaddr/PAGE_SIZE) % 2 == 0)	222	if ((badvaddr/PAGE_SIZE) % 2 == 0)
223	cp0_entry_lo0_write(lo.value);	223	cp0_entry_lo0_write(lo.value);
224	else	224	else
225	cp0_entry_lo1_write(lo.value);	225	cp0_entry_lo1_write(lo.value);
226	cp0_pagemask_write(TLB_PAGE_MASK_16K);	226	cp0_pagemask_write(TLB_PAGE_MASK_16K);
227	tlbwi();	227	tlbwi();
228		228
229	page_table_unlock(AS, true);	229	page_table_unlock(AS, true);
230	return;	230	return;
231		231
232	fail:	232	fail:
233	page_table_unlock(AS, true);	233	page_table_unlock(AS, true);
234	tlb_invalid_fail(istate);	234	tlb_invalid_fail(istate);
235	}	235	}
236		236
237	/** Process TLB Modified Exception	237	/** Process TLB Modified Exception
238	*	238	*
239	* Process TLB Modified Exception.	239	* Process TLB Modified Exception.
240	*	240	*
241	* @param istate Interrupted register context.	241	* @param istate Interrupted register context.
242	*/	242	*/
243	void tlb_modified(istate_t *istate)	243	void tlb_modified(istate_t *istate)
244	{	244	{
245	tlb_index_t index;	245	tlb_index_t index;
246	__address badvaddr;	246	__address badvaddr;
247	entry_lo_t lo;	247	entry_lo_t lo;
248	entry_hi_t hi;	248	entry_hi_t hi;
249	pte_t *pte;	249	pte_t *pte;
250	int pfrc;	250	int pfrc;
251		251
252	badvaddr = cp0_badvaddr_read();	252	badvaddr = cp0_badvaddr_read();
253		253
254	/*	254	/*
255	* Locate the faulting entry in TLB.	255	* Locate the faulting entry in TLB.
256	*/	256	*/
257	hi.value = cp0_entry_hi_read();	257	hi.value = cp0_entry_hi_read();
258	prepare_entry_hi(&hi, hi.asid, badvaddr);	258	prepare_entry_hi(&hi, hi.asid, badvaddr);
259	cp0_entry_hi_write(hi.value);	259	cp0_entry_hi_write(hi.value);
260	tlbp();	260	tlbp();
261	index.value = cp0_index_read();	261	index.value = cp0_index_read();
262		262
263	page_table_lock(AS, true);	263	page_table_lock(AS, true);
264		264
265	/*	265	/*
266	* Fail if the entry is not in TLB.	266	* Fail if the entry is not in TLB.
267	*/	267	*/
268	if (index.p) {	268	if (index.p) {
269	printf("TLB entry not found.\n");	269	printf("TLB entry not found.\n");
270	goto fail;	270	goto fail;
271	}	271	}
272		272
273	pte = find_mapping_and_check(badvaddr, istate, &pfrc);	273	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
274	if (!pte) {	274	if (!pte) {
275	switch (pfrc) {	275	switch (pfrc) {
276	case AS_PF_FAULT:	276	case AS_PF_FAULT:
277	goto fail;	277	goto fail;
278	break;	278	break;
279	case AS_PF_DEFER:	279	case AS_PF_DEFER:
280	/*	280	/*
281	* The page fault came during copy_from_uspace()	281	* The page fault came during copy_from_uspace()
282	* or copy_to_uspace().	282	* or copy_to_uspace().
283	*/	283	*/
284	page_table_unlock(AS, true);	284	page_table_unlock(AS, true);
285	return;	285	return;
286	default:	286	default:
287	panic("unexpected pfrc (%d)\n", pfrc);	287	panic("unexpected pfrc (%d)\n", pfrc);
288	}	288	}
289	}	289	}
290		290
291	/*	291	/*
292	* Fail if the page is not writable.	292	* Fail if the page is not writable.
293	*/	293	*/
294	if (!pte->w)	294	if (!pte->w)
295	goto fail;	295	goto fail;
296		296
297	/*	297	/*
298	* Read the faulting TLB entry.	298	* Read the faulting TLB entry.
299	*/	299	*/
300	tlbr();	300	tlbr();
301		301
302	/*	302	/*
303	* Record access and write to PTE.	303	* Record access and write to PTE.
304	*/	304	*/
305	pte->a = 1;	305	pte->a = 1;
306	pte->d = 1;	306	pte->d = 1;
307		307
308	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);	308	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
309		309
310	/*	310	/*
311	* The entry is to be updated in TLB.	311	* The entry is to be updated in TLB.
312	*/	312	*/
313	if ((badvaddr/PAGE_SIZE) % 2 == 0)	313	if ((badvaddr/PAGE_SIZE) % 2 == 0)
314	cp0_entry_lo0_write(lo.value);	314	cp0_entry_lo0_write(lo.value);
315	else	315	else
316	cp0_entry_lo1_write(lo.value);	316	cp0_entry_lo1_write(lo.value);
317	cp0_pagemask_write(TLB_PAGE_MASK_16K);	317	cp0_pagemask_write(TLB_PAGE_MASK_16K);
318	tlbwi();	318	tlbwi();
319		319
320	page_table_unlock(AS, true);	320	page_table_unlock(AS, true);
321	return;	321	return;
322		322
323	fail:	323	fail:
324	page_table_unlock(AS, true);	324	page_table_unlock(AS, true);
325	tlb_modified_fail(istate);	325	tlb_modified_fail(istate);
326	}	326	}
327		327
328	void tlb_refill_fail(istate_t *istate)	328	void tlb_refill_fail(istate_t *istate)
329	{	329	{
330	char *symbol = "";	330	char *symbol = "";
331	char *sym2 = "";	331	char *sym2 = "";
332		332
333	char *s = get_symtab_entry(istate->epc);	333	char *s = get_symtab_entry(istate->epc);
334	if (s)	334	if (s)
335	symbol = s;	335	symbol = s;
336	s = get_symtab_entry(istate->ra);	336	s = get_symtab_entry(istate->ra);
337	if (s)	337	if (s)
338	sym2 = s;	338	sym2 = s;
339	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);	339	panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
340	}	340	}
341		341
342		342
343	void tlb_invalid_fail(istate_t *istate)	343	void tlb_invalid_fail(istate_t *istate)
344	{	344	{
345	char *symbol = "";	345	char *symbol = "";
346		346
347	char *s = get_symtab_entry(istate->epc);	347	char *s = get_symtab_entry(istate->epc);
348	if (s)	348	if (s)
349	symbol = s;	349	symbol = s;
350	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	350	panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
351	}	351	}
352		352
353	void tlb_modified_fail(istate_t *istate)	353	void tlb_modified_fail(istate_t *istate)
354	{	354	{
355	char *symbol = "";	355	char *symbol = "";
356		356
357	char *s = get_symtab_entry(istate->epc);	357	char *s = get_symtab_entry(istate->epc);
358	if (s)	358	if (s)
359	symbol = s;	359	symbol = s;
360	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	360	panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
361	}	361	}
362		362
363	/** Try to find PTE for faulting address	363	/** Try to find PTE for faulting address
364	*	364	*
365	* Try to find PTE for faulting address.	365	* Try to find PTE for faulting address.
366	* The AS->lock must be held on entry to this function.	366	* The AS->lock must be held on entry to this function.
367	*	367	*
368	* @param badvaddr Faulting virtual address.	368	* @param badvaddr Faulting virtual address.
-		369	* @param access Access mode that caused the fault.
369	* @param istate Pointer to interrupted state.	370	* @param istate Pointer to interrupted state.
370	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	371	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
371	*	372	*
372	* @return PTE on success, NULL otherwise.	373	* @return PTE on success, NULL otherwise.
373	*/	374	*/
374	pte_t find_mapping_and_check(__address badvaddr, istate_t istate, int *pfrc)	375	pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc)
375	{	376	{
376	entry_hi_t hi;	377	entry_hi_t hi;
377	pte_t *pte;	378	pte_t *pte;
378		379
379	hi.value = cp0_entry_hi_read();	380	hi.value = cp0_entry_hi_read();
380		381
381	/*	382	/*
382	* Handler cannot succeed if the ASIDs don't match.	383	* Handler cannot succeed if the ASIDs don't match.
383	*/	384	*/
384	if (hi.asid != AS->asid) {	385	if (hi.asid != AS->asid) {
385	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	386	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
386	return NULL;	387	return NULL;
387	}	388	}
388		389
389	/*	390	/*
390	* Check if the mapping exists in page tables.	391	* Check if the mapping exists in page tables.
391	*/	392	*/
392	pte = page_mapping_find(AS, badvaddr);	393	pte = page_mapping_find(AS, badvaddr);
393	if (pte && pte->p) {	394	if (pte && pte->p) {
394	/*	395	/*
395	* Mapping found in page tables.	396	* Mapping found in page tables.
396	* Immediately succeed.	397	* Immediately succeed.
397	*/	398	*/
398	return pte;	399	return pte;
399	} else {	400	} else {
400	int rc;	401	int rc;
401		402
402	/*	403	/*
403	* Mapping not found in page tables.	404	* Mapping not found in page tables.
404	* Resort to higher-level page fault handler.	405	* Resort to higher-level page fault handler.
405	*/	406	*/
406	page_table_unlock(AS, true);	407	page_table_unlock(AS, true);
407	switch (rc = as_page_fault(badvaddr, istate)) {	408	switch (rc = as_page_fault(badvaddr, access, istate)) {
408	case AS_PF_OK:	409	case AS_PF_OK:
409	/*	410	/*
410	* The higher-level page fault handler succeeded,	411	* The higher-level page fault handler succeeded,
411	* The mapping ought to be in place.	412	* The mapping ought to be in place.
412	*/	413	*/
413	page_table_lock(AS, true);	414	page_table_lock(AS, true);
414	pte = page_mapping_find(AS, badvaddr);	415	pte = page_mapping_find(AS, badvaddr);
415	ASSERT(pte && pte->p);	416	ASSERT(pte && pte->p);
416	return pte;	417	return pte;
417	break;	418	break;
418	case AS_PF_DEFER:	419	case AS_PF_DEFER:
419	page_table_lock(AS, true);	420	page_table_lock(AS, true);
420	*pfrc = AS_PF_DEFER;	421	*pfrc = AS_PF_DEFER;
421	return NULL;	422	return NULL;
422	break;	423	break;
423	case AS_PF_FAULT:	424	case AS_PF_FAULT:
424	page_table_lock(AS, true);	425	page_table_lock(AS, true);
425	printf("Page fault.\n");	426	printf("Page fault.\n");
426	*pfrc = AS_PF_FAULT;	427	*pfrc = AS_PF_FAULT;
427	return NULL;	428	return NULL;
428	break;	429	break;
429	default:	430	default:
430	panic("unexpected rc (%d)\n", rc);	431	panic("unexpected rc (%d)\n", rc);
431	}	432	}
432		433
433	}	434	}
434	}	435	}
435		436
436	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)	437	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
437	{	438	{
438	lo->value = 0;	439	lo->value = 0;
439	lo->g = g;	440	lo->g = g;
440	lo->v = v;	441	lo->v = v;
441	lo->d = d;	442	lo->d = d;
442	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	443	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
443	lo->pfn = pfn;	444	lo->pfn = pfn;
444	}	445	}
445		446
446	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)	447	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
447	{	448	{
448	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	449	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
449	hi->asid = asid;	450	hi->asid = asid;
450	}	451	}
451		452
452	/** Print contents of TLB. */	453	/** Print contents of TLB. */
453	void tlb_print(void)	454	void tlb_print(void)
454	{	455	{
455	page_mask_t mask;	456	page_mask_t mask;
456	entry_lo_t lo0, lo1;	457	entry_lo_t lo0, lo1;
457	entry_hi_t hi, hi_save;	458	entry_hi_t hi, hi_save;
458	int i;	459	int i;
459		460
460	hi_save.value = cp0_entry_hi_read();	461	hi_save.value = cp0_entry_hi_read();
461		462
462	printf("TLB:\n");	463	printf("TLB:\n");
463	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	464	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
464	cp0_index_write(i);	465	cp0_index_write(i);
465	tlbr();	466	tlbr();
466		467
467	mask.value = cp0_pagemask_read();	468	mask.value = cp0_pagemask_read();
468	hi.value = cp0_entry_hi_read();	469	hi.value = cp0_entry_hi_read();
469	lo0.value = cp0_entry_lo0_read();	470	lo0.value = cp0_entry_lo0_read();
470	lo1.value = cp0_entry_lo1_read();	471	lo1.value = cp0_entry_lo1_read();
471		472
472	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"	473	printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
473	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",	474	"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
474	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,	475	i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
475	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	476	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
476	}	477	}
477		478
478	cp0_entry_hi_write(hi_save.value);	479	cp0_entry_hi_write(hi_save.value);
479	}	480	}
480		481
481	/** Invalidate all not wired TLB entries. */	482	/** Invalidate all not wired TLB entries. */
482	void tlb_invalidate_all(void)	483	void tlb_invalidate_all(void)
483	{	484	{
484	ipl_t ipl;	485	ipl_t ipl;
485	entry_lo_t lo0, lo1;	486	entry_lo_t lo0, lo1;
486	entry_hi_t hi_save;	487	entry_hi_t hi_save;
487	int i;	488	int i;
488		489
489	hi_save.value = cp0_entry_hi_read();	490	hi_save.value = cp0_entry_hi_read();
490	ipl = interrupts_disable();	491	ipl = interrupts_disable();
491		492
492	for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {	493	for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
493	cp0_index_write(i);	494	cp0_index_write(i);
494	tlbr();	495	tlbr();
495		496
496	lo0.value = cp0_entry_lo0_read();	497	lo0.value = cp0_entry_lo0_read();
497	lo1.value = cp0_entry_lo1_read();	498	lo1.value = cp0_entry_lo1_read();
498		499
499	lo0.v = 0;	500	lo0.v = 0;

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/mm/tlb.c @ 1780 – Rev 1288 → 1411