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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch.h> |
29 | #include <arch.h> |
30 | #include <arch/cp0.h> |
30 | #include <arch/cp0.h> |
31 | #include <arch/exception.h> |
31 | #include <arch/exception.h> |
32 | #include <arch/asm/regname.h> |
32 | #include <arch/asm/regname.h> |
33 | #include <arch/asm.h> |
33 | #include <arch/asm.h> |
34 | #include <mm/vm.h> |
34 | #include <mm/vm.h> |
35 | #include <userspace.h> |
35 | #include <userspace.h> |
36 | #include <arch/console.h> |
36 | #include <arch/console.h> |
37 | #include <memstr.h> |
37 | #include <memstr.h> |
38 | #include <arch/interrupt.h> |
38 | #include <arch/interrupt.h> |
39 | 39 | ||
- | 40 | #include <print.h> |
|
- | 41 | ||
40 | /* Size of the code jumping to the exception handler code |
42 | /* Size of the code jumping to the exception handler code |
41 | * - J+NOP |
43 | * - J+NOP |
42 | */ |
44 | */ |
43 | #define EXCEPTION_JUMP_SIZE 8 |
45 | #define EXCEPTION_JUMP_SIZE 8 |
44 | 46 | ||
45 | #define TLB_EXC ((char *) 0x80000000) |
47 | #define TLB_EXC ((char *) 0x80000000) |
46 | #define NORM_EXC ((char *) 0x80000180) |
48 | #define NORM_EXC ((char *) 0x80000180) |
47 | #define CACHE_EXC ((char *) 0x80000100) |
49 | #define CACHE_EXC ((char *) 0x80000100) |
48 | 50 | ||
49 | #include <arch/debug.h> |
- | |
50 | - | ||
51 | #include <print.h> |
- | |
52 | void arch_pre_mm_init(void) |
51 | void arch_pre_mm_init(void) |
53 | { |
52 | { |
54 | /* It is not assumed by default */ |
53 | /* It is not assumed by default */ |
55 | cpu_priority_high(); |
54 | cpu_priority_high(); |
56 | 55 | ||
57 | /* Copy the exception vectors to the right places */ |
56 | /* Copy the exception vectors to the right places */ |
58 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
57 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
59 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
58 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
60 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
59 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
61 | 60 | ||
62 | /* |
61 | /* |
63 | * Switch to BEV normal level so that exception vectors point to the kernel. |
62 | * Switch to BEV normal level so that exception vectors point to the kernel. |
64 | * Clear the error level. |
63 | * Clear the error level. |
65 | */ |
64 | */ |
66 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
65 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
67 | 66 | ||
68 | /* |
67 | /* |
69 | * Mask all interrupts |
68 | * Mask all interrupts |
70 | */ |
69 | */ |
71 | cp0_mask_all_int(); |
70 | cp0_mask_all_int(); |
72 | /* |
71 | /* |
73 | * Unmask hardware clock interrupt. |
72 | * Unmask hardware clock interrupt. |
74 | */ |
73 | */ |
75 | cp0_unmask_int(TIMER_INTERRUPT); |
74 | cp0_unmask_int(TIMER_INTERRUPT); |
76 | 75 | ||
77 | /* |
76 | /* |
78 | * Start hardware clock. |
77 | * Start hardware clock. |
79 | */ |
78 | */ |
80 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
79 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
81 | 80 | ||
82 | console_init(); |
81 | console_init(); |
83 | } |
82 | } |
84 | 83 | ||
85 | void arch_post_mm_init(void) |
84 | void arch_post_mm_init(void) |
86 | { |
85 | { |
87 | } |
86 | } |
88 | 87 | ||
89 | void arch_late_init(void) |
88 | void arch_late_init(void) |
90 | { |
89 | { |
91 | } |
90 | } |
92 | 91 | ||
93 | void userspace(void) |
92 | void userspace(void) |
94 | { |
93 | { |
95 | /* EXL=1, UM=1, IE=1 */ |
94 | /* EXL=1, UM=1, IE=1 */ |
96 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
95 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
97 | cp0_status_um_bit | |
96 | cp0_status_um_bit | |
98 | cp0_status_ie_enabled_bit)); |
97 | cp0_status_ie_enabled_bit)); |
99 | 98 | ||
100 | cp0_epc_write(UTEXT_ADDRESS); |
99 | cp0_epc_write(UTEXT_ADDRESS); |
101 | userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
100 | userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
102 | while (1) |
101 | while (1) |
103 | ; |
102 | ; |
104 | } |
103 | } |
105 | 104 | ||
106 | /* Stack pointer saved when entering user mode */ |
105 | /* Stack pointer saved when entering user mode */ |
107 | /* TODO: How do we do it on SMP system???? */ |
106 | /* TODO: How do we do it on SMP system???? */ |
108 | __address supervisor_sp; |
107 | __address supervisor_sp; |
109 | 108 | ||
110 | void before_thread_runs_arch(void) |
109 | void before_thread_runs_arch(void) |
111 | { |
110 | { |
112 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
111 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
113 | } |
112 | } |
114 | 113 | ||
115 | 114 | ||
116 | 115 |