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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch.h> |
29 | #include <arch.h> |
30 | #include <arch/cp0.h> |
30 | #include <arch/cp0.h> |
31 | #include <arch/exception.h> |
31 | #include <arch/exception.h> |
32 | #include <arch/asm/regname.h> |
32 | #include <arch/asm/regname.h> |
33 | #include <arch/asm.h> |
33 | #include <arch/asm.h> |
34 | #include <mm/vm.h> |
34 | #include <mm/vm.h> |
35 | #include <userspace.h> |
35 | #include <userspace.h> |
36 | #include <arch/console.h> |
36 | #include <arch/console.h> |
37 | #include <memstr.h> |
37 | #include <memstr.h> |
- | 38 | #include <arch/interrupt.h> |
|
38 | 39 | ||
39 | /* Size of the code jumping to the exception handler code |
40 | /* Size of the code jumping to the exception handler code |
40 | * - J+NOP |
41 | * - J+NOP |
41 | */ |
42 | */ |
42 | #define EXCEPTION_JUMP_SIZE 8 |
43 | #define EXCEPTION_JUMP_SIZE 8 |
43 | 44 | ||
44 | #define TLB_EXC ((char *) 0x80000000) |
45 | #define TLB_EXC ((char *) 0x80000000) |
45 | #define NORM_EXC ((char *) 0x80000180) |
46 | #define NORM_EXC ((char *) 0x80000180) |
46 | #define CACHE_EXC ((char *) 0x80000100) |
47 | #define CACHE_EXC ((char *) 0x80000100) |
47 | 48 | ||
48 | #include <arch/debug.h> |
49 | #include <arch/debug.h> |
49 | 50 | ||
- | 51 | #include <print.h> |
|
50 | void arch_pre_mm_init(void) |
52 | void arch_pre_mm_init(void) |
51 | { |
53 | { |
- | 54 | /* It is not assumed by default */ |
|
- | 55 | cpu_priority_high(); |
|
- | 56 | ||
52 | /* Copy the exception vectors to the right places */ |
57 | /* Copy the exception vectors to the right places */ |
53 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
58 | memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
54 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
59 | memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
55 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
60 | memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
56 | 61 | ||
57 | - | ||
58 | /* |
62 | /* |
59 | * Switch to BEV normal level so that exception vectors point to the kernel. |
63 | * Switch to BEV normal level so that exception vectors point to the kernel. |
60 | * Clear the error level. |
64 | * Clear the error level. |
61 | */ |
65 | */ |
62 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
66 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
63 | 67 | ||
- | 68 | /* |
|
- | 69 | * Mask all interrupts |
|
- | 70 | */ |
|
- | 71 | cp0_mask_all_int(); |
|
64 | /* |
72 | /* |
65 | * Unmask hardware clock interrupt. |
73 | * Unmask hardware clock interrupt. |
66 | */ |
74 | */ |
67 | cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift)); |
75 | cp0_unmask_int(TIMER_INTERRUPT); |
68 | 76 | ||
69 | /* |
77 | /* |
70 | * Start hardware clock. |
78 | * Start hardware clock. |
71 | */ |
79 | */ |
72 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
80 | cp0_compare_write(cp0_compare_value + cp0_count_read()); |
73 | 81 | ||
74 | console_init(); |
82 | console_init(); |
75 | } |
83 | } |
76 | 84 | ||
77 | void arch_post_mm_init(void) |
85 | void arch_post_mm_init(void) |
78 | { |
86 | { |
79 | } |
87 | } |
80 | 88 | ||
81 | void arch_late_init(void) |
89 | void arch_late_init(void) |
82 | { |
90 | { |
83 | } |
91 | } |
84 | 92 | ||
85 | void userspace(void) |
93 | void userspace(void) |
86 | { |
94 | { |
87 | /* EXL=1, UM=1, IE=1 */ |
95 | /* EXL=1, UM=1, IE=1 */ |
88 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
96 | cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
89 | cp0_status_um_bit | |
97 | cp0_status_um_bit | |
90 | cp0_status_ie_enabled_bit)); |
98 | cp0_status_ie_enabled_bit)); |
91 | 99 | ||
92 | cp0_epc_write(UTEXT_ADDRESS); |
100 | cp0_epc_write(UTEXT_ADDRESS); |
93 | userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
101 | userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
94 | while (1) |
102 | while (1) |
95 | ; |
103 | ; |
96 | } |
104 | } |
97 | 105 | ||
98 | /* Stack pointer saved when entering user mode */ |
106 | /* Stack pointer saved when entering user mode */ |
99 | /* TODO: How do we do it on SMP system???? */ |
107 | /* TODO: How do we do it on SMP system???? */ |
100 | __address supervisor_sp; |
108 | __address supervisor_sp; |
101 | 109 | ||
102 | void before_thread_runs_arch(void) |
110 | void before_thread_runs_arch(void) |
103 | { |
111 | { |
104 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
112 | supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
105 | } |
113 | } |
106 | 114 | ||
107 | 115 | ||
108 | 116 |