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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <interrupt.h> |
29 | #include <interrupt.h> |
30 | #include <arch/interrupt.h> |
30 | #include <arch/interrupt.h> |
31 | #include <arch/types.h> |
31 | #include <arch/types.h> |
32 | #include <arch.h> |
32 | #include <arch.h> |
33 | #include <arch/cp0.h> |
33 | #include <arch/cp0.h> |
34 | #include <time/clock.h> |
34 | #include <time/clock.h> |
35 | #include <arch/drivers/arc.h> |
35 | #include <arch/drivers/arc.h> |
36 | 36 | ||
37 | /** Disable interrupts. |
37 | /** Disable interrupts. |
38 | * |
38 | * |
39 | * @return Old interrupt priority level. |
39 | * @return Old interrupt priority level. |
40 | */ |
40 | */ |
41 | ipl_t interrupts_disable(void) |
41 | ipl_t interrupts_disable(void) |
42 | { |
42 | { |
43 | ipl_t ipl = (ipl_t) cp0_status_read(); |
43 | ipl_t ipl = (ipl_t) cp0_status_read(); |
44 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
44 | cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
45 | return ipl; |
45 | return ipl; |
46 | } |
46 | } |
47 | 47 | ||
48 | /** Enable interrupts. |
48 | /** Enable interrupts. |
49 | * |
49 | * |
50 | * @return Old interrupt priority level. |
50 | * @return Old interrupt priority level. |
51 | */ |
51 | */ |
52 | ipl_t interrupts_enable(void) |
52 | ipl_t interrupts_enable(void) |
53 | { |
53 | { |
54 | ipl_t ipl = (ipl_t) cp0_status_read(); |
54 | ipl_t ipl = (ipl_t) cp0_status_read(); |
55 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
55 | cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
56 | return ipl; |
56 | return ipl; |
57 | } |
57 | } |
58 | 58 | ||
59 | /** Restore interrupt priority level. |
59 | /** Restore interrupt priority level. |
60 | * |
60 | * |
61 | * @param ipl Saved interrupt priority level. |
61 | * @param ipl Saved interrupt priority level. |
62 | */ |
62 | */ |
63 | void interrupts_restore(ipl_t ipl) |
63 | void interrupts_restore(ipl_t ipl) |
64 | { |
64 | { |
65 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
65 | cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
66 | } |
66 | } |
67 | 67 | ||
68 | /** Read interrupt priority level. |
68 | /** Read interrupt priority level. |
69 | * |
69 | * |
70 | * @return Current interrupt priority level. |
70 | * @return Current interrupt priority level. |
71 | */ |
71 | */ |
72 | ipl_t interrupts_read(void) |
72 | ipl_t interrupts_read(void) |
73 | { |
73 | { |
74 | return cp0_status_read(); |
74 | return cp0_status_read(); |
75 | } |
75 | } |
76 | 76 | ||
77 | static void timer_exception(int n, void *stack) |
77 | static void timer_exception(int n, void *stack) |
78 | { |
78 | { |
79 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
79 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
80 | clock(); |
80 | clock(); |
81 | } |
81 | } |
82 | 82 | ||
83 | static void swint0(int n, void *stack) |
83 | static void swint0(int n, void *stack) |
84 | { |
84 | { |
85 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
85 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
86 | } |
86 | } |
87 | 87 | ||
88 | static void swint1(int n, void *stack) |
88 | static void swint1(int n, void *stack) |
89 | { |
89 | { |
90 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
90 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
91 | } |
91 | } |
92 | 92 | ||
93 | /* Initialize basic tables for exception dispatching */ |
93 | /* Initialize basic tables for exception dispatching */ |
94 | void interrupt_init(void) |
94 | void interrupt_init(void) |
95 | { |
95 | { |
96 | int i; |
- | |
97 | - | ||
98 | int_register(TIMER_IRQ, "timer", timer_exception); |
96 | int_register(TIMER_IRQ, "timer", timer_exception); |
99 | int_register(0, "swint0", swint0); |
97 | int_register(0, "swint0", swint0); |
100 | int_register(1, "swint1", swint1); |
98 | int_register(1, "swint1", swint1); |
101 | } |
99 | } |
102 | 100 |