WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/exception.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/exception.h>
#include <arch/interrupt.h>
#include <panic.h>
#include <arch/cp0.h>
#include <arch/types.h>
#include <arch.h>
#include <debug.h>
#include <proc/thread.h>
 
void exception(struct exception_regdump *pstate)
{
    int cause;
    int excno;
    __u32 epc_shift = 0;
 
    ASSERT(CPU != NULL);
 
    /*
     * NOTE ON OPERATION ORDERING
     *
     * On entry, cpu_priority_high() must be called before
     * exception bit is cleared.
     */
 
    cpu_priority_high();
    cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
                        cp0_status_um_bit));
 
    /* Save pstate so that the threads can access it */
    /* If THREAD->pstate is set, this is nested exception,
     * do not rewrite it
     */
    if (THREAD && !THREAD->pstate)
        THREAD->pstate = pstate;
 
    cause = cp0_cause_read();
    excno = cp0_cause_excno(cause);
    /* decode exception number and process the exception */
    switch (excno) {
        case EXC_Int:
            interrupt(pstate);
            break;
        case EXC_TLBL:
        case EXC_TLBS:
            tlb_invalid(pstate);
            break;
        case EXC_CpU:
#ifdef FPU_LAZY     
            if (cp0_cause_coperr(cause) == fpu_cop_id)
                scheduler_fpu_lazy_request();
            else
#endif
                panic("unhandled Coprocessor Unusable Exception\n");
            break;
        case EXC_Mod:
            tlb_modified(pstate);
            break;
        case EXC_AdEL:
            panic("unhandled Address Error Exception - load or instruction fetch\n");
            break;
        case EXC_AdES:
            panic("unhandled Address Error Exception - store\n");
            break;
        case EXC_IBE:
            panic("unhandled Bus Error Exception - fetch instruction\n");
            break;
        case EXC_DBE:
            panic("unhandled Bus Error Exception - data reference: load or store\n");
            break;
        case EXC_Bp:
            /* it is necessary to not re-execute BREAK instruction after returning from Exception handler
               (see page 138 in R4000 Manual for more information) */
            epc_shift = 4;
            break;
        case EXC_RI:
            panic("unhandled Reserved Instruction Exception\n");
            break;
        case EXC_Ov:
            panic("unhandled Arithmetic Overflow Exception\n");
            break;
        case EXC_Tr:
            panic("unhandled Trap Exception\n");
            break;
        case EXC_VCEI:
            panic("unhandled Virtual Coherency Exception - instruction\n");
            break;
        case EXC_FPE:
            panic("unhandled Floating-Point Exception\n");
            break;
        case EXC_WATCH:
            panic("unhandled reference to WatchHi/WatchLo address\n");
            break;
        case EXC_VCED:
            panic("unhandled Virtual Coherency Exception - data\n");
            break;
        default:
            panic("unhandled exception %d\n", excno);
    }
   
    pstate->epc += epc_shift;
    /* Set to NULL, so that we can still support nested
     * exceptions
     * TODO: We should probably set EXL bit before this command,
     * nesting. On the other hand, if some exception occurs between
     * here and ERET, it won't set anything on the pstate anyway.
     */
    if (THREAD)
        THREAD->pstate = NULL;
}
 

Rev 389	Rev 391
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/exception.h>	29	#include <arch/exception.h>
30	#include <arch/interrupt.h>	30	#include <arch/interrupt.h>
31	#include <panic.h>	31	#include <panic.h>
32	#include <arch/cp0.h>	32	#include <arch/cp0.h>
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#include <arch.h>	34	#include <arch.h>
35	#include <debug.h>	35	#include <debug.h>
-		36	#include <proc/thread.h>
36		37
37	void exception(struct exception_regdump *pstate)	38	void exception(struct exception_regdump *pstate)
38	{	39	{
39	int cause;	40	int cause;
40	int excno;	41	int excno;
41	__u32 epc_shift = 0;	42	__u32 epc_shift = 0;
42		43
43	ASSERT(CPU != NULL);	44	ASSERT(CPU != NULL);
44		45
45	/*	46	/*
46	* NOTE ON OPERATION ORDERING	47	* NOTE ON OPERATION ORDERING
47	*	48	*
48	* On entry, cpu_priority_high() must be called before	49	* On entry, cpu_priority_high() must be called before
49	* exception bit is cleared.	50	* exception bit is cleared.
50	*/	51	*/
51		52
52	cpu_priority_high();	53	cpu_priority_high();
53	cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit \|	54	cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit \|
54	cp0_status_um_bit));	55	cp0_status_um_bit));
55		56
56	/* Save pstate so that the threads can access it */	57	/* Save pstate so that the threads can access it */
57	/* If THREAD->pstate is set, this is nested exception,	58	/* If THREAD->pstate is set, this is nested exception,
58	* do not rewrite it	59	* do not rewrite it
59	*/	60	*/
60	if (THREAD && !THREAD->pstate)	61	if (THREAD && !THREAD->pstate)
61	THREAD->pstate = pstate;	62	THREAD->pstate = pstate;
62		63
63	cause = cp0_cause_read();	64	cause = cp0_cause_read();
64	excno = cp0_cause_excno(cause);	65	excno = cp0_cause_excno(cause);
65	/* decode exception number and process the exception */	66	/* decode exception number and process the exception */
66	switch (excno) {	67	switch (excno) {
67	case EXC_Int:	68	case EXC_Int:
68	interrupt(pstate);	69	interrupt(pstate);
69	break;	70	break;
70	case EXC_TLBL:	71	case EXC_TLBL:
71	case EXC_TLBS:	72	case EXC_TLBS:
72	tlb_invalid(pstate);	73	tlb_invalid(pstate);
73	break;	74	break;
74	case EXC_CpU:	75	case EXC_CpU:
75	#ifdef FPU_LAZY	76	#ifdef FPU_LAZY
76	if (cp0_cause_coperr(cause) == fpu_cop_id)	77	if (cp0_cause_coperr(cause) == fpu_cop_id)
77	scheduler_fpu_lazy_request();	78	scheduler_fpu_lazy_request();
78	else	79	else
79	#endif	80	#endif
80	panic("unhandled Coprocessor Unusable Exception\n");	81	panic("unhandled Coprocessor Unusable Exception\n");
81	break;	82	break;
82	case EXC_Mod:	83	case EXC_Mod:
83	tlb_modified(pstate);	84	tlb_modified(pstate);
84	break;	85	break;
85	case EXC_AdEL:	86	case EXC_AdEL:
86	panic("unhandled Address Error Exception - load or instruction fetch\n");	87	panic("unhandled Address Error Exception - load or instruction fetch\n");
87	break;	88	break;
88	case EXC_AdES:	89	case EXC_AdES:
89	panic("unhandled Address Error Exception - store\n");	90	panic("unhandled Address Error Exception - store\n");
90	break;	91	break;
91	case EXC_IBE:	92	case EXC_IBE:
92	panic("unhandled Bus Error Exception - fetch instruction\n");	93	panic("unhandled Bus Error Exception - fetch instruction\n");
93	break;	94	break;
94	case EXC_DBE:	95	case EXC_DBE:
95	panic("unhandled Bus Error Exception - data reference: load or store\n");	96	panic("unhandled Bus Error Exception - data reference: load or store\n");
96	break;	97	break;
97	case EXC_Bp:	98	case EXC_Bp:
98	/* it is necessary to not re-execute BREAK instruction after returning from Exception handler	99	/* it is necessary to not re-execute BREAK instruction after returning from Exception handler
99	(see page 138 in R4000 Manual for more information) */	100	(see page 138 in R4000 Manual for more information) */
100	epc_shift = 4;	101	epc_shift = 4;
101	break;	102	break;
102	case EXC_RI:	103	case EXC_RI:
103	panic("unhandled Reserved Instruction Exception\n");	104	panic("unhandled Reserved Instruction Exception\n");
104	break;	105	break;
105	case EXC_Ov:	106	case EXC_Ov:
106	panic("unhandled Arithmetic Overflow Exception\n");	107	panic("unhandled Arithmetic Overflow Exception\n");
107	break;	108	break;
108	case EXC_Tr:	109	case EXC_Tr:
109	panic("unhandled Trap Exception\n");	110	panic("unhandled Trap Exception\n");
110	break;	111	break;
111	case EXC_VCEI:	112	case EXC_VCEI:
112	panic("unhandled Virtual Coherency Exception - instruction\n");	113	panic("unhandled Virtual Coherency Exception - instruction\n");
113	break;	114	break;
114	case EXC_FPE:	115	case EXC_FPE:
115	panic("unhandled Floating-Point Exception\n");	116	panic("unhandled Floating-Point Exception\n");
116	break;	117	break;
117	case EXC_WATCH:	118	case EXC_WATCH:
118	panic("unhandled reference to WatchHi/WatchLo address\n");	119	panic("unhandled reference to WatchHi/WatchLo address\n");
119	break;	120	break;
120	case EXC_VCED:	121	case EXC_VCED:
121	panic("unhandled Virtual Coherency Exception - data\n");	122	panic("unhandled Virtual Coherency Exception - data\n");
122	break;	123	break;
123	default:	124	default:
124	panic("unhandled exception %d\n", excno);	125	panic("unhandled exception %d\n", excno);
125	}	126	}
126		127
127	pstate->epc += epc_shift;	128	pstate->epc += epc_shift;
128	/* Set to NULL, so that we can still support nested	129	/* Set to NULL, so that we can still support nested
129	* exceptions	130	* exceptions
130	* TODO: We should probably set EXL bit before this command,	131	* TODO: We should probably set EXL bit before this command,
131	* nesting. On the other hand, if some exception occurs between	132	* nesting. On the other hand, if some exception occurs between
132	* here and ERET, it won't set anything on the pstate anyway.	133	* here and ERET, it won't set anything on the pstate anyway.
133	*/	134	*/
134	if (THREAD)	135	if (THREAD)
135	THREAD->pstate = NULL;	136	THREAD->pstate = NULL;
136	}	137	}
137		138

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/exception.c @ 1780 – Rev 389 → 391