WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/exception.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/exception.h>
#include <arch/interrupt.h>
#include <panic.h>
#include <arch/cp0.h>
#include <arch/types.h>
#include <arch.h>
#include <debug.h>
 
void exception(struct exception_regdump *pstate)
{
    int cause;
    int excno;
    __u32 epc_shift = 0;
 
    ASSERT(CPU != NULL);
 
    /*
     * NOTE ON OPERATION ORDERING
     *
     * On entry, cpu_priority_high() must be called before
     * exception bit is cleared.
     */
 
    cpu_priority_high();
    cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
                        cp0_status_um_bit));
 
    /* Save pstate so that the threads can access it */
    /* If THREAD->pstate is set, this is nested exception,
     * do not rewrite it
     */
    if (THREAD && !THREAD->pstate)
        THREAD->pstate = pstate;
 
    cause = cp0_cause_read();
    excno = cp0_cause_excno(cause);
    /* decode exception number and process the exception */
    switch (excno) {
        case EXC_Int:
            interrupt();
            break;
        case EXC_TLBL:
        case EXC_TLBS:
            tlb_invalid(pstate);
            break;
        case EXC_CpU:
#ifdef FPU_LAZY     
            if (cp0_cause_coperr(cause) == fpu_cop_id)
                scheduler_fpu_lazy_request();
            else
 
#endif
                panic("unhandled Coprocessor Unusable Exception\n");
            break;
        case EXC_Mod:
            panic("unhandled TLB Modification Exception\n");
            break;
        case EXC_AdEL:
            panic("unhandled Address Error Exception - load or instruction fetch\n");
            break;
        case EXC_AdES:
            panic("unhandled Address Error Exception - store\n");
            break;
        case EXC_IBE:
            panic("unhandled Bus Error Exception - fetch instruction\n");
            break;
        case EXC_DBE:
            panic("unhandled Bus Error Exception - data reference: load or store\n");
            break;
        case EXC_Bp:
            /* it is necessary to not re-execute BREAK instruction after returning from Exception handler
               (see page 138 in R4000 Manual for more information) */
            epc_shift = 4;
            break;
        case EXC_RI:
            panic("unhandled Reserved Instruction Exception\n");
            break;
        case EXC_Ov:
            panic("unhandled Arithmetic Overflow Exception\n");
            break;
        case EXC_Tr:
            panic("unhandled Trap Exception\n");
            break;
        case EXC_VCEI:
            panic("unhandled Virtual Coherency Exception - instruction\n");
            break;
        case EXC_FPE:
            panic("unhandled Floating-Point Exception\n");
            break;
        case EXC_WATCH:
            panic("unhandled reference to WatchHi/WatchLo address\n");
            break;
        case EXC_VCED:
            panic("unhandled Virtual Coherency Exception - data\n");
            break;
        default:
            panic("unhandled exception %d\n", excno);
    }
   
    pstate->epc += epc_shift;
    /* Set to NULL, so that we can still support nested
     * exceptions
     * TODO: We should probably set EXL bit before this command,
     * nesting. On the other hand, if some exception occurs between
     * here and ERET, it won't set anything on the pstate anyway.
     */
    if (THREAD)
        THREAD->pstate = NULL;
}
 

Rev 327	Rev 330
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/exception.h>	29	#include <arch/exception.h>
30	#include <arch/interrupt.h>	30	#include <arch/interrupt.h>
31	#include <panic.h>	31	#include <panic.h>
32	#include <arch/cp0.h>	32	#include <arch/cp0.h>
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#include <arch.h>	34	#include <arch.h>
35	#include <debug.h>	35	#include <debug.h>
36		36
37	void exception(struct exception_regdump *pstate)	37	void exception(struct exception_regdump *pstate)
38	{	38	{
-		39	int cause;
39	int excno;	40	int excno;
40	__u32 epc_shift = 0;	41	__u32 epc_shift = 0;
41		42
42	ASSERT(CPU != NULL);	43	ASSERT(CPU != NULL);
43		44
44	/*	45	/*
45	* NOTE ON OPERATION ORDERING	46	* NOTE ON OPERATION ORDERING
46	*	47	*
47	* On entry, cpu_priority_high() must be called before	48	* On entry, cpu_priority_high() must be called before
48	* exception bit is cleared.	49	* exception bit is cleared.
49	*/	50	*/
50		51
51	cpu_priority_high();	52	cpu_priority_high();
52	cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit \|	53	cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit \|
53	cp0_status_um_bit));	54	cp0_status_um_bit));
54		55
55	/* Save pstate so that the threads can access it */	56	/* Save pstate so that the threads can access it */
56	/* If THREAD->pstate is set, this is nested exception,	57	/* If THREAD->pstate is set, this is nested exception,
57	* do not rewrite it	58	* do not rewrite it
58	*/	59	*/
59	if (THREAD && !THREAD->pstate)	60	if (THREAD && !THREAD->pstate)
60	THREAD->pstate = pstate;	61	THREAD->pstate = pstate;
61		62
-		63	cause = cp0_cause_read();
-		64	excno = cp0_cause_excno(cause);
62	/* decode exception number and process the exception */	65	/* decode exception number and process the exception */
63	switch (excno = (cp0_cause_read() >> 2) & 0x1f) {	66	switch (excno) {
64	case EXC_Int:	67	case EXC_Int:
65	interrupt();	68	interrupt();
66	break;	69	break;
67	case EXC_TLBL:	70	case EXC_TLBL:
68	case EXC_TLBS:	71	case EXC_TLBS:
69	tlb_invalid(pstate);	72	tlb_invalid(pstate);
70	break;	73	break;
71	case EXC_CpU:	74	case EXC_CpU:
72	#ifdef FPU_LAZY	75	#ifdef FPU_LAZY
-		76	if (cp0_cause_coperr(cause) == fpu_cop_id)
73	scheduler_fpu_lazy_request();	77	scheduler_fpu_lazy_request();
74	#else	78	else
75	panic("unhandled Coprocessor Unusable Exception\n");	-
76	#endif	79	#endif
-		80	panic("unhandled Coprocessor Unusable Exception\n");
77	break;	81	break;
78	case EXC_Mod:	82	case EXC_Mod:
79	panic("unhandled TLB Modification Exception\n");	83	panic("unhandled TLB Modification Exception\n");
80	break;	84	break;
81	case EXC_AdEL:	85	case EXC_AdEL:
82	panic("unhandled Address Error Exception - load or instruction fetch\n");	86	panic("unhandled Address Error Exception - load or instruction fetch\n");
83	break;	87	break;
84	case EXC_AdES:	88	case EXC_AdES:
85	panic("unhandled Address Error Exception - store\n");	89	panic("unhandled Address Error Exception - store\n");
86	break;	90	break;
87	case EXC_IBE:	91	case EXC_IBE:
88	panic("unhandled Bus Error Exception - fetch instruction\n");	92	panic("unhandled Bus Error Exception - fetch instruction\n");
89	break;	93	break;
90	case EXC_DBE:	94	case EXC_DBE:
91	panic("unhandled Bus Error Exception - data reference: load or store\n");	95	panic("unhandled Bus Error Exception - data reference: load or store\n");
92	break;	96	break;
93	case EXC_Bp:	97	case EXC_Bp:
94	/* it is necessary to not re-execute BREAK instruction after returning from Exception handler	98	/* it is necessary to not re-execute BREAK instruction after returning from Exception handler
95	(see page 138 in R4000 Manual for more information) */	99	(see page 138 in R4000 Manual for more information) */
96	epc_shift = 4;	100	epc_shift = 4;
97	break;	101	break;
98	case EXC_RI:	102	case EXC_RI:
99	panic("unhandled Reserved Instruction Exception\n");	103	panic("unhandled Reserved Instruction Exception\n");
100	break;	104	break;
101	case EXC_Ov:	105	case EXC_Ov:
102	panic("unhandled Arithmetic Overflow Exception\n");	106	panic("unhandled Arithmetic Overflow Exception\n");
103	break;	107	break;
104	case EXC_Tr:	108	case EXC_Tr:
105	panic("unhandled Trap Exception\n");	109	panic("unhandled Trap Exception\n");
106	break;	110	break;
107	case EXC_VCEI:	111	case EXC_VCEI:
108	panic("unhandled Virtual Coherency Exception - instruction\n");	112	panic("unhandled Virtual Coherency Exception - instruction\n");
109	break;	113	break;
110	case EXC_FPE:	114	case EXC_FPE:
111	panic("unhandled Floating-Point Exception\n");	115	panic("unhandled Floating-Point Exception\n");
112	break;	116	break;
113	case EXC_WATCH:	117	case EXC_WATCH:
114	panic("unhandled reference to WatchHi/WatchLo address\n");	118	panic("unhandled reference to WatchHi/WatchLo address\n");
115	break;	119	break;
116	case EXC_VCED:	120	case EXC_VCED:
117	panic("unhandled Virtual Coherency Exception - data\n");	121	panic("unhandled Virtual Coherency Exception - data\n");
118	break;	122	break;
119	default:	123	default:
120	panic("unhandled exception %d\n", excno);	124	panic("unhandled exception %d\n", excno);
121	}	125	}
122		126
123	pstate->epc += epc_shift;	127	pstate->epc += epc_shift;
124	/* Set to NULL, so that we can still support nested	128	/* Set to NULL, so that we can still support nested
125	* exceptions	129	* exceptions
126	* TODO: We should probably set EXL bit before this command,	130	* TODO: We should probably set EXL bit before this command,
127	* nesting. On the other hand, if some exception occurs between	131	* nesting. On the other hand, if some exception occurs between
128	* here and ERET, it won't set anything on the pstate anyway.	132	* here and ERET, it won't set anything on the pstate anyway.
129	*/	133	*/
130	if (THREAD)	134	if (THREAD)
131	THREAD->pstate = NULL;	135	THREAD->pstate = NULL;
132	}	136	}
133		137

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(root)/kernel/trunk/arch/mips32/src/exception.c @ 1708 – Rev 327 → 330