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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Ondrej Palkovsky |
2 | * Copyright (C) 2005 Ondrej Palkovsky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <interrupt.h> |
29 | #include <interrupt.h> |
30 | #include <console/chardev.h> |
30 | #include <console/chardev.h> |
31 | #include <arch/drivers/msim.h> |
31 | #include <arch/drivers/msim.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
- | 33 | #include <console/console.h> |
|
33 | 34 | ||
34 | static chardev_t console; |
35 | static chardev_t console; |
35 | 36 | ||
36 | static void msim_write(chardev_t *dev, const char ch); |
37 | static void msim_write(chardev_t *dev, const char ch); |
37 | static void msim_enable(chardev_t *dev); |
38 | static void msim_enable(chardev_t *dev); |
38 | static void msim_disable(chardev_t *dev); |
39 | static void msim_disable(chardev_t *dev); |
39 | 40 | ||
40 | static chardev_operations_t msim_ops = { |
41 | static chardev_operations_t msim_ops = { |
41 | .resume = msim_enable, |
42 | .resume = msim_enable, |
42 | .suspend = msim_disable, |
43 | .suspend = msim_disable, |
43 | .write = msim_write |
44 | .write = msim_write |
44 | }; |
45 | }; |
45 | 46 | ||
46 | /** Putchar that works with MSIM & gxemul */ |
47 | /** Putchar that works with MSIM & gxemul */ |
47 | void msim_write(chardev_t *dev, const char ch) |
48 | void msim_write(chardev_t *dev, const char ch) |
48 | { |
49 | { |
49 | *((char *) MSIM_VIDEORAM) = ch; |
50 | *((char *) MSIM_VIDEORAM) = ch; |
50 | } |
51 | } |
51 | 52 | ||
52 | /* Called from getc(). */ |
53 | /* Called from getc(). */ |
53 | void msim_enable(chardev_t *dev) |
54 | void msim_enable(chardev_t *dev) |
54 | { |
55 | { |
55 | cp0_unmask_int(MSIM_KBD_IRQ); |
56 | cp0_unmask_int(MSIM_KBD_IRQ); |
56 | } |
57 | } |
57 | 58 | ||
58 | /* Called from getc(). */ |
59 | /* Called from getc(). */ |
59 | void msim_disable(chardev_t *dev) |
60 | void msim_disable(chardev_t *dev) |
60 | { |
61 | { |
61 | cp0_mask_int(MSIM_KBD_IRQ); |
62 | cp0_mask_int(MSIM_KBD_IRQ); |
62 | } |
63 | } |
63 | 64 | ||
64 | #include <print.h> |
65 | #include <print.h> |
65 | /** Process keyboard interrupt. */ |
66 | /** Process keyboard interrupt. */ |
66 | static void msim_interrupt(int n, void *stack) |
67 | static void msim_interrupt(int n, void *stack) |
67 | { |
68 | { |
68 | char ch; |
69 | char ch; |
69 | 70 | ||
70 | ch = *((char *) MSIM_KBD_ADDRESS); |
71 | ch = *((char *) MSIM_KBD_ADDRESS); |
71 | if (ch =='\r') |
72 | if (ch =='\r') |
72 | ch = '\n'; |
73 | ch = '\n'; |
73 | if (ch == 0x7f) |
74 | if (ch == 0x7f) |
74 | ch = '\b'; |
75 | ch = '\b'; |
75 | chardev_push_character(&console, ch); |
76 | chardev_push_character(&console, ch); |
76 | } |
77 | } |
77 | 78 | ||
78 | 79 | ||
79 | /* Return console object representing msim console */ |
80 | /* Return console object representing msim console */ |
80 | chardev_t * msim_console(void) |
81 | void msim_console(void) |
81 | { |
82 | { |
82 | chardev_initialize("msim_console", &console, &msim_ops); |
83 | chardev_initialize("msim_console", &console, &msim_ops); |
83 | 84 | ||
84 | int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); |
85 | int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); |
85 | 86 | ||
86 | cp0_unmask_int(MSIM_KBD_IRQ); |
87 | cp0_unmask_int(MSIM_KBD_IRQ); |
87 | 88 | ||
88 | return &console; |
89 | stdin = &console; |
- | 90 | stdout = &console; |
|
89 | } |
91 | } |
90 | 92 |