WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/asm.S


#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/asm/regname.h>
	
.text
 
.macro cp0_read reg
	mfc0 $2,\reg
	j $31
	nop
.endm
 
.macro cp0_write reg
	mtc0 $4,\reg
	j $31
	nop
.endm
 
.set noat
.set noreorder
.set nomacro
 
.global cpu_halt
cpu_halt:
	j cpu_halt
	nop
 
 
.global memsetb
memsetb:
	j _memsetb
	nop
 
 
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
        srl     $t1,$a2,0x2
	beqz    $t1,1f
        move    $t0,$zero
        move    $a3,$zero
2:	
        addu    $v0,$a1,$a3
        lw      $v1,0($v0)
        addiu   $t0,$t0,1
        addu    $v0,$a0,$a3
        sw      $v1,0($v0)
        bne     $t0,$t1,2b
        addiu   $a3,$a3,4
1:	
        andi    $a2,$a2,0x3
        beqz    $a2,3f
        move    $a3,$zero
        sll     $v0,$t0,0x2
        addu    $t1,$a0,$v0
        addu    $t0,$v0,$a1
4:	
        addu    $v0,$t0,$a3
        lbu     $a0,0($v0)
        addu    $v1,$t1,$a3
        addiu   $a3,$a3,1
        bne     $a3,$a2,4b
        sb      $a0,0($v1)
3:	
        jr      $ra
        move    $v0,$a1
 
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
 
	jr	$ra
	move	$v0, $zero
 
 
 
.macro fpu_gp_save reg ctx
	mfc1 $t0,$\reg
	sw $t0, \reg*4(\ctx)
.endm
 
.macro fpu_gp_restore reg ctx
	lw $t0, \reg*4(\ctx)
	mtc1 $t0,$\reg
.endm
 
.macro fpu_ct_save reg ctx
	cfc1 $t0,$1
	sw $t0, (\reg+32)*4(\ctx)
.endm	
 
.macro fpu_ct_restore reg ctx
	lw $t0, (\reg+32)*4(\ctx)
	ctc1 $t0,$\reg
.endm
 
 
.global fpu_context_save
fpu_context_save:
#ifdef ARCH_HAS_FPU
	fpu_gp_save 0,$a0
	fpu_gp_save 1,$a0
	fpu_gp_save 2,$a0
	fpu_gp_save 3,$a0
	fpu_gp_save 4,$a0
	fpu_gp_save 5,$a0
	fpu_gp_save 6,$a0
	fpu_gp_save 7,$a0
	fpu_gp_save 8,$a0
	fpu_gp_save 9,$a0
	fpu_gp_save 10,$a0
	fpu_gp_save 11,$a0
	fpu_gp_save 12,$a0
	fpu_gp_save 13,$a0
	fpu_gp_save 14,$a0
	fpu_gp_save 15,$a0
	fpu_gp_save 16,$a0
	fpu_gp_save 17,$a0
	fpu_gp_save 18,$a0
	fpu_gp_save 19,$a0
	fpu_gp_save 20,$a0
	fpu_gp_save 21,$a0
	fpu_gp_save 22,$a0
	fpu_gp_save 23,$a0
	fpu_gp_save 24,$a0
	fpu_gp_save 25,$a0
	fpu_gp_save 26,$a0
	fpu_gp_save 27,$a0
	fpu_gp_save 28,$a0
	fpu_gp_save 29,$a0
	fpu_gp_save 30,$a0
	fpu_gp_save 31,$a0
 
	fpu_ct_save 1,$a0
	fpu_ct_save 2,$a0
	fpu_ct_save 3,$a0
	fpu_ct_save 4,$a0
	fpu_ct_save 5,$a0
	fpu_ct_save 6,$a0
	fpu_ct_save 7,$a0
	fpu_ct_save 8,$a0
	fpu_ct_save 9,$a0
	fpu_ct_save 10,$a0
	fpu_ct_save 11,$a0
	fpu_ct_save 12,$a0
	fpu_ct_save 13,$a0
	fpu_ct_save 14,$a0
	fpu_ct_save 15,$a0
	fpu_ct_save 16,$a0
	fpu_ct_save 17,$a0
	fpu_ct_save 18,$a0
	fpu_ct_save 19,$a0
	fpu_ct_save 20,$a0
	fpu_ct_save 21,$a0
	fpu_ct_save 22,$a0
	fpu_ct_save 23,$a0
	fpu_ct_save 24,$a0
	fpu_ct_save 25,$a0
	fpu_ct_save 26,$a0
	fpu_ct_save 27,$a0
	fpu_ct_save 28,$a0
	fpu_ct_save 29,$a0
	fpu_ct_save 30,$a0
	fpu_ct_save 31,$a0
#endif		
	j $ra
	nop
 
.global fpu_context_restore
fpu_context_restore:
#ifdef ARCH_HAS_FPU
	fpu_gp_restore 0,$a0
	fpu_gp_restore 1,$a0
	fpu_gp_restore 2,$a0
	fpu_gp_restore 3,$a0
	fpu_gp_restore 4,$a0
	fpu_gp_restore 5,$a0
	fpu_gp_restore 6,$a0
	fpu_gp_restore 7,$a0
	fpu_gp_restore 8,$a0
	fpu_gp_restore 9,$a0
	fpu_gp_restore 10,$a0
	fpu_gp_restore 11,$a0
	fpu_gp_restore 12,$a0
	fpu_gp_restore 13,$a0
	fpu_gp_restore 14,$a0
	fpu_gp_restore 15,$a0
	fpu_gp_restore 16,$a0
	fpu_gp_restore 17,$a0
	fpu_gp_restore 18,$a0
	fpu_gp_restore 19,$a0
	fpu_gp_restore 20,$a0
	fpu_gp_restore 21,$a0
	fpu_gp_restore 22,$a0
	fpu_gp_restore 23,$a0
	fpu_gp_restore 24,$a0
	fpu_gp_restore 25,$a0
	fpu_gp_restore 26,$a0
	fpu_gp_restore 27,$a0
	fpu_gp_restore 28,$a0
	fpu_gp_restore 29,$a0
	fpu_gp_restore 30,$a0
	fpu_gp_restore 31,$a0
 
	fpu_ct_restore 1,$a0
	fpu_ct_restore 2,$a0
	fpu_ct_restore 3,$a0
	fpu_ct_restore 4,$a0
	fpu_ct_restore 5,$a0
	fpu_ct_restore 6,$a0
	fpu_ct_restore 7,$a0
	fpu_ct_restore 8,$a0
	fpu_ct_restore 9,$a0
	fpu_ct_restore 10,$a0
	fpu_ct_restore 11,$a0
	fpu_ct_restore 12,$a0
	fpu_ct_restore 13,$a0
	fpu_ct_restore 14,$a0
	fpu_ct_restore 15,$a0
	fpu_ct_restore 16,$a0
	fpu_ct_restore 17,$a0
	fpu_ct_restore 18,$a0
	fpu_ct_restore 19,$a0
	fpu_ct_restore 20,$a0
	fpu_ct_restore 21,$a0
	fpu_ct_restore 22,$a0
	fpu_ct_restore 23,$a0
	fpu_ct_restore 24,$a0
	fpu_ct_restore 25,$a0
	fpu_ct_restore 26,$a0
	fpu_ct_restore 27,$a0
	fpu_ct_restore 28,$a0
	fpu_ct_restore 29,$a0
	fpu_ct_restore 30,$a0
	fpu_ct_restore 31,$a0
#endif	
	j $ra
	nop
 

Rev 1288	Rev 1293
1	#	1	#
2	# Copyright (C) 2003-2004 Jakub Jermar	2	# Copyright (C) 2003-2004 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/asm/regname.h>	29	#include <arch/asm/regname.h>
30		30
31	.text	31	.text
32		32
33	.macro cp0_read reg	33	.macro cp0_read reg
34	mfc0 $2,\reg	34	mfc0 $2,\reg
35	j $31	35	j $31
36	nop	36	nop
37	.endm	37	.endm
38		38
39	.macro cp0_write reg	39	.macro cp0_write reg
40	mtc0 $4,\reg	40	mtc0 $4,\reg
41	j $31	41	j $31
42	nop	42	nop
43	.endm	43	.endm
44		44
45	.set noat	45	.set noat
46	.set noreorder	46	.set noreorder
47	.set nomacro	47	.set nomacro
48		48
49	.global cpu_halt	49	.global cpu_halt
50	cpu_halt:	50	cpu_halt:
51	j cpu_halt	51	j cpu_halt
52	nop	52	nop
53		53
54		54
55	.global memsetb	55	.global memsetb
56	memsetb:	56	memsetb:
57	j _memsetb	57	j _memsetb
58	nop	58	nop
59		59
60		60
61	.global memcpy	61	.global memcpy
62	.global memcpy_from_uspace	62	.global memcpy_from_uspace
63	.global memcpy_to_uspace	63	.global memcpy_to_uspace
64	.global memcpy_from_uspace_failover_address	64	.global memcpy_from_uspace_failover_address
65	.global memcpy_to_uspace_failover_address	65	.global memcpy_to_uspace_failover_address
66	memcpy:	66	memcpy:
67	memcpy_from_uspace:	67	memcpy_from_uspace:
68	memcpy_to_uspace:	68	memcpy_to_uspace:
-		69	srl $t1,$a2,0x2
69	j _memcpy	70	beqz $t1,1f
-		71	move $t0,$zero
-		72	move $a3,$zero
-		73	2:
-		74	addu $v0,$a1,$a3
-		75	lw $v1,0($v0)
-		76	addiu $t0,$t0,1
-		77	addu $v0,$a0,$a3
-		78	sw $v1,0($v0)
-		79	bne $t0,$t1,2b
-		80	addiu $a3,$a3,4
70	nop	81	1:
-		82	andi $a2,$a2,0x3
-		83	beqz $a2,3f
-		84	move $a3,$zero
-		85	sll $v0,$t0,0x2
-		86	addu $t1,$a0,$v0
-		87	addu $t0,$v0,$a1
-		88	4:
-		89	addu $v0,$t0,$a3
-		90	lbu $a0,0($v0)
-		91	addu $v1,$t1,$a3
-		92	addiu $a3,$a3,1
-		93	bne $a3,$a2,4b
-		94	sb $a0,0($v1)
-		95	3:
-		96	jr $ra
-		97	move $v0,$a1
71		98
72	memcpy_from_uspace_failover_address:	99	memcpy_from_uspace_failover_address:
73	memcpy_to_uspace_failover_address:	100	memcpy_to_uspace_failover_address:
74	j memcpy_from_uspace_failover_address	-
75	nop	101	jr $ra
-		102	move $v0, $zero
76		103
77		104
78		105
79	.macro fpu_gp_save reg ctx	106	.macro fpu_gp_save reg ctx
80	mfc1 $t0,$\reg	107	mfc1 $t0,$\reg
81	sw $t0, \reg*4(\ctx)	108	sw $t0, \reg*4(\ctx)
82	.endm	109	.endm
83		110
84	.macro fpu_gp_restore reg ctx	111	.macro fpu_gp_restore reg ctx
85	lw $t0, \reg*4(\ctx)	112	lw $t0, \reg*4(\ctx)
86	mtc1 $t0,$\reg	113	mtc1 $t0,$\reg
87	.endm	114	.endm
88		115
89	.macro fpu_ct_save reg ctx	116	.macro fpu_ct_save reg ctx
90	cfc1 $t0,$1	117	cfc1 $t0,$1
91	sw $t0, (\reg+32)*4(\ctx)	118	sw $t0, (\reg+32)*4(\ctx)
92	.endm	119	.endm
93		120
94	.macro fpu_ct_restore reg ctx	121	.macro fpu_ct_restore reg ctx
95	lw $t0, (\reg+32)*4(\ctx)	122	lw $t0, (\reg+32)*4(\ctx)
96	ctc1 $t0,$\reg	123	ctc1 $t0,$\reg
97	.endm	124	.endm
98		125
99		126
100	.global fpu_context_save	127	.global fpu_context_save
101	fpu_context_save:	128	fpu_context_save:
102	#ifdef ARCH_HAS_FPU	129	#ifdef ARCH_HAS_FPU
103	fpu_gp_save 0,$a0	130	fpu_gp_save 0,$a0
104	fpu_gp_save 1,$a0	131	fpu_gp_save 1,$a0
105	fpu_gp_save 2,$a0	132	fpu_gp_save 2,$a0
106	fpu_gp_save 3,$a0	133	fpu_gp_save 3,$a0
107	fpu_gp_save 4,$a0	134	fpu_gp_save 4,$a0
108	fpu_gp_save 5,$a0	135	fpu_gp_save 5,$a0
109	fpu_gp_save 6,$a0	136	fpu_gp_save 6,$a0
110	fpu_gp_save 7,$a0	137	fpu_gp_save 7,$a0
111	fpu_gp_save 8,$a0	138	fpu_gp_save 8,$a0
112	fpu_gp_save 9,$a0	139	fpu_gp_save 9,$a0
113	fpu_gp_save 10,$a0	140	fpu_gp_save 10,$a0
114	fpu_gp_save 11,$a0	141	fpu_gp_save 11,$a0
115	fpu_gp_save 12,$a0	142	fpu_gp_save 12,$a0
116	fpu_gp_save 13,$a0	143	fpu_gp_save 13,$a0
117	fpu_gp_save 14,$a0	144	fpu_gp_save 14,$a0
118	fpu_gp_save 15,$a0	145	fpu_gp_save 15,$a0
119	fpu_gp_save 16,$a0	146	fpu_gp_save 16,$a0
120	fpu_gp_save 17,$a0	147	fpu_gp_save 17,$a0
121	fpu_gp_save 18,$a0	148	fpu_gp_save 18,$a0
122	fpu_gp_save 19,$a0	149	fpu_gp_save 19,$a0
123	fpu_gp_save 20,$a0	150	fpu_gp_save 20,$a0
124	fpu_gp_save 21,$a0	151	fpu_gp_save 21,$a0
125	fpu_gp_save 22,$a0	152	fpu_gp_save 22,$a0
126	fpu_gp_save 23,$a0	153	fpu_gp_save 23,$a0
127	fpu_gp_save 24,$a0	154	fpu_gp_save 24,$a0
128	fpu_gp_save 25,$a0	155	fpu_gp_save 25,$a0
129	fpu_gp_save 26,$a0	156	fpu_gp_save 26,$a0
130	fpu_gp_save 27,$a0	157	fpu_gp_save 27,$a0
131	fpu_gp_save 28,$a0	158	fpu_gp_save 28,$a0
132	fpu_gp_save 29,$a0	159	fpu_gp_save 29,$a0
133	fpu_gp_save 30,$a0	160	fpu_gp_save 30,$a0
134	fpu_gp_save 31,$a0	161	fpu_gp_save 31,$a0
135		162
136	fpu_ct_save 1,$a0	163	fpu_ct_save 1,$a0
137	fpu_ct_save 2,$a0	164	fpu_ct_save 2,$a0
138	fpu_ct_save 3,$a0	165	fpu_ct_save 3,$a0
139	fpu_ct_save 4,$a0	166	fpu_ct_save 4,$a0
140	fpu_ct_save 5,$a0	167	fpu_ct_save 5,$a0
141	fpu_ct_save 6,$a0	168	fpu_ct_save 6,$a0
142	fpu_ct_save 7,$a0	169	fpu_ct_save 7,$a0
143	fpu_ct_save 8,$a0	170	fpu_ct_save 8,$a0
144	fpu_ct_save 9,$a0	171	fpu_ct_save 9,$a0
145	fpu_ct_save 10,$a0	172	fpu_ct_save 10,$a0
146	fpu_ct_save 11,$a0	173	fpu_ct_save 11,$a0
147	fpu_ct_save 12,$a0	174	fpu_ct_save 12,$a0
148	fpu_ct_save 13,$a0	175	fpu_ct_save 13,$a0
149	fpu_ct_save 14,$a0	176	fpu_ct_save 14,$a0
150	fpu_ct_save 15,$a0	177	fpu_ct_save 15,$a0
151	fpu_ct_save 16,$a0	178	fpu_ct_save 16,$a0
152	fpu_ct_save 17,$a0	179	fpu_ct_save 17,$a0
153	fpu_ct_save 18,$a0	180	fpu_ct_save 18,$a0
154	fpu_ct_save 19,$a0	181	fpu_ct_save 19,$a0
155	fpu_ct_save 20,$a0	182	fpu_ct_save 20,$a0
156	fpu_ct_save 21,$a0	183	fpu_ct_save 21,$a0
157	fpu_ct_save 22,$a0	184	fpu_ct_save 22,$a0
158	fpu_ct_save 23,$a0	185	fpu_ct_save 23,$a0
159	fpu_ct_save 24,$a0	186	fpu_ct_save 24,$a0
160	fpu_ct_save 25,$a0	187	fpu_ct_save 25,$a0
161	fpu_ct_save 26,$a0	188	fpu_ct_save 26,$a0
162	fpu_ct_save 27,$a0	189	fpu_ct_save 27,$a0
163	fpu_ct_save 28,$a0	190	fpu_ct_save 28,$a0
164	fpu_ct_save 29,$a0	191	fpu_ct_save 29,$a0
165	fpu_ct_save 30,$a0	192	fpu_ct_save 30,$a0
166	fpu_ct_save 31,$a0	193	fpu_ct_save 31,$a0
167	#endif	194	#endif
168	j $ra	195	j $ra
169	nop	196	nop
170		197
171	.global fpu_context_restore	198	.global fpu_context_restore
172	fpu_context_restore:	199	fpu_context_restore:
173	#ifdef ARCH_HAS_FPU	200	#ifdef ARCH_HAS_FPU
174	fpu_gp_restore 0,$a0	201	fpu_gp_restore 0,$a0
175	fpu_gp_restore 1,$a0	202	fpu_gp_restore 1,$a0
176	fpu_gp_restore 2,$a0	203	fpu_gp_restore 2,$a0
177	fpu_gp_restore 3,$a0	204	fpu_gp_restore 3,$a0
178	fpu_gp_restore 4,$a0	205	fpu_gp_restore 4,$a0
179	fpu_gp_restore 5,$a0	206	fpu_gp_restore 5,$a0
180	fpu_gp_restore 6,$a0	207	fpu_gp_restore 6,$a0
181	fpu_gp_restore 7,$a0	208	fpu_gp_restore 7,$a0
182	fpu_gp_restore 8,$a0	209	fpu_gp_restore 8,$a0
183	fpu_gp_restore 9,$a0	210	fpu_gp_restore 9,$a0
184	fpu_gp_restore 10,$a0	211	fpu_gp_restore 10,$a0
185	fpu_gp_restore 11,$a0	212	fpu_gp_restore 11,$a0
186	fpu_gp_restore 12,$a0	213	fpu_gp_restore 12,$a0
187	fpu_gp_restore 13,$a0	214	fpu_gp_restore 13,$a0
188	fpu_gp_restore 14,$a0	215	fpu_gp_restore 14,$a0
189	fpu_gp_restore 15,$a0	216	fpu_gp_restore 15,$a0
190	fpu_gp_restore 16,$a0	217	fpu_gp_restore 16,$a0
191	fpu_gp_restore 17,$a0	218	fpu_gp_restore 17,$a0
192	fpu_gp_restore 18,$a0	219	fpu_gp_restore 18,$a0
193	fpu_gp_restore 19,$a0	220	fpu_gp_restore 19,$a0
194	fpu_gp_restore 20,$a0	221	fpu_gp_restore 20,$a0
195	fpu_gp_restore 21,$a0	222	fpu_gp_restore 21,$a0
196	fpu_gp_restore 22,$a0	223	fpu_gp_restore 22,$a0
197	fpu_gp_restore 23,$a0	224	fpu_gp_restore 23,$a0
198	fpu_gp_restore 24,$a0	225	fpu_gp_restore 24,$a0
199	fpu_gp_restore 25,$a0	226	fpu_gp_restore 25,$a0
200	fpu_gp_restore 26,$a0	227	fpu_gp_restore 26,$a0
201	fpu_gp_restore 27,$a0	228	fpu_gp_restore 27,$a0
202	fpu_gp_restore 28,$a0	229	fpu_gp_restore 28,$a0
203	fpu_gp_restore 29,$a0	230	fpu_gp_restore 29,$a0
204	fpu_gp_restore 30,$a0	231	fpu_gp_restore 30,$a0
205	fpu_gp_restore 31,$a0	232	fpu_gp_restore 31,$a0
206		233
207	fpu_ct_restore 1,$a0	234	fpu_ct_restore 1,$a0
208	fpu_ct_restore 2,$a0	235	fpu_ct_restore 2,$a0
209	fpu_ct_restore 3,$a0	236	fpu_ct_restore 3,$a0
210	fpu_ct_restore 4,$a0	237	fpu_ct_restore 4,$a0
211	fpu_ct_restore 5,$a0	238	fpu_ct_restore 5,$a0
212	fpu_ct_restore 6,$a0	239	fpu_ct_restore 6,$a0
213	fpu_ct_restore 7,$a0	240	fpu_ct_restore 7,$a0
214	fpu_ct_restore 8,$a0	241	fpu_ct_restore 8,$a0
215	fpu_ct_restore 9,$a0	242	fpu_ct_restore 9,$a0
216	fpu_ct_restore 10,$a0	243	fpu_ct_restore 10,$a0
217	fpu_ct_restore 11,$a0	244	fpu_ct_restore 11,$a0
218	fpu_ct_restore 12,$a0	245	fpu_ct_restore 12,$a0
219	fpu_ct_restore 13,$a0	246	fpu_ct_restore 13,$a0
220	fpu_ct_restore 14,$a0	247	fpu_ct_restore 14,$a0
221	fpu_ct_restore 15,$a0	248	fpu_ct_restore 15,$a0
222	fpu_ct_restore 16,$a0	249	fpu_ct_restore 16,$a0
223	fpu_ct_restore 17,$a0	250	fpu_ct_restore 17,$a0
224	fpu_ct_restore 18,$a0	251	fpu_ct_restore 18,$a0
225	fpu_ct_restore 19,$a0	252	fpu_ct_restore 19,$a0
226	fpu_ct_restore 20,$a0	253	fpu_ct_restore 20,$a0
227	fpu_ct_restore 21,$a0	254	fpu_ct_restore 21,$a0
228	fpu_ct_restore 22,$a0	255	fpu_ct_restore 22,$a0
229	fpu_ct_restore 23,$a0	256	fpu_ct_restore 23,$a0
230	fpu_ct_restore 24,$a0	257	fpu_ct_restore 24,$a0
231	fpu_ct_restore 25,$a0	258	fpu_ct_restore 25,$a0
232	fpu_ct_restore 26,$a0	259	fpu_ct_restore 26,$a0
233	fpu_ct_restore 27,$a0	260	fpu_ct_restore 27,$a0
234	fpu_ct_restore 28,$a0	261	fpu_ct_restore 28,$a0
235	fpu_ct_restore 29,$a0	262	fpu_ct_restore 29,$a0
236	fpu_ct_restore 30,$a0	263	fpu_ct_restore 30,$a0
237	fpu_ct_restore 31,$a0	264	fpu_ct_restore 31,$a0
238	#endif	265	#endif
239	j $ra	266	j $ra
240	nop	267	nop
241		268

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/asm.S – Rev 1288 → 1293