WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/include/cp0.h


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __mips32_CP0_H__
#define __mips32_CP0_H__
 
#include <arch/types.h>
#include <arch/mm/tlb.h>
 
#define cp0_status_ie_enabled_bit   (1<<0)
#define cp0_status_exl_exception_bit    (1<<1)
#define cp0_status_erl_error_bit    (1<<2)
#define cp0_status_um_bit           (1<<4)
#define cp0_status_bev_bootstrap_bit    (1<<22)
#define cp0_status_fpu_bit              (1<<29)
 
#define cp0_status_im_shift     8
#define cp0_status_im_mask              0xff00
 
#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
 
#define fpu_cop_id 1
 
/*
 * Magic value for use in msim.
 * On AMD Duron 800Mhz, this roughly seems like one us.
 */
#define cp0_compare_value       10000
 
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
extern  __u32 cp0_index_read(void);
extern void cp0_index_write(__u32 val);
 
extern __u32 cp0_random_read(void);
 
extern __u32 cp0_entry_lo0_read(void);
extern void cp0_entry_lo0_write(__u32 val);
 
extern __u32 cp0_entry_lo1_read(void);
extern void cp0_entry_lo1_write(__u32 val);
 
extern __u32 cp0_context_read(void);
extern void cp0_context_write(__u32 val);
 
extern __u32 cp0_pagemask_read(void);
extern void cp0_pagemask_write(__u32 val);
 
extern __u32 cp0_wired_read(void);
extern void cp0_wired_write(__u32 val);
 
extern __u32 cp0_badvaddr_read(void);
 
extern __u32 cp0_count_read(void);
extern void cp0_count_write(__u32 val);
 
extern __u32 cp0_entry_hi_read(void);
extern void cp0_entry_hi_write(__u32 val);
 
extern __u32 cp0_compare_read(void);
extern void cp0_compare_write(__u32 val);
 
extern __u32 cp0_status_read(void);
extern void cp0_status_write(__u32 val);
 
extern __u32 cp0_cause_read(void);
extern void cp0_cause_write(__u32 val);
 
extern __u32 cp0_epc_read(void);
extern void cp0_epc_write(__u32 val);
 
extern __u32 cp0_prid_read(void);
 
#endif
 

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/include/cp0.h @ 1096 – Rev 534 → 610

Rev 534		Rev 610
1	/*	1	/*
2	* Copyright (C) 2003-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __mips32_CP0_H__	29	#ifndef __mips32_CP0_H__
30	#define __mips32_CP0_H__	30	#define __mips32_CP0_H__
31		31
32	#include <arch/types.h>	32	#include <arch/types.h>
33	#include <arch/mm/tlb.h>	33	#include <arch/mm/tlb.h>
34		34
35	#define cp0_status_ie_enabled_bit (1<<0)	35	#define cp0_status_ie_enabled_bit (1<<0)
36	#define cp0_status_exl_exception_bit (1<<1)	36	#define cp0_status_exl_exception_bit (1<<1)
37	#define cp0_status_erl_error_bit (1<<2)	37	#define cp0_status_erl_error_bit (1<<2)
38	#define cp0_status_um_bit (1<<4)	38	#define cp0_status_um_bit (1<<4)
39	#define cp0_status_bev_bootstrap_bit (1<<22)	39	#define cp0_status_bev_bootstrap_bit (1<<22)
40	#define cp0_status_fpu_bit (1<<29)	40	#define cp0_status_fpu_bit (1<<29)
41		41
42	#define cp0_status_im_shift 8	42	#define cp0_status_im_shift 8
43	#define cp0_status_im_mask 0xff00	43	#define cp0_status_im_mask 0xff00
44		44
45	#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)	45	#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
46	#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)	46	#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
47		47
48	#define fpu_cop_id 1	48	#define fpu_cop_id 1
49		49
50	/*	50	/*
51	* Magic value for use in msim.	51	* Magic value for use in msim.
52	* On AMD Duron 800Mhz, this roughly seems like one us.	52	* On AMD Duron 800Mhz, this roughly seems like one us.
53	*/	53	*/
54	#define cp0_compare_value 10000	54	#define cp0_compare_value 10000
55		55
56	#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))	56	#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
57	#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() \| cp0_status_im_mask)	57	#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() \| cp0_status_im_mask)
58	#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))	58	#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
59	#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() \| (1<<(cp0_status_im_shift+(it))))	59	#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() \| (1<<(cp0_status_im_shift+(it))))
60		60
61	extern __u32 cp0_index_read(void);	61	extern __u32 cp0_index_read(void);
62	extern void cp0_index_write(__u32 val);	62	extern void cp0_index_write(__u32 val);
63		63
64	extern __u32 cp0_random_read(void);	64	extern __u32 cp0_random_read(void);
65		65
66	extern __u32 cp0_entry_lo0_read(void);	66	extern __u32 cp0_entry_lo0_read(void);
67	extern void cp0_entry_lo0_write(__u32 val);	67	extern void cp0_entry_lo0_write(__u32 val);
68		68
69	extern __u32 cp0_entry_lo1_read(void);	69	extern __u32 cp0_entry_lo1_read(void);
70	extern void cp0_entry_lo1_write(__u32 val);	70	extern void cp0_entry_lo1_write(__u32 val);
71		71
72	extern __u32 cp0_context_read(void);	72	extern __u32 cp0_context_read(void);
73	extern void cp0_context_write(__u32 val);	73	extern void cp0_context_write(__u32 val);
74		74
75	extern __u32 cp0_pagemask_read(void);	75	extern __u32 cp0_pagemask_read(void);
76	extern void cp0_pagemask_write(__u32 val);	76	extern void cp0_pagemask_write(__u32 val);
77		77
78	extern __u32 cp0_wired_read(void);	78	extern __u32 cp0_wired_read(void);
79	extern void cp0_wired_write(__u32 val);	79	extern void cp0_wired_write(__u32 val);
80		80
81	extern __u32 cp0_badvaddr_read(void);	81	extern __u32 cp0_badvaddr_read(void);
82		82
83	extern volatile __u32 cp0_count_read(void);	83	extern __u32 cp0_count_read(void);
84	extern void cp0_count_write(__u32 val);	84	extern void cp0_count_write(__u32 val);
85		85
86	extern volatile __u32 cp0_entry_hi_read(void);	86	extern __u32 cp0_entry_hi_read(void);
87	extern void cp0_entry_hi_write(__u32 val);	87	extern void cp0_entry_hi_write(__u32 val);
88		88
89	extern volatile __u32 cp0_compare_read(void);	89	extern __u32 cp0_compare_read(void);
90	extern void cp0_compare_write(__u32 val);	90	extern void cp0_compare_write(__u32 val);
91		91
92	extern __u32 cp0_status_read(void);	92	extern __u32 cp0_status_read(void);
93	extern void cp0_status_write(__u32 val);	93	extern void cp0_status_write(__u32 val);
94		94
95	extern __u32 cp0_cause_read(void);	95	extern __u32 cp0_cause_read(void);
96	extern void cp0_cause_write(__u32 val);	96	extern void cp0_cause_write(__u32 val);
97		97
98	extern __u32 cp0_epc_read(void);	98	extern __u32 cp0_epc_read(void);
99	extern void cp0_epc_write(__u32 val);	99	extern void cp0_epc_write(__u32 val);
100		100
101	extern __u32 cp0_prid_read(void);	101	extern __u32 cp0_prid_read(void);
102		102
103	#endif	103	#endif
104		104