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/*
1
/*
2
 * Copyright (C) 2006 Jakub Jermar
2
 * Copyright (C) 2006 Jakub Jermar
3
 * Copyright (C) 2006 Jakub Vana
3
 * Copyright (C) 2006 Jakub Vana
4
 * All rights reserved.
4
 * All rights reserved.
5
 *
5
 *
6
 * Redistribution and use in source and binary forms, with or without
6
 * Redistribution and use in source and binary forms, with or without
7
 * modification, are permitted provided that the following conditions
7
 * modification, are permitted provided that the following conditions
8
 * are met:
8
 * are met:
9
 *
9
 *
10
 * - Redistributions of source code must retain the above copyright
10
 * - Redistributions of source code must retain the above copyright
11
 *   notice, this list of conditions and the following disclaimer.
11
 *   notice, this list of conditions and the following disclaimer.
12
 * - Redistributions in binary form must reproduce the above copyright
12
 * - Redistributions in binary form must reproduce the above copyright
13
 *   notice, this list of conditions and the following disclaimer in the
13
 *   notice, this list of conditions and the following disclaimer in the
14
 *   documentation and/or other materials provided with the distribution.
14
 *   documentation and/or other materials provided with the distribution.
15
 * - The name of the author may not be used to endorse or promote products
15
 * - The name of the author may not be used to endorse or promote products
16
 *   derived from this software without specific prior written permission.
16
 *   derived from this software without specific prior written permission.
17
 *
17
 *
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
 */
28
 */
29
 
29
 
30
#include <arch/mm/page.h>
30
#include <arch/mm/page.h>
31
#include <genarch/mm/page_ht.h>
31
#include <genarch/mm/page_ht.h>
32
#include <mm/asid.h>
32
#include <mm/asid.h>
33
#include <arch/mm/asid.h>
33
#include <arch/mm/asid.h>
34
#include <arch/types.h>
34
#include <arch/types.h>
35
#include <typedefs.h>
35
#include <typedefs.h>
36
#include <print.h>
36
#include <print.h>
37
#include <mm/page.h>
37
#include <mm/page.h>
38
#include <mm/frame.h>
38
#include <mm/frame.h>
39
#include <config.h>
39
#include <config.h>
40
#include <panic.h>
40
#include <panic.h>
41
#include <arch/asm.h>
41
#include <arch/asm.h>
42
#include <arch/barrier.h>
42
#include <arch/barrier.h>
43
#include <memstr.h>
43
#include <memstr.h>
44
 
44
 
45
static void set_environment(void);
45
static void set_environment(void);
46
 
46
 
47
/** Initialize ia64 virtual address translation subsystem. */
47
/** Initialize ia64 virtual address translation subsystem. */
48
void page_arch_init(void)
48
void page_arch_init(void)
49
{
49
{
50
    page_mapping_operations = &ht_mapping_operations;
50
    page_mapping_operations = &ht_mapping_operations;
51
    pk_disable();
51
    pk_disable();
52
    set_environment();
52
    set_environment();
53
}
53
}
54
 
54
 
55
/** Initialize VHPT and region registers. */
55
/** Initialize VHPT and region registers. */
56
void set_environment(void)
56
void set_environment(void)
57
{
57
{
58
    region_register rr;
58
    region_register rr;
59
    pta_register pta;  
59
    pta_register pta;  
60
    int i;
60
    int i;
61
 
61
 
62
    /*
62
    /*
63
     * First set up kernel region register.
63
     * First set up kernel region register.
64
     * This is redundant (see start.S) but we keep it here just for sure.
64
     * This is redundant (see start.S) but we keep it here just for sure.
65
     */
65
     */
66
    rr.word = rr_read(VRN_KERNEL);
66
    rr.word = rr_read(VRN_KERNEL);
67
    rr.map.ve = 0;                  /* disable VHPT walker */
67
    rr.map.ve = 0;                  /* disable VHPT walker */
68
    rr.map.ps = PAGE_WIDTH;
68
    rr.map.ps = PAGE_WIDTH;
69
    rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
69
    rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
70
    rr_write(VRN_KERNEL, rr.word);
70
    rr_write(VRN_KERNEL, rr.word);
71
    srlz_i();
71
    srlz_i();
72
    srlz_d();
72
    srlz_d();
73
 
73
 
74
    /*
74
    /*
75
     * And setup the rest of region register.
75
     * And setup the rest of region register.
76
     */
76
     */
77
    for(i = 0; i < REGION_REGISTERS; i++) {
77
    for(i = 0; i < REGION_REGISTERS; i++) {
78
        /* skip kernel rr */
78
        /* skip kernel rr */
79
        if (i == VRN_KERNEL)
79
        if (i == VRN_KERNEL)
80
            continue;
80
            continue;
81
   
81
   
82
        rr.word == rr_read(i);
82
        rr.word = rr_read(i);
83
        rr.map.ve = 0;      /* disable VHPT walker */
83
        rr.map.ve = 0;      /* disable VHPT walker */
84
        rr.map.rid = RID_KERNEL;
84
        rr.map.rid = RID_KERNEL;
85
        rr.map.ps = PAGE_WIDTH;
85
        rr.map.ps = PAGE_WIDTH;
86
        rr_write(i, rr.word);
86
        rr_write(i, rr.word);
87
        srlz_i();
87
        srlz_i();
88
        srlz_d();
88
        srlz_d();
89
    }
89
    }
90
 
90
 
91
    /*
91
    /*
92
     * Set up PTA register.
92
     * Set up PTA register.
93
     */
93
     */
94
    pta.word = pta_read();
94
    pta.word = pta_read();
95
    pta.map.ve = 0;                   /* disable VHPT walker */
95
    pta.map.ve = 0;                   /* disable VHPT walker */
96
    pta.map.vf = 1;                   /* large entry format */
96
    pta.map.vf = 1;                   /* large entry format */
97
    pta.map.size = VHPT_WIDTH;
97
    pta.map.size = VHPT_WIDTH;
98
    pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
98
    pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
99
    pta_write(pta.word);
99
    pta_write(pta.word);
100
    srlz_i();
100
    srlz_i();
101
    srlz_d();
101
    srlz_d();
102
}
102
}
103
 
103
 
104
/** Calculate address of collision chain from VPN and ASID.
104
/** Calculate address of collision chain from VPN and ASID.
105
 *
105
 *
106
 * Interrupts must be disabled.
106
 * Interrupts must be disabled.
107
 *
107
 *
108
 * @param page Address of virtual page including VRN bits.
108
 * @param page Address of virtual page including VRN bits.
109
 * @param asid Address space identifier.
109
 * @param asid Address space identifier.
110
 *
110
 *
111
 * @return VHPT entry address.
111
 * @return VHPT entry address.
112
 */
112
 */
113
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
113
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
114
{
114
{
115
    region_register rr_save, rr;
115
    region_register rr_save, rr;
116
    index_t vrn;
116
    index_t vrn;
117
    rid_t rid;
117
    rid_t rid;
118
    vhpt_entry_t *v;
118
    vhpt_entry_t *v;
119
 
119
 
120
    vrn = page >> VRN_SHIFT;
120
    vrn = page >> VRN_SHIFT;
121
    rid = ASID2RID(asid, vrn);
121
    rid = ASID2RID(asid, vrn);
122
   
122
   
123
    rr_save.word = rr_read(vrn);
123
    rr_save.word = rr_read(vrn);
124
    if (rr_save.map.rid == rid) {
124
    if (rr_save.map.rid == rid) {
125
        /*
125
        /*
126
         * The RID is already in place, compute thash and return.
126
         * The RID is already in place, compute thash and return.
127
         */
127
         */
128
        v = (vhpt_entry_t *) thash(page);
128
        v = (vhpt_entry_t *) thash(page);
129
        return v;
129
        return v;
130
    }
130
    }
131
   
131
   
132
    /*
132
    /*
133
     * The RID must be written to some region register.
133
     * The RID must be written to some region register.
134
     * To speed things up, register indexed by vrn is used.
134
     * To speed things up, register indexed by vrn is used.
135
     */
135
     */
136
    rr.word = rr_save.word;
136
    rr.word = rr_save.word;
137
    rr.map.rid = rid;
137
    rr.map.rid = rid;
138
    rr_write(vrn, rr.word);
138
    rr_write(vrn, rr.word);
139
    srlz_i();
139
    srlz_i();
140
    v = (vhpt_entry_t *) thash(page);
140
    v = (vhpt_entry_t *) thash(page);
141
    rr_write(vrn, rr_save.word);
141
    rr_write(vrn, rr_save.word);
142
    srlz_i();
142
    srlz_i();
143
    srlz_d();
143
    srlz_d();
144
 
144
 
145
    return v;
145
    return v;
146
}
146
}
147
 
147
 
148
/** Compare ASID and VPN against PTE.
148
/** Compare ASID and VPN against PTE.
149
 *
149
 *
150
 * Interrupts must be disabled.
150
 * Interrupts must be disabled.
151
 *
151
 *
152
 * @param page Address of virtual page including VRN bits.
152
 * @param page Address of virtual page including VRN bits.
153
 * @param asid Address space identifier.
153
 * @param asid Address space identifier.
154
 *
154
 *
155
 * @return True if page and asid match the page and asid of t, false otherwise.
155
 * @return True if page and asid match the page and asid of t, false otherwise.
156
 */
156
 */
157
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
157
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
158
{
158
{
159
    region_register rr_save, rr;   
159
    region_register rr_save, rr;   
160
    index_t vrn;
160
    index_t vrn;
161
    rid_t rid;
161
    rid_t rid;
162
    bool match;
162
    bool match;
163
 
163
 
164
    ASSERT(v);
164
    ASSERT(v);
165
 
165
 
166
    vrn = page >> VRN_SHIFT;
166
    vrn = page >> VRN_SHIFT;
167
    rid = ASID2RID(asid, vrn);
167
    rid = ASID2RID(asid, vrn);
168
   
168
   
169
    rr_save.word = rr_read(vrn);
169
    rr_save.word = rr_read(vrn);
170
    if (rr_save.map.rid == rid) {
170
    if (rr_save.map.rid == rid) {
171
        /*
171
        /*
172
         * The RID is already in place, compare ttag with t and return.
172
         * The RID is already in place, compare ttag with t and return.
173
         */
173
         */
174
        return ttag(page) == v->present.tag.tag_word;
174
        return ttag(page) == v->present.tag.tag_word;
175
    }
175
    }
176
   
176
   
177
    /*
177
    /*
178
     * The RID must be written to some region register.
178
     * The RID must be written to some region register.
179
     * To speed things up, register indexed by vrn is used.
179
     * To speed things up, register indexed by vrn is used.
180
     */
180
     */
181
    rr.word = rr_save.word;
181
    rr.word = rr_save.word;
182
    rr.map.rid = rid;
182
    rr.map.rid = rid;
183
    rr_write(vrn, rr.word);
183
    rr_write(vrn, rr.word);
184
    srlz_i();
184
    srlz_i();
185
    match = (ttag(page) == v->present.tag.tag_word);
185
    match = (ttag(page) == v->present.tag.tag_word);
186
    rr_write(vrn, rr_save.word);
186
    rr_write(vrn, rr_save.word);
187
    srlz_i();
187
    srlz_i();
188
    srlz_d();
188
    srlz_d();
189
 
189
 
190
    return match;      
190
    return match;      
191
}
191
}
192
 
192
 
193
/** Set up one VHPT entry.
193
/** Set up one VHPT entry.
194
 *
194
 *
195
 * @param t VHPT entry to be set up.
195
 * @param t VHPT entry to be set up.
196
 * @param page Virtual address of the page mapped by the entry.
196
 * @param page Virtual address of the page mapped by the entry.
197
 * @param asid Address space identifier of the address space to which page belongs.
197
 * @param asid Address space identifier of the address space to which page belongs.
198
 * @param frame Physical address of the frame to wich page is mapped.
198
 * @param frame Physical address of the frame to wich page is mapped.
199
 * @param flags Different flags for the mapping.
199
 * @param flags Different flags for the mapping.
200
 */
200
 */
201
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
201
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
202
{
202
{
203
    region_register rr_save, rr;   
203
    region_register rr_save, rr;   
204
    index_t vrn;
204
    index_t vrn;
205
    rid_t rid;
205
    rid_t rid;
206
    __u64 tag;
206
    __u64 tag;
207
 
207
 
208
    ASSERT(v);
208
    ASSERT(v);
209
 
209
 
210
    vrn = page >> VRN_SHIFT;
210
    vrn = page >> VRN_SHIFT;
211
    rid = ASID2RID(asid, vrn);
211
    rid = ASID2RID(asid, vrn);
212
   
212
   
213
    /*
213
    /*
214
     * Compute ttag.
214
     * Compute ttag.
215
     */
215
     */
216
    rr_save.word = rr_read(vrn);
216
    rr_save.word = rr_read(vrn);
217
    rr.word = rr_save.word;
217
    rr.word = rr_save.word;
218
    rr.map.rid = rid;
218
    rr.map.rid = rid;
219
    rr_write(vrn, rr.word);
219
    rr_write(vrn, rr.word);
220
    srlz_i();
220
    srlz_i();
221
    tag = ttag(page);
221
    tag = ttag(page);
222
    rr_write(vrn, rr_save.word);
222
    rr_write(vrn, rr_save.word);
223
    srlz_i();
223
    srlz_i();
224
    srlz_d();
224
    srlz_d();
225
   
225
   
226
    /*
226
    /*
227
     * Clear the entry.
227
     * Clear the entry.
228
     */
228
     */
229
    v->word[0] = 0;
229
    v->word[0] = 0;
230
    v->word[1] = 0;
230
    v->word[1] = 0;
231
    v->word[2] = 0;
231
    v->word[2] = 0;
232
    v->word[3] = 0;
232
    v->word[3] = 0;
233
   
233
   
234
    v->present.p = true;
234
    v->present.p = true;
235
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
235
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
236
    v->present.a = false;   /* not accessed */
236
    v->present.a = false;   /* not accessed */
237
    v->present.d = false;   /* not dirty */
237
    v->present.d = false;   /* not dirty */
238
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
238
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
239
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
239
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
240
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
240
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
241
    v->present.ppn = frame >> PPN_SHIFT;
241
    v->present.ppn = frame >> PPN_SHIFT;
242
    v->present.ed = false;  /* exception not deffered */
242
    v->present.ed = false;  /* exception not deffered */
243
    v->present.ps = PAGE_WIDTH;
243
    v->present.ps = PAGE_WIDTH;
244
    v->present.key = 0;
244
    v->present.key = 0;
245
    v->present.tag.tag_word = tag;
245
    v->present.tag.tag_word = tag;
246
}
246
}
247
 
247