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1
/*
1
/*
2
 * Copyright (C) 2006 Jakub Jermar
2
 * Copyright (C) 2006 Jakub Jermar
3
 * Copyright (C) 2006 Jakub Vana
3
 * Copyright (C) 2006 Jakub Vana
4
 * All rights reserved.
4
 * All rights reserved.
5
 *
5
 *
6
 * Redistribution and use in source and binary forms, with or without
6
 * Redistribution and use in source and binary forms, with or without
7
 * modification, are permitted provided that the following conditions
7
 * modification, are permitted provided that the following conditions
8
 * are met:
8
 * are met:
9
 *
9
 *
10
 * - Redistributions of source code must retain the above copyright
10
 * - Redistributions of source code must retain the above copyright
11
 *   notice, this list of conditions and the following disclaimer.
11
 *   notice, this list of conditions and the following disclaimer.
12
 * - Redistributions in binary form must reproduce the above copyright
12
 * - Redistributions in binary form must reproduce the above copyright
13
 *   notice, this list of conditions and the following disclaimer in the
13
 *   notice, this list of conditions and the following disclaimer in the
14
 *   documentation and/or other materials provided with the distribution.
14
 *   documentation and/or other materials provided with the distribution.
15
 * - The name of the author may not be used to endorse or promote products
15
 * - The name of the author may not be used to endorse or promote products
16
 *   derived from this software without specific prior written permission.
16
 *   derived from this software without specific prior written permission.
17
 *
17
 *
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
 */
28
 */
29
 
29
 
30
#include <arch/mm/page.h>
30
#include <arch/mm/page.h>
31
#include <genarch/mm/page_ht.h>
31
#include <genarch/mm/page_ht.h>
32
#include <mm/asid.h>
32
#include <mm/asid.h>
33
#include <arch/mm/asid.h>
33
#include <arch/mm/asid.h>
34
#include <arch/types.h>
34
#include <arch/types.h>
35
#include <typedefs.h>
35
#include <typedefs.h>
36
#include <print.h>
36
#include <print.h>
37
#include <mm/page.h>
37
#include <mm/page.h>
38
#include <mm/frame.h>
38
#include <mm/frame.h>
39
#include <config.h>
39
#include <config.h>
40
#include <panic.h>
40
#include <panic.h>
41
#include <arch/asm.h>
41
#include <arch/asm.h>
42
#include <arch/barrier.h>
42
#include <arch/barrier.h>
43
#include <memstr.h>
43
#include <memstr.h>
44
 
44
 
45
static void set_environment(void);
45
static void set_environment(void);
46
 
46
 
47
/** Initialize ia64 virtual address translation subsystem. */
47
/** Initialize ia64 virtual address translation subsystem. */
48
void page_arch_init(void)
48
void page_arch_init(void)
49
{
49
{
50
    page_mapping_operations = &ht_mapping_operations;
50
    page_mapping_operations = &ht_mapping_operations;
51
    pk_disable();
51
    pk_disable();
52
    set_environment();
52
    set_environment();
53
}
53
}
54
 
54
 
55
/** Initialize VHPT and region registers. */
55
/** Initialize VHPT and region registers. */
56
void set_environment(void)
56
void set_environment(void)
57
{
57
{
58
 
58
 
59
//#ifdef NEVERDEFINED   
-
 
60
    region_register rr;
59
    region_register rr;
61
    pta_register pta;  
60
    pta_register pta;  
62
    int i;
61
    int i;
63
 
62
 
64
    /*
63
    /*
65
     * First set up kernel region register.
64
     * First set up kernel region register.
-
 
65
     * This action is redundand (see start.S) but I would to keep it to make sure that
-
 
66
     *no unexpected changes will be made.
66
     */
67
     */
67
    rr.word = rr_read(VRN_KERNEL);
68
    rr.word = rr_read(VRN_KERNEL);
68
    rr.map.ve = 0;                  /* disable VHPT walker */
69
    rr.map.ve = 0;                  /* disable VHPT walker */
69
    rr.map.ps = PAGE_WIDTH;
70
    rr.map.ps = PAGE_WIDTH;
70
    rr.map.rid = ASID_KERNEL;
71
    rr.map.rid = ASID2RID(ASID_KERNEL,VRN_KERNEL);  
71
    rr_write(VRN_KERNEL, rr.word);
72
    rr_write(VRN_KERNEL, rr.word);
72
    srlz_i();
73
    srlz_i();
73
    srlz_d();
74
    srlz_d();
74
   
75
   
75
    /*
76
    /*
76
     * And invalidate the rest of region register.
77
     * And invalidate the rest of region register.
77
     */
78
     */
78
    for(i = 0; i < REGION_REGISTERS; i++) {
79
    for(i = 0; i < REGION_REGISTERS; i++) {
79
        /* skip kernel rr */
80
        /* skip kernel rr */
80
        if (i == VRN_KERNEL)
81
        if (i == VRN_KERNEL)
81
            continue;
82
            continue;
82
   
83
   
83
        rr.word == rr_read(i);
84
        rr.word == rr_read(i);
84
        rr.map.ve = 0;      /* disable VHPT walker */
85
        rr.map.ve = 0;      /* disable VHPT walker */
85
        rr.map.rid = ASID_INVALID;
86
        rr.map.rid = ASID2RID(ASID_INVALID,i);
86
        rr_write(i, rr.word);
87
        rr_write(i, rr.word);
87
        srlz_i();
88
        srlz_i();
88
        srlz_d();
89
        srlz_d();
89
    }
90
    }
90
 
91
 
91
    /*
92
    /*
92
     * Set up PTA register.
93
     * Set up PTA register.
93
     */
94
     */
94
    pta.word = pta_read();
95
    pta.word = pta_read();
95
    pta.map.ve = 0;                   /* disable VHPT walker */
96
    pta.map.ve = 0;                   /* disable VHPT walker */
96
    pta.map.vf = 1;                   /* large entry format */
97
    pta.map.vf = 1;                   /* large entry format */
97
    pta.map.size = VHPT_WIDTH;
98
    pta.map.size = VHPT_WIDTH;
98
    pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
99
    pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
99
    pta_write(pta.word);
100
    pta_write(pta.word);
100
    srlz_i();
101
    srlz_i();
101
    srlz_d();
102
    srlz_d();
102
   
103
   
103
//#endif
-
 
104
 
104
 
105
    return ;   
105
    return ;   
106
   
106
   
107
}
107
}
108
 
108
 
109
/** Calculate address of collision chain from VPN and ASID.
109
/** Calculate address of collision chain from VPN and ASID.
110
 *
110
 *
111
 * Interrupts must be disabled.
111
 * Interrupts must be disabled.
112
 *
112
 *
113
 * @param page Address of virtual page including VRN bits.
113
 * @param page Address of virtual page including VRN bits.
114
 * @param asid Address space identifier.
114
 * @param asid Address space identifier.
115
 *
115
 *
116
 * @return VHPT entry address.
116
 * @return VHPT entry address.
117
 */
117
 */
118
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
118
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
119
{
119
{
120
    region_register rr_save, rr;
120
    region_register rr_save, rr;
121
    index_t vrn;
121
    index_t vrn;
122
    rid_t rid;
122
    rid_t rid;
123
    vhpt_entry_t *v;
123
    vhpt_entry_t *v;
124
 
124
 
125
    vrn = page >> VRN_SHIFT;
125
    vrn = page >> VRN_SHIFT;
126
    rid = ASID2RID(asid, vrn);
126
    rid = ASID2RID(asid, vrn);
127
   
127
   
128
    rr_save.word = rr_read(vrn);
128
    rr_save.word = rr_read(vrn);
129
    if (rr_save.map.rid == rid) {
129
    if (rr_save.map.rid == rid) {
130
        /*
130
        /*
131
         * The RID is already in place, compute thash and return.
131
         * The RID is already in place, compute thash and return.
132
         */
132
         */
133
        v = (vhpt_entry_t *) thash(page);
133
        v = (vhpt_entry_t *) thash(page);
134
        return v;
134
        return v;
135
    }
135
    }
136
   
136
   
137
    /*
137
    /*
138
     * The RID must be written to some region register.
138
     * The RID must be written to some region register.
139
     * To speed things up, register indexed by vrn is used.
139
     * To speed things up, register indexed by vrn is used.
140
     */
140
     */
141
    rr.word = rr_save.word;
141
    rr.word = rr_save.word;
142
    rr.map.rid = rid;
142
    rr.map.rid = rid;
143
    rr_write(vrn, rr.word);
143
    rr_write(vrn, rr.word);
144
    srlz_i();
144
    srlz_i();
145
    v = (vhpt_entry_t *) thash(page);
145
    v = (vhpt_entry_t *) thash(page);
146
    rr_write(vrn, rr_save.word);
146
    rr_write(vrn, rr_save.word);
147
    srlz_i();
147
    srlz_i();
148
    srlz_d();
148
    srlz_d();
149
 
149
 
150
    return v;
150
    return v;
151
}
151
}
152
 
152
 
153
/** Compare ASID and VPN against PTE.
153
/** Compare ASID and VPN against PTE.
154
 *
154
 *
155
 * Interrupts must be disabled.
155
 * Interrupts must be disabled.
156
 *
156
 *
157
 * @param page Address of virtual page including VRN bits.
157
 * @param page Address of virtual page including VRN bits.
158
 * @param asid Address space identifier.
158
 * @param asid Address space identifier.
159
 *
159
 *
160
 * @return True if page and asid match the page and asid of t, false otherwise.
160
 * @return True if page and asid match the page and asid of t, false otherwise.
161
 */
161
 */
162
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
162
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
163
{
163
{
164
    region_register rr_save, rr;   
164
    region_register rr_save, rr;   
165
    index_t vrn;
165
    index_t vrn;
166
    rid_t rid;
166
    rid_t rid;
167
    bool match;
167
    bool match;
168
 
168
 
169
    ASSERT(v);
169
    ASSERT(v);
170
 
170
 
171
    vrn = page >> VRN_SHIFT;
171
    vrn = page >> VRN_SHIFT;
172
    rid = ASID2RID(asid, vrn);
172
    rid = ASID2RID(asid, vrn);
173
   
173
   
174
    rr_save.word = rr_read(vrn);
174
    rr_save.word = rr_read(vrn);
175
    if (rr_save.map.rid == rid) {
175
    if (rr_save.map.rid == rid) {
176
        /*
176
        /*
177
         * The RID is already in place, compare ttag with t and return.
177
         * The RID is already in place, compare ttag with t and return.
178
         */
178
         */
179
        return ttag(page) == v->present.tag.tag_word;
179
        return ttag(page) == v->present.tag.tag_word;
180
    }
180
    }
181
   
181
   
182
    /*
182
    /*
183
     * The RID must be written to some region register.
183
     * The RID must be written to some region register.
184
     * To speed things up, register indexed by vrn is used.
184
     * To speed things up, register indexed by vrn is used.
185
     */
185
     */
186
    rr.word = rr_save.word;
186
    rr.word = rr_save.word;
187
    rr.map.rid = rid;
187
    rr.map.rid = rid;
188
    rr_write(vrn, rr.word);
188
    rr_write(vrn, rr.word);
189
    srlz_i();
189
    srlz_i();
190
    match = (ttag(page) == v->present.tag.tag_word);
190
    match = (ttag(page) == v->present.tag.tag_word);
191
    rr_write(vrn, rr_save.word);
191
    rr_write(vrn, rr_save.word);
192
    srlz_i();
192
    srlz_i();
193
    srlz_d();
193
    srlz_d();
194
 
194
 
195
    return match;      
195
    return match;      
196
}
196
}
197
 
197
 
198
/** Set up one VHPT entry.
198
/** Set up one VHPT entry.
199
 *
199
 *
200
 * @param t VHPT entry to be set up.
200
 * @param t VHPT entry to be set up.
201
 * @param page Virtual address of the page mapped by the entry.
201
 * @param page Virtual address of the page mapped by the entry.
202
 * @param asid Address space identifier of the address space to which page belongs.
202
 * @param asid Address space identifier of the address space to which page belongs.
203
 * @param frame Physical address of the frame to wich page is mapped.
203
 * @param frame Physical address of the frame to wich page is mapped.
204
 * @param flags Different flags for the mapping.
204
 * @param flags Different flags for the mapping.
205
 */
205
 */
206
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
206
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
207
{
207
{
208
    region_register rr_save, rr;   
208
    region_register rr_save, rr;   
209
    index_t vrn;
209
    index_t vrn;
210
    rid_t rid;
210
    rid_t rid;
211
    __u64 tag;
211
    __u64 tag;
212
 
212
 
213
    ASSERT(v);
213
    ASSERT(v);
214
 
214
 
215
    vrn = page >> VRN_SHIFT;
215
    vrn = page >> VRN_SHIFT;
216
    rid = ASID2RID(asid, vrn);
216
    rid = ASID2RID(asid, vrn);
217
   
217
   
218
    /*
218
    /*
219
     * Compute ttag.
219
     * Compute ttag.
220
     */
220
     */
221
    rr_save.word = rr_read(vrn);
221
    rr_save.word = rr_read(vrn);
222
    rr.word = rr_save.word;
222
    rr.word = rr_save.word;
223
    rr.map.rid = rid;
223
    rr.map.rid = rid;
224
    rr_write(vrn, rr.word);
224
    rr_write(vrn, rr.word);
225
    srlz_i();
225
    srlz_i();
226
    tag = ttag(page);
226
    tag = ttag(page);
227
    rr_write(vrn, rr_save.word);
227
    rr_write(vrn, rr_save.word);
228
    srlz_i();
228
    srlz_i();
229
    srlz_d();
229
    srlz_d();
230
   
230
   
231
    /*
231
    /*
232
     * Clear the entry.
232
     * Clear the entry.
233
     */
233
     */
234
    v->word[0] = 0;
234
    v->word[0] = 0;
235
    v->word[1] = 0;
235
    v->word[1] = 0;
236
    v->word[2] = 0;
236
    v->word[2] = 0;
237
    v->word[3] = 0;
237
    v->word[3] = 0;
238
   
238
   
239
    v->present.p = true;
239
    v->present.p = true;
240
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
240
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
241
    v->present.a = false;   /* not accessed */
241
    v->present.a = false;   /* not accessed */
242
    v->present.d = false;   /* not dirty */
242
    v->present.d = false;   /* not dirty */
243
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
243
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
244
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
244
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
245
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
245
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
246
    v->present.ppn = frame >> PPN_SHIFT;
246
    v->present.ppn = frame >> PPN_SHIFT;
247
    v->present.ed = false;  /* exception not deffered */
247
    v->present.ed = false;  /* exception not deffered */
248
    v->present.ps = PAGE_WIDTH;
248
    v->present.ps = PAGE_WIDTH;
249
    v->present.key = 0;
249
    v->present.key = 0;
250
    v->present.tag.tag_word = tag;
250
    v->present.tag.tag_word = tag;
251
}
251
}
252
 
252