WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/mm/page.c


/*
 * Copyright (C) 2006 Jakub Jermar
 * Copyright (C) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/mm/page.h>
#include <genarch/mm/page_ht.h>
#include <mm/asid.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <typedefs.h>
#include <print.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <config.h>
#include <panic.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <memstr.h>
 
static void set_vhpt_environment(void);
 
/** Initialize ia64 virtual address translation subsystem. */
void page_arch_init(void)
{
    page_operations = &page_ht_operations;
    pk_disable();
    set_vhpt_environment();
}
 
/** Initialize VHPT and region registers. */
void set_vhpt_environment(void)
{
    region_register rr;
    pta_register pta;  
    int i;
   
    /*
     * First set up kernel region register.
     */
    rr.word = rr_read(VRN_KERNEL);
    rr.map.ve = 0;                  /* disable VHPT walker */
    rr.map.ps = PAGE_WIDTH;
    rr.map.rid = ASID_KERNEL;
    rr_write(VRN_KERNEL, rr.word);
    srlz_i();
    srlz_d();
   
    /*
     * And invalidate the rest of region register.
     */
    for(i = 0; i < REGION_REGISTERS; i++) {
        /* skip kernel rr */
        if (i == VRN_KERNEL)
            continue;
   
        rr.word == rr_read(i);
        rr.map.ve = 0;      /* disable VHPT walker */
        rr.map.rid = ASID_INVALID;
        rr_write(i, rr.word);
        srlz_i();
        srlz_d();
    }
 
    /*
     * Allocate VHPT and invalidate all its entries.
     */
    page_ht = (pte_t *) frame_alloc(FRAME_KA, VHPT_WIDTH - FRAME_WIDTH, NULL, NULL);
    memsetb((__address) page_ht, VHPT_SIZE, 0);
    ht_invalidate_all();   
   
    /*
     * Set up PTA register.
     */
    pta.word = pta_read();
    pta.map.ve = 0;                   /* disable VHPT walker */
    pta.map.vf = 1;                   /* large entry format */
    pta.map.size = VHPT_WIDTH;
    pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT;
    pta_write(pta.word);
    srlz_i();
    srlz_d();
}
 
/** Calculate address of collision chain from VPN and ASID.
 *
 * Interrupts must be disabled.
 *
 * @param page Address of virtual page including VRN bits.
 * @param asid Address space identifier.
 *
 * @return Head of VHPT collision chain for page and asid.
 */
pte_t *vhpt_hash(__address page, asid_t asid)
{
    region_register rr_save, rr;
    index_t vrn;
    rid_t rid;
    pte_t *t;
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    rr_save.word = rr_read(vrn);
    if (rr_save.map.rid == rid) {
        /*
         * The RID is already in place, compute thash and return.
         */
        t = (pte_t *) thash(page);
        return t;
    }
   
    /*
     * The RID must be written to some region register.
     * To speed things up, register indexed by vrn is used.
     */
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    t = (pte_t *) thash(page);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
 
    return t;
}
 
/** Compare ASID and VPN against PTE.
 *
 * Interrupts must be disabled.
 *
 * @param page Address of virtual page including VRN bits.
 * @param asid Address space identifier.
 *
 * @return True if page and asid match the page and asid of t, false otherwise.
 */
bool vhpt_compare(__address page, asid_t asid, pte_t *t)
{
    region_register rr_save, rr;   
    index_t vrn;
    rid_t rid;
    bool match;
 
    ASSERT(t);
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    rr_save.word = rr_read(vrn);
    if (rr_save.map.rid == rid) {
        /*
         * The RID is already in place, compare ttag with t and return.
         */
        return ttag(page) == t->present.tag.tag_word;
    }
   
    /*
     * The RID must be written to some region register.
     * To speed things up, register indexed by vrn is used.
     */
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    match = (ttag(page) == t->present.tag.tag_word);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
 
    return match;      
}
 
/** Set up one VHPT entry.
 *
 * @param t VHPT entry to be set up.
 * @param page Virtual address of the page mapped by the entry.
 * @param asid Address space identifier of the address space to which page belongs.
 * @param frame Physical address of the frame to wich page is mapped.
 * @param flags Different flags for the mapping.
 */
void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags)
{
    region_register rr_save, rr;   
    index_t vrn;
    rid_t rid;
    __u64 tag;
 
    ASSERT(t);
 
    vrn = page >> VRN_SHIFT;
    rid = ASID2RID(asid, vrn);
   
    /*
     * Compute ttag.
     */
    rr_save.word = rr_read(vrn);
    rr.word = rr_save.word;
    rr.map.rid = rid;
    rr_write(vrn, rr.word);
    srlz_i();
    tag = ttag(page);
    rr_write(vrn, rr_save.word);
    srlz_i();
    srlz_d();
   
    /*
     * Clear the entry.
     */
    t->word[0] = 0;
    t->word[1] = 0;
    t->word[2] = 0;
    t->word[3] = 0;
   
    t->present.p = true;
    t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
    t->present.a = false;   /* not accessed */
    t->present.d = false;   /* not dirty */
    t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
    t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
    t->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
    t->present.ppn = frame >> PPN_SHIFT;
    t->present.ed = false;  /* exception not deffered */
    t->present.ps = PAGE_WIDTH;
    t->present.key = 0;
    t->present.tag.tag_word = tag;
    t->present.next = NULL;
}
 

Rev 751	Rev 762
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* Copyright (C) 2006 Jakub Vana	3	* Copyright (C) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#include <arch/mm/page.h>	30	#include <arch/mm/page.h>
31	#include <genarch/mm/page_ht.h>	31	#include <genarch/mm/page_ht.h>
32	#include <mm/asid.h>	32	#include <mm/asid.h>
33	#include <arch/mm/asid.h>	33	#include <arch/mm/asid.h>
34	#include <arch/types.h>	34	#include <arch/types.h>
35	#include <typedefs.h>	35	#include <typedefs.h>
36	#include <print.h>	36	#include <print.h>
37	#include <mm/page.h>	37	#include <mm/page.h>
38	#include <mm/frame.h>	38	#include <mm/frame.h>
39	#include <config.h>	39	#include <config.h>
40	#include <panic.h>	40	#include <panic.h>
41	#include <arch/asm.h>	41	#include <arch/asm.h>
42	#include <arch/barrier.h>	42	#include <arch/barrier.h>
43	#include <memstr.h>	43	#include <memstr.h>
44		44
45	static void set_vhpt_environment(void);	45	static void set_vhpt_environment(void);
46		46
47	/** Initialize ia64 virtual address translation subsystem. */	47	/** Initialize ia64 virtual address translation subsystem. */
48	void page_arch_init(void)	48	void page_arch_init(void)
49	{	49	{
50	page_operations = &page_ht_operations;	50	page_operations = &page_ht_operations;
51	pk_disable();	51	pk_disable();
52	set_vhpt_environment();	52	set_vhpt_environment();
53	}	53	}
54		54
55	/** Initialize VHPT and region registers. */	55	/** Initialize VHPT and region registers. */
56	void set_vhpt_environment(void)	56	void set_vhpt_environment(void)
57	{	57	{
58	region_register rr;	58	region_register rr;
59	pta_register pta;	59	pta_register pta;
60	int i;	60	int i;
61		61
62	/*	62	/*
63	* First set up kernel region register.	63	* First set up kernel region register.
64	*/	64	*/
65	rr.word = rr_read(VRN_KERNEL);	65	rr.word = rr_read(VRN_KERNEL);
66	rr.map.ve = 0; /* disable VHPT walker */	66	rr.map.ve = 0; /* disable VHPT walker */
67	rr.map.ps = PAGE_WIDTH;	67	rr.map.ps = PAGE_WIDTH;
68	rr.map.rid = ASID_KERNEL;	68	rr.map.rid = ASID_KERNEL;
69	rr_write(VRN_KERNEL, rr.word);	69	rr_write(VRN_KERNEL, rr.word);
70	srlz_i();	70	srlz_i();
71	srlz_d();	71	srlz_d();
72		72
73	/*	73	/*
74	* And invalidate the rest of region register.	74	* And invalidate the rest of region register.
75	*/	75	*/
76	for(i = 0; i < REGION_REGISTERS; i++) {	76	for(i = 0; i < REGION_REGISTERS; i++) {
77	/* skip kernel rr */	77	/* skip kernel rr */
78	if (i == VRN_KERNEL)	78	if (i == VRN_KERNEL)
79	continue;	79	continue;
80		80
81	rr.word == rr_read(i);	81	rr.word == rr_read(i);
82	rr.map.ve = 0; /* disable VHPT walker */	82	rr.map.ve = 0; /* disable VHPT walker */
83	rr.map.rid = ASID_INVALID;	83	rr.map.rid = ASID_INVALID;
84	rr_write(i, rr.word);	84	rr_write(i, rr.word);
85	srlz_i();	85	srlz_i();
86	srlz_d();	86	srlz_d();
87	}	87	}
88		88
89	/*	89	/*
90	* Allocate VHPT and invalidate all its entries.	90	* Allocate VHPT and invalidate all its entries.
91	*/	91	*/
92	page_ht = (pte_t *) frame_alloc(FRAME_KA, VHPT_WIDTH - FRAME_WIDTH, NULL);	92	page_ht = (pte_t *) frame_alloc(FRAME_KA, VHPT_WIDTH - FRAME_WIDTH, NULL, NULL);
93	memsetb((__address) page_ht, VHPT_SIZE, 0);	93	memsetb((__address) page_ht, VHPT_SIZE, 0);
94	ht_invalidate_all();	94	ht_invalidate_all();
95		95
96	/*	96	/*
97	* Set up PTA register.	97	* Set up PTA register.
98	*/	98	*/
99	pta.word = pta_read();	99	pta.word = pta_read();
100	pta.map.ve = 0; /* disable VHPT walker */	100	pta.map.ve = 0; /* disable VHPT walker */
101	pta.map.vf = 1; /* large entry format */	101	pta.map.vf = 1; /* large entry format */
102	pta.map.size = VHPT_WIDTH;	102	pta.map.size = VHPT_WIDTH;
103	pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT;	103	pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT;
104	pta_write(pta.word);	104	pta_write(pta.word);
105	srlz_i();	105	srlz_i();
106	srlz_d();	106	srlz_d();
107	}	107	}
108		108
109	/** Calculate address of collision chain from VPN and ASID.	109	/** Calculate address of collision chain from VPN and ASID.
110	*	110	*
111	* Interrupts must be disabled.	111	* Interrupts must be disabled.
112	*	112	*
113	* @param page Address of virtual page including VRN bits.	113	* @param page Address of virtual page including VRN bits.
114	* @param asid Address space identifier.	114	* @param asid Address space identifier.
115	*	115	*
116	* @return Head of VHPT collision chain for page and asid.	116	* @return Head of VHPT collision chain for page and asid.
117	*/	117	*/
118	pte_t *vhpt_hash(__address page, asid_t asid)	118	pte_t *vhpt_hash(__address page, asid_t asid)
119	{	119	{
120	region_register rr_save, rr;	120	region_register rr_save, rr;
121	index_t vrn;	121	index_t vrn;
122	rid_t rid;	122	rid_t rid;
123	pte_t *t;	123	pte_t *t;
124		124
125	vrn = page >> VRN_SHIFT;	125	vrn = page >> VRN_SHIFT;
126	rid = ASID2RID(asid, vrn);	126	rid = ASID2RID(asid, vrn);
127		127
128	rr_save.word = rr_read(vrn);	128	rr_save.word = rr_read(vrn);
129	if (rr_save.map.rid == rid) {	129	if (rr_save.map.rid == rid) {
130	/*	130	/*
131	* The RID is already in place, compute thash and return.	131	* The RID is already in place, compute thash and return.
132	*/	132	*/
133	t = (pte_t *) thash(page);	133	t = (pte_t *) thash(page);
134	return t;	134	return t;
135	}	135	}
136		136
137	/*	137	/*
138	* The RID must be written to some region register.	138	* The RID must be written to some region register.
139	* To speed things up, register indexed by vrn is used.	139	* To speed things up, register indexed by vrn is used.
140	*/	140	*/
141	rr.word = rr_save.word;	141	rr.word = rr_save.word;
142	rr.map.rid = rid;	142	rr.map.rid = rid;
143	rr_write(vrn, rr.word);	143	rr_write(vrn, rr.word);
144	srlz_i();	144	srlz_i();
145	t = (pte_t *) thash(page);	145	t = (pte_t *) thash(page);
146	rr_write(vrn, rr_save.word);	146	rr_write(vrn, rr_save.word);
147	srlz_i();	147	srlz_i();
148	srlz_d();	148	srlz_d();
149		149
150	return t;	150	return t;
151	}	151	}
152		152
153	/** Compare ASID and VPN against PTE.	153	/** Compare ASID and VPN against PTE.
154	*	154	*
155	* Interrupts must be disabled.	155	* Interrupts must be disabled.
156	*	156	*
157	* @param page Address of virtual page including VRN bits.	157	* @param page Address of virtual page including VRN bits.
158	* @param asid Address space identifier.	158	* @param asid Address space identifier.
159	*	159	*
160	* @return True if page and asid match the page and asid of t, false otherwise.	160	* @return True if page and asid match the page and asid of t, false otherwise.
161	*/	161	*/
162	bool vhpt_compare(__address page, asid_t asid, pte_t *t)	162	bool vhpt_compare(__address page, asid_t asid, pte_t *t)
163	{	163	{
164	region_register rr_save, rr;	164	region_register rr_save, rr;
165	index_t vrn;	165	index_t vrn;
166	rid_t rid;	166	rid_t rid;
167	bool match;	167	bool match;
168		168
169	ASSERT(t);	169	ASSERT(t);
170		170
171	vrn = page >> VRN_SHIFT;	171	vrn = page >> VRN_SHIFT;
172	rid = ASID2RID(asid, vrn);	172	rid = ASID2RID(asid, vrn);
173		173
174	rr_save.word = rr_read(vrn);	174	rr_save.word = rr_read(vrn);
175	if (rr_save.map.rid == rid) {	175	if (rr_save.map.rid == rid) {
176	/*	176	/*
177	* The RID is already in place, compare ttag with t and return.	177	* The RID is already in place, compare ttag with t and return.
178	*/	178	*/
179	return ttag(page) == t->present.tag.tag_word;	179	return ttag(page) == t->present.tag.tag_word;
180	}	180	}
181		181
182	/*	182	/*
183	* The RID must be written to some region register.	183	* The RID must be written to some region register.
184	* To speed things up, register indexed by vrn is used.	184	* To speed things up, register indexed by vrn is used.
185	*/	185	*/
186	rr.word = rr_save.word;	186	rr.word = rr_save.word;
187	rr.map.rid = rid;	187	rr.map.rid = rid;
188	rr_write(vrn, rr.word);	188	rr_write(vrn, rr.word);
189	srlz_i();	189	srlz_i();
190	match = (ttag(page) == t->present.tag.tag_word);	190	match = (ttag(page) == t->present.tag.tag_word);
191	rr_write(vrn, rr_save.word);	191	rr_write(vrn, rr_save.word);
192	srlz_i();	192	srlz_i();
193	srlz_d();	193	srlz_d();
194		194
195	return match;	195	return match;
196	}	196	}
197		197
198	/** Set up one VHPT entry.	198	/** Set up one VHPT entry.
199	*	199	*
200	* @param t VHPT entry to be set up.	200	* @param t VHPT entry to be set up.
201	* @param page Virtual address of the page mapped by the entry.	201	* @param page Virtual address of the page mapped by the entry.
202	* @param asid Address space identifier of the address space to which page belongs.	202	* @param asid Address space identifier of the address space to which page belongs.
203	* @param frame Physical address of the frame to wich page is mapped.	203	* @param frame Physical address of the frame to wich page is mapped.
204	* @param flags Different flags for the mapping.	204	* @param flags Different flags for the mapping.
205	*/	205	*/
206	void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags)	206	void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags)
207	{	207	{
208	region_register rr_save, rr;	208	region_register rr_save, rr;
209	index_t vrn;	209	index_t vrn;
210	rid_t rid;	210	rid_t rid;
211	__u64 tag;	211	__u64 tag;
212		212
213	ASSERT(t);	213	ASSERT(t);
214		214
215	vrn = page >> VRN_SHIFT;	215	vrn = page >> VRN_SHIFT;
216	rid = ASID2RID(asid, vrn);	216	rid = ASID2RID(asid, vrn);
217		217
218	/*	218	/*
219	* Compute ttag.	219	* Compute ttag.
220	*/	220	*/
221	rr_save.word = rr_read(vrn);	221	rr_save.word = rr_read(vrn);
222	rr.word = rr_save.word;	222	rr.word = rr_save.word;
223	rr.map.rid = rid;	223	rr.map.rid = rid;
224	rr_write(vrn, rr.word);	224	rr_write(vrn, rr.word);
225	srlz_i();	225	srlz_i();
226	tag = ttag(page);	226	tag = ttag(page);
227	rr_write(vrn, rr_save.word);	227	rr_write(vrn, rr_save.word);
228	srlz_i();	228	srlz_i();
229	srlz_d();	229	srlz_d();
230		230
231	/*	231	/*
232	* Clear the entry.	232	* Clear the entry.
233	*/	233	*/
234	t->word[0] = 0;	234	t->word[0] = 0;
235	t->word[1] = 0;	235	t->word[1] = 0;
236	t->word[2] = 0;	236	t->word[2] = 0;
237	t->word[3] = 0;	237	t->word[3] = 0;
238		238
239	t->present.p = true;	239	t->present.p = true;
240	t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;	240	t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
241	t->present.a = false; /* not accessed */	241	t->present.a = false; /* not accessed */
242	t->present.d = false; /* not dirty */	242	t->present.d = false; /* not dirty */
243	t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;	243	t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
244	t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;	244	t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
245	t->present.ar \|= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;	245	t->present.ar \|= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
246	t->present.ppn = frame >> PPN_SHIFT;	246	t->present.ppn = frame >> PPN_SHIFT;
247	t->present.ed = false; /* exception not deffered */	247	t->present.ed = false; /* exception not deffered */
248	t->present.ps = PAGE_WIDTH;	248	t->present.ps = PAGE_WIDTH;
249	t->present.key = 0;	249	t->present.key = 0;
250	t->present.tag.tag_word = tag;	250	t->present.tag.tag_word = tag;
251	t->present.next = NULL;	251	t->present.next = NULL;
252	}	252	}
253		253

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/mm/page.c – Rev 751 → 762