WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/ivt.S


#
# Copyright (C) 2005 Jakub Vana
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/stack.h>
#include <arch/register.h>
#include <arch/mm/page.h>
#include <align.h>
 
#define STACK_ITEMS		13
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
#if (STACK_ITEMS % 2 == 0)
#	define STACK_FRAME_BIAS	8
#else
#	define STACK_FRAME_BIAS 16
#endif
 
/** Partitioning of bank 0 registers. */
#define R_OFFS 		r16
#define R_HANDLER	r17
#define R_RET		r18
#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
 
/** Heavyweight interrupt handler
 *
 * This macro roughly follows steps from 1 to 19 described in
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 *
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
 * This goal is achieved by using procedure calls after RSE becomes operational.
 *
 * Some steps are skipped (enabling and disabling interrupts).
 * Some steps are not fully supported yet (e.g. interruptions
 * from userspace and floating-point context).
 *
 * @param offs Offset from the beginning of IVT.
 * @param handler Interrupt handler address.
 */
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
    .org ivt + \offs
	mov R_OFFS = \offs
	movl R_HANDLER = \handler ;;
	br heavyweight_handler
.endm
 
.global heavyweight_handler
heavyweight_handler:
    /* 1. copy interrupt registers into bank 0 */
    
	/*
	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
	 */
	mov r24 = cr.iip
	mov r25 = cr.ipsr
	mov r26 = cr.iipa
	mov r27 = cr.isr
	mov r28 = cr.ifa
	
    /* 2. preserve predicate register into bank 0 */
	mov r29 = pr ;;
	
    /* 3. switch to kernel memory stack */
    	mov r30 = cr.ipsr
	shr.u r31 = r12, VRN_SHIFT ;; 
 
	/*
	 * Set p6 to true if the stack register references kernel address space.
	 * Set p7 to false if the stack register doesn't reference kernel address space.
	 */
	cmp.eq p6, p7 = VRN_KERNEL, r31 ;;
	
	(p6) shr.u r30 = r30, PSR_CPL_SHIFT ;;
	(p6) and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
 
	/*
	 * Set p6 to true if the interrupted context executed in kernel mode.
	 * Set p7 to false if the interrupted context didn't execute in kernel mode.
	 */
	(p6) cmp.eq p6, p7 = r30, r0 ;;
	
	/*
	 * Now, p7 is true iff the stack needs to be switched to kernel stack.
	 */
	mov r30 = r12
	(p7) mov r12 = R_KSTACK ;;
	
	add r31 = -STACK_FRAME_BIAS, r12 ;;
	add r12 = -STACK_FRAME_SIZE, r12
 
    /* 4. save registers in bank 0 into memory stack */	
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
	
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
 
	st8 [r31] = r24, -8 ;;		/* save cr.iip */
	st8 [r31] = r25, -8 ;;		/* save cr.ipsr */
	st8 [r31] = r26, -8 ;;		/* save cr.iipa */
	st8 [r31] = r27, -8 ;;		/* save cr.isr */
	st8 [r31] = r28, -8 ;;		/* save cr.ifa */
 
    /* 5. RSE switch from interrupted context */
	mov r24 = ar.rsc
	mov r25 = ar.pfs
	cover
	mov r26 = cr.ifs
	
	st8 [r31] = r24, -8 ;;	/* save ar.rsc */
	st8 [r31] = r25, -8 ;;	/* save ar.pfs */
	st8 [r31] = r26, -8	/* save ar.ifs */
	
	and r30 = ~3, r24 ;;
	mov ar.rsc = r30 ;;	/* place RSE in enforced lazy mode */
	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/* assume kernel backing store */
	/* mov ar.bspstore = r28 ;; */
	
	mov r29 = ar.bsp
	
	st8 [r31] = r27, -8 ;;	/* save ar.rnat */
	st8 [r31] = r28, -8 ;;	/* save ar.bspstore */
	st8 [r31] = r29, -8 	/* save ar.bsp */
	
	mov ar.rsc = r24	/* restore RSE's setting */
	
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
	mov R_RET = b0 		/* save b0 belonging to interrupted context */
	br.call.sptk.many b0 = heavyweight_handler_inner
0:	mov b0 = R_RET		/* restore b0 belonging to the interrupted context */
 
    /* 16. RSE switch to interrupted context */
	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
 
	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
 
	mov r28 = ar.bspstore   	/* calculate loadrs (step 2) */
	ld8 r29 = [r31], +8 ;;		/* load ar.bsp */
	sub r27 = r29 , r28 ;;
	shl r27 = r27, 16
 
	mov r24 = ar.rsc ;;
	and r30 = ~3, r24 ;;
	or  r24 = r30 , r27 ;;     
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
 
	loadrs 				/* (step 3) */
 
	ld8 r28 = [r31], +8 ;;    	/* load ar.bspstore */
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
	/* mov ar.bspstore = r28 ;; */	/* (step 4) */
	/* mov ar.rnat = r27 */		/* (step 5) */
 
	mov ar.pfs = r25		/* (step 6) */
	mov cr.ifs = r26	
 
	mov ar.rsc = r24		/* (step 7) */
 
    /* 17. restore interruption state from memory stack */
	ld8 r28 = [r31], +8 ;;	/* load cr.ifa */		
	ld8 r27 = [r31], +8 ;;	/* load cr.isr */
	ld8 r26 = [r31], +8 ;;	/* load cr.iipa */
	ld8 r25 = [r31], +8 ;;	/* load cr.ipsr */
	ld8 r24 = [r31], +8 ;;	/* load cr.iip */
 
	mov cr.iip = r24
	mov cr.ipsr = r25
	mov cr.iipa = r26
	mov cr.isr = r27
	mov cr.ifa = r28
 
    /* 18. restore predicate registers from memory stack */
	ld8 r29 = [r31], +8 ;;	/* load predicate registers */
	mov pr = r29
	
    /* 19. return from interruption */
    	ld8 r12 = [r31]		/* load stack pointer */ 
	rfi ;;
 
.global heavyweight_handler_inner
heavyweight_handler_inner:
	/*
	 * From this point, the rest of the interrupted context
	 * will be preserved in stacked registers and backing store.
	 */
	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
	
	/* bank 0 is going to be shadowed, copy essential data from there */
	mov loc1 = R_RET	/* b0 belonging to interrupted context */
	mov loc2 = R_HANDLER
	mov out0 = R_OFFS
	
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
    /* 6. switch to bank 1 and reenable PSR.ic */
	ssm PSR_IC_MASK
	bsw.1 ;;
	srlz.d
	
    /* 7. preserve branch and application registers */
    	mov loc3 = ar.unat
	mov loc4 = ar.lc
	mov loc5 = ar.ec
	mov loc6 = ar.ccv
	mov loc7 = ar.csd
	mov loc8 = ar.ssd
	
	mov loc9 = b0
	mov loc10 = b1
	mov loc11 = b2
	mov loc12 = b3
	mov loc13 = b4
	mov loc14 = b5
	mov loc15 = b6
	mov loc16 = b7
	
    /* 8. preserve general and floating-point registers */
	/* TODO: save floating-point context */
	mov loc17 = r1
	mov loc18 = r2
	mov loc19 = r3
	mov loc20 = r4
	mov loc21 = r5
	mov loc22 = r6
	mov loc23 = r7
	mov loc24 = r8
	mov loc25 = r9
	mov loc26 = r10
	mov loc27 = r11
	/* skip r12 (stack pointer) */
	mov loc28 = r13
	mov loc29 = r14
	mov loc30 = r15
	mov loc31 = r16
	mov loc32 = r17
	mov loc33 = r18
	mov loc34 = r19
	mov loc35 = r20
	mov loc36 = r21
	mov loc37 = r22
	mov loc38 = r23
	mov loc39 = r24
	mov loc40 = r25
	mov loc41 = r26
	mov loc42 = r27
	mov loc43 = r28
	mov loc44 = r29
	mov loc45 = r30
	mov loc46 = r31
    
    /* 9. skipped (will not enable interrupts) */
	/*
    	 * ssm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 10. call handler */
    	mov b1 = loc2
	br.call.sptk.many b0 = b1
 
    /* 11. return from handler */
0:
	
    /* 12. skipped (will not disable interrupts) */
	/*
    	 * rsm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 13. restore general and floating-point registers */
	/* TODO: restore floating-point context */
	mov r1 = loc17
	mov r2 = loc18
	mov r3 = loc19
	mov r4 = loc20
	mov r5 = loc21
	mov r6 = loc22
	mov r7 = loc23
	mov r8 = loc24
	mov r9 = loc25
	mov r10 = loc26
	mov r11 = loc27
	/* skip r12 (stack pointer) */
	mov r13 = loc28
	mov r14 = loc29
	mov r15 = loc30
	mov r16 = loc31
	mov r17 = loc32
	mov r18 = loc33
	mov r19 = loc34
	mov r20 = loc35
	mov r21 = loc36
	mov r22 = loc37
	mov r23 = loc38
	mov r24 = loc39
	mov r25 = loc40
	mov r26 = loc41 
	mov r27 = loc42
	mov r28 = loc43
	mov r29 = loc44
	mov r30 = loc45
	mov r31 = loc46
	
    /* 14. restore branch and application registers */
    	mov ar.unat = loc3
	mov ar.lc = loc4
	mov ar.ec = loc5
	mov ar.ccv = loc6
	mov ar.csd = loc7
	mov ar.ssd = loc8
	
	mov b0 = loc9
	mov b1 = loc10
	mov b2 = loc11
	mov b3 = loc12
	mov b4 = loc13
	mov b5 = loc14
	mov b6 = loc15
	mov b7 = loc16
	
    /* 15. disable PSR.ic and switch to bank 0 */
	rsm PSR_IC_MASK
	bsw.0 ;;
	srlz.d
 
	mov R_RET = loc1
	mov ar.pfs = loc0
	br.ret.sptk.many b0
 
.global ivt
.align 32768
ivt:
	HEAVYWEIGHT_HANDLER 0x0000
	HEAVYWEIGHT_HANDLER 0x0400
	HEAVYWEIGHT_HANDLER 0x0800
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1800
	HEAVYWEIGHT_HANDLER 0x1c00
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
	HEAVYWEIGHT_HANDLER 0x3400
	HEAVYWEIGHT_HANDLER 0x3800
	HEAVYWEIGHT_HANDLER 0x3c00
	HEAVYWEIGHT_HANDLER 0x4000
	HEAVYWEIGHT_HANDLER 0x4400
	HEAVYWEIGHT_HANDLER 0x4800
	HEAVYWEIGHT_HANDLER 0x4c00
 
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
	HEAVYWEIGHT_HANDLER 0x5100
	HEAVYWEIGHT_HANDLER 0x5200
	HEAVYWEIGHT_HANDLER 0x5300
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
	HEAVYWEIGHT_HANDLER 0x5500
	HEAVYWEIGHT_HANDLER 0x5600
	HEAVYWEIGHT_HANDLER 0x5700
	HEAVYWEIGHT_HANDLER 0x5800
	HEAVYWEIGHT_HANDLER 0x5900
	HEAVYWEIGHT_HANDLER 0x5a00
	HEAVYWEIGHT_HANDLER 0x5b00
	HEAVYWEIGHT_HANDLER 0x5c00
	HEAVYWEIGHT_HANDLER 0x5d00
	HEAVYWEIGHT_HANDLER 0x5e00
	HEAVYWEIGHT_HANDLER 0x5f00
	
	HEAVYWEIGHT_HANDLER 0x6000
	HEAVYWEIGHT_HANDLER 0x6100
	HEAVYWEIGHT_HANDLER 0x6200
	HEAVYWEIGHT_HANDLER 0x6300
	HEAVYWEIGHT_HANDLER 0x6400
	HEAVYWEIGHT_HANDLER 0x6500
	HEAVYWEIGHT_HANDLER 0x6600
	HEAVYWEIGHT_HANDLER 0x6700
	HEAVYWEIGHT_HANDLER 0x6800
	HEAVYWEIGHT_HANDLER 0x6900
	HEAVYWEIGHT_HANDLER 0x6a00
	HEAVYWEIGHT_HANDLER 0x6b00
	HEAVYWEIGHT_HANDLER 0x6c00
	HEAVYWEIGHT_HANDLER 0x6d00
	HEAVYWEIGHT_HANDLER 0x6e00
	HEAVYWEIGHT_HANDLER 0x6f00
 
	HEAVYWEIGHT_HANDLER 0x7000
	HEAVYWEIGHT_HANDLER 0x7100
	HEAVYWEIGHT_HANDLER 0x7200
	HEAVYWEIGHT_HANDLER 0x7300
	HEAVYWEIGHT_HANDLER 0x7400
	HEAVYWEIGHT_HANDLER 0x7500
	HEAVYWEIGHT_HANDLER 0x7600
	HEAVYWEIGHT_HANDLER 0x7700
	HEAVYWEIGHT_HANDLER 0x7800
	HEAVYWEIGHT_HANDLER 0x7900
	HEAVYWEIGHT_HANDLER 0x7a00
	HEAVYWEIGHT_HANDLER 0x7b00
	HEAVYWEIGHT_HANDLER 0x7c00
	HEAVYWEIGHT_HANDLER 0x7d00
	HEAVYWEIGHT_HANDLER 0x7e00
	HEAVYWEIGHT_HANDLER 0x7f00
 

Rev 911	Rev 912
1	#	1	#
2	# Copyright (C) 2005 Jakub Vana	2	# Copyright (C) 2005 Jakub Vana
3	# Copyright (C) 2005 Jakub Jermar	3	# Copyright (C) 2005 Jakub Jermar
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <arch/stack.h>	30	#include <arch/stack.h>
31	#include <arch/register.h>	31	#include <arch/register.h>
-		32	#include <arch/mm/page.h>
-		33	#include <align.h>
32		34
33	#define STACK_ITEMS 12	35	#define STACK_ITEMS 13
34	#define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)	36	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
35		37
36	#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)	38	#if (STACK_ITEMS % 2 == 0)
-		39	# define STACK_FRAME_BIAS 8
-		40	#else
37	#error Memory stack must be 16-byte aligned.	41	# define STACK_FRAME_BIAS 16
38	#endif	42	#endif
39		43
40	/** Partitioning of bank 0 registers. */	44	/** Partitioning of bank 0 registers. */
41	#define R_OFFS r16	45	#define R_OFFS r16
42	#define R_HANDLER r17	46	#define R_HANDLER r17
43	#define R_RET r18	47	#define R_RET r18
44	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */	48	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
45		49
46	/** Heavyweight interrupt handler	50	/** Heavyweight interrupt handler
47	*	51	*
48	* This macro roughly follows steps from 1 to 19 described in	52	* This macro roughly follows steps from 1 to 19 described in
49	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.	53	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
50	*	54	*
51	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).	55	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
52	* This goal is achieved by using procedure calls after RSE becomes operational.	56	* This goal is achieved by using procedure calls after RSE becomes operational.
53	*	57	*
54	* Some steps are skipped (enabling and disabling interrupts).	58	* Some steps are skipped (enabling and disabling interrupts).
55	* Some steps are not fully supported yet (e.g. interruptions	59	* Some steps are not fully supported yet (e.g. interruptions
56	* from userspace and floating-point context).	60	* from userspace and floating-point context).
57	*	61	*
58	* @param offs Offset from the beginning of IVT.	62	* @param offs Offset from the beginning of IVT.
59	* @param handler Interrupt handler address.	63	* @param handler Interrupt handler address.
60	*/	64	*/
61	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler	65	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
62	.org ivt + \offs	66	.org ivt + \offs
63	mov R_OFFS = \offs	67	mov R_OFFS = \offs
64	movl R_HANDLER = \handler ;;	68	movl R_HANDLER = \handler ;;
65	br heavyweight_handler	69	br heavyweight_handler
66	.endm	70	.endm
67		71
68	.global heavyweight_handler	72	.global heavyweight_handler
69	heavyweight_handler:	73	heavyweight_handler:
70	/* 1. copy interrupt registers into bank 0 */	74	/* 1. copy interrupt registers into bank 0 */
71		75
72	/*	76	/*
73	* Note that r24-r31 from bank0 can be used only as long as PSR.ic = 0.	77	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
74	*/	78	*/
75	mov r24 = cr.iip	79	mov r24 = cr.iip
76	mov r25 = cr.ipsr	80	mov r25 = cr.ipsr
77	mov r26 = cr.iipa	81	mov r26 = cr.iipa
78	mov r27 = cr.isr	82	mov r27 = cr.isr
79	mov r28 = cr.ifa	83	mov r28 = cr.ifa
80		84
81	/* 2. preserve predicate register into bank 0 */	85	/* 2. preserve predicate register into bank 0 */
82	mov r29 = pr ;;	86	mov r29 = pr ;;
83		87
84	/* 3. switch to kernel memory stack */	88	/* 3. switch to kernel memory stack */
-		89	mov r30 = cr.ipsr
-		90	shr.u r31 = r12, VRN_SHIFT ;;
-		91
-		92	/*
85	/* TODO: support interruptions from userspace */	93	* Set p6 to true if the stack register references kernel address space.
-		94	* Set p7 to false if the stack register doesn't reference kernel address space.
-		95	*/
86	/* assume kernel stack */	96	cmp.eq p6, p7 = VRN_KERNEL, r31 ;;
87		97
-		98	(p6) shr.u r30 = r30, PSR_CPL_SHIFT ;;
-		99	(p6) and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
-		100
-		101	/*
-		102	* Set p6 to true if the interrupted context executed in kernel mode.
-		103	* Set p7 to false if the interrupted context didn't execute in kernel mode.
-		104	*/
-		105	(p6) cmp.eq p6, p7 = r30, r0 ;;
-		106
-		107	/*
-		108	* Now, p7 is true iff the stack needs to be switched to kernel stack.
-		109	*/
-		110	mov r30 = r12
-		111	(p7) mov r12 = R_KSTACK ;;
-		112
88	add r31 = -8, r12 ;;	113	add r31 = -STACK_FRAME_BIAS, r12 ;;
89	add r12 = -STACK_FRAME_SIZE, r12	114	add r12 = -STACK_FRAME_SIZE, r12
90		115
91	/* 4. save registers in bank 0 into memory stack */	116	/* 4. save registers in bank 0 into memory stack */
-		117	st8 [r31] = r30, -8 ;; / save old stack pointer /
-		118
92	st8 [r31] = r29, -8 ;; / save predicate registers /	119	st8 [r31] = r29, -8 ;; / save predicate registers /
93		120
94	st8 [r31] = r24, -8 ;; / save cr.iip /	121	st8 [r31] = r24, -8 ;; / save cr.iip /
95	st8 [r31] = r25, -8 ;; / save cr.ipsr /	122	st8 [r31] = r25, -8 ;; / save cr.ipsr /
96	st8 [r31] = r26, -8 ;; / save cr.iipa /	123	st8 [r31] = r26, -8 ;; / save cr.iipa /
97	st8 [r31] = r27, -8 ;; / save cr.isr /	124	st8 [r31] = r27, -8 ;; / save cr.isr /
98	st8 [r31] = r28, -8 /* save cr.ifa */	125	st8 [r31] = r28, -8 ;; / save cr.ifa /
99		126
100	/* 5. RSE switch from interrupted context */	127	/* 5. RSE switch from interrupted context */
101	mov r24 = ar.rsc	128	mov r24 = ar.rsc
102	mov r25 = ar.pfs	129	mov r25 = ar.pfs
103	cover	130	cover
104	mov r26 = cr.ifs	131	mov r26 = cr.ifs
105		132
106	st8 [r31] = r24, -8;; /* save ar.rsc */	133	st8 [r31] = r24, -8 ;; / save ar.rsc /
107	st8 [r31] = r25, -8;; / save ar.pfs /	134	st8 [r31] = r25, -8 ;; / save ar.pfs /
108	st8 [r31] = r26, -8 /* save ar.ifs */	135	st8 [r31] = r26, -8 /* save ar.ifs */
109		136
110	and r30 = ~3, r24 ;;	137	and r30 = ~3, r24 ;;
111	mov ar.rsc = r30 ;; / place RSE in enforced lazy mode /	138	mov ar.rsc = r30 ;; / place RSE in enforced lazy mode /
112		139
113	mov r27 = ar.rnat	140	mov r27 = ar.rnat
114	mov r28 = ar.bspstore ;;	141	mov r28 = ar.bspstore ;;
115		142
116	/* assume kernel backing store */	143	/* assume kernel backing store */
117	/* mov ar.bspstore = r28 ;; /*	144	/* mov ar.bspstore = r28 ;; /*
118		145
119	mov r29 = ar.bsp	146	mov r29 = ar.bsp
120		147
121	st8 [r31] = r27, -8 ;; / save ar.rnat /	148	st8 [r31] = r27, -8 ;; / save ar.rnat /
122	st8 [r31] = r28, -8 ;; / save ar.bspstore /	149	st8 [r31] = r28, -8 ;; / save ar.bspstore /
123	st8 [r31] = r29, -8 /* save ar.bsp */	150	st8 [r31] = r29, -8 /* save ar.bsp */
124		151
125	mov ar.rsc = r24 /* restore RSE's setting */	152	mov ar.rsc = r24 /* restore RSE's setting */
126		153
127	/* steps 6 - 15 are done by heavyweight_handler_inner() */	154	/* steps 6 - 15 are done by heavyweight_handler_inner() */
128	mov R_RET = b0 /* save b0 belonging to interrupted context */	155	mov R_RET = b0 /* save b0 belonging to interrupted context */
129	br.call.sptk.many b0 = heavyweight_handler_inner	156	br.call.sptk.many b0 = heavyweight_handler_inner
130	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */	157	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
131		158
132	/* 16. RSE switch to interrupted context */	159	/* 16. RSE switch to interrupted context */
133	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */	160	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
134		161
135	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;	162	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
136		163
137	mov r28 = ar.bspstore /* calculate loadrs (step 2) */	164	mov r28 = ar.bspstore /* calculate loadrs (step 2) */
138	ld8 r29 = [r31], +8 ;; / load ar.bsp /	165	ld8 r29 = [r31], +8 ;; / load ar.bsp /
139	sub r27 = r29 , r28 ;;	166	sub r27 = r29 , r28 ;;
140	shl r27 = r27, 16	167	shl r27 = r27, 16
141		168
142	mov r24 = ar.rsc ;;	169	mov r24 = ar.rsc ;;
143	and r30 = ~3, r24 ;;	170	and r30 = ~3, r24 ;;
144	or r24 = r30 , r27 ;;	171	or r24 = r30 , r27 ;;
145	mov ar.rsc = r24 ;; / place RSE in enforced lazy mode /	172	mov ar.rsc = r24 ;; / place RSE in enforced lazy mode /
146		173
147	loadrs /* (step 3) */	174	loadrs /* (step 3) */
148		175
149	ld8 r28 = [r31], +8 ;; / load ar.bspstore /	176	ld8 r28 = [r31], +8 ;; / load ar.bspstore /
150	ld8 r27 = [r31], +8 ;; / load ar.rnat /	177	ld8 r27 = [r31], +8 ;; / load ar.rnat /
151	ld8 r26 = [r31], +8 ;; / load cr.ifs /	178	ld8 r26 = [r31], +8 ;; / load cr.ifs /
152	ld8 r25 = [r31], +8 ;; / load ar.pfs /	179	ld8 r25 = [r31], +8 ;; / load ar.pfs /
153	ld8 r24 = [r31], +8 ;; / load ar.rsc /	180	ld8 r24 = [r31], +8 ;; / load ar.rsc /
154		181
155	/* mov ar.bspstore = r28 ;; / /* (step 4) /	182	/* mov ar.bspstore = r28 ;; / /* (step 4) /
156	/ mov ar.rnat = r27 / / (step 5) /	183	/ mov ar.rnat = r27 / / (step 5) /
157		184
158	mov ar.pfs = r25 /* (step 6) */	185	mov ar.pfs = r25 /* (step 6) */
159	mov cr.ifs = r26	186	mov cr.ifs = r26
160		187
161	mov ar.rsc = r24 /* (step 7) */	188	mov ar.rsc = r24 /* (step 7) */
162		189
163	/* 17. restore interruption state from memory stack */	190	/* 17. restore interruption state from memory stack */
164	ld8 r28 = [r31], +8 ;; / load cr.ifa /	191	ld8 r28 = [r31], +8 ;; / load cr.ifa /
165	ld8 r27 = [r31], +8 ;; / load cr.isr /	192	ld8 r27 = [r31], +8 ;; / load cr.isr /
166	ld8 r26 = [r31], +8 ;; / load cr.iipa /	193	ld8 r26 = [r31], +8 ;; / load cr.iipa /
167	ld8 r25 = [r31], +8 ;; / load cr.ipsr /	194	ld8 r25 = [r31], +8 ;; / load cr.ipsr /
168	ld8 r24 = [r31], +8 ;; / load cr.iip /	195	ld8 r24 = [r31], +8 ;; / load cr.iip /
169		196
170	mov cr.iip = r24	197	mov cr.iip = r24
171	mov cr.ipsr = r25	198	mov cr.ipsr = r25
172	mov cr.iipa = r26	199	mov cr.iipa = r26
173	mov cr.isr = r27	200	mov cr.isr = r27
174	mov cr.ifa = r28	201	mov cr.ifa = r28
175		202
176	/* 18. restore predicate registers from memory stack */	203	/* 18. restore predicate registers from memory stack */
177	ld8 r29 = [r31] , -8 ;; / load predicate registers /	204	ld8 r29 = [r31], +8 ;; / load predicate registers /
178	mov pr = r29	205	mov pr = r29
179		206
180	/* 19. return from interruption */	207	/* 19. return from interruption */
181	add r12 = STACK_FRAME_SIZE, r12	208	ld8 r12 = [r31] /* load stack pointer */
182	rfi ;;	209	rfi ;;
183		210
184	.global heavyweight_handler_inner	211	.global heavyweight_handler_inner
185	heavyweight_handler_inner:	212	heavyweight_handler_inner:
186	/*	213	/*
187	* From this point, the rest of the interrupted context	214	* From this point, the rest of the interrupted context
188	* will be preserved in stacked registers and backing store.	215	* will be preserved in stacked registers and backing store.
189	*/	216	*/
190	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;	217	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
191		218
192	/* bank 0 is going to be shadowed, copy essential data from there */	219	/* bank 0 is going to be shadowed, copy essential data from there */
193	mov loc1 = R_RET /* b0 belonging to interrupted context */	220	mov loc1 = R_RET /* b0 belonging to interrupted context */
194	mov loc2 = R_HANDLER	221	mov loc2 = R_HANDLER
195	mov out0 = R_OFFS	222	mov out0 = R_OFFS
196		223
197	add out1 = STACK_SCRATCH_AREA_SIZE, r12	224	add out1 = STACK_SCRATCH_AREA_SIZE, r12
198		225
199	/* 6. switch to bank 1 and reenable PSR.ic */	226	/* 6. switch to bank 1 and reenable PSR.ic */
200	ssm PSR_IC_MASK	227	ssm PSR_IC_MASK
201	bsw.1 ;;	228	bsw.1 ;;
202	srlz.d	229	srlz.d
203		230
204	/* 7. preserve branch and application registers */	231	/* 7. preserve branch and application registers */
205	mov loc3 = ar.unat	232	mov loc3 = ar.unat
206	mov loc4 = ar.lc	233	mov loc4 = ar.lc
207	mov loc5 = ar.ec	234	mov loc5 = ar.ec
208	mov loc6 = ar.ccv	235	mov loc6 = ar.ccv
209	mov loc7 = ar.csd	236	mov loc7 = ar.csd
210	mov loc8 = ar.ssd	237	mov loc8 = ar.ssd
211		238
212	mov loc9 = b0	239	mov loc9 = b0
213	mov loc10 = b1	240	mov loc10 = b1
214	mov loc11 = b2	241	mov loc11 = b2
215	mov loc12 = b3	242	mov loc12 = b3
216	mov loc13 = b4	243	mov loc13 = b4
217	mov loc14 = b5	244	mov loc14 = b5
218	mov loc15 = b6	245	mov loc15 = b6
219	mov loc16 = b7	246	mov loc16 = b7
220		247
221	/* 8. preserve general and floating-point registers */	248	/* 8. preserve general and floating-point registers */
222	/* TODO: save floating-point context */	249	/* TODO: save floating-point context */
223	mov loc17 = r1	250	mov loc17 = r1
224	mov loc18 = r2	251	mov loc18 = r2
225	mov loc19 = r3	252	mov loc19 = r3
226	mov loc20 = r4	253	mov loc20 = r4
227	mov loc21 = r5	254	mov loc21 = r5
228	mov loc22 = r6	255	mov loc22 = r6
229	mov loc23 = r7	256	mov loc23 = r7
230	mov loc24 = r8	257	mov loc24 = r8
231	mov loc25 = r9	258	mov loc25 = r9
232	mov loc26 = r10	259	mov loc26 = r10
233	mov loc27 = r11	260	mov loc27 = r11
234	/* skip r12 (stack pointer) */	261	/* skip r12 (stack pointer) */
235	mov loc28 = r13	262	mov loc28 = r13
236	mov loc29 = r14	263	mov loc29 = r14
237	mov loc30 = r15	264	mov loc30 = r15
238	mov loc31 = r16	265	mov loc31 = r16
239	mov loc32 = r17	266	mov loc32 = r17
240	mov loc33 = r18	267	mov loc33 = r18
241	mov loc34 = r19	268	mov loc34 = r19
242	mov loc35 = r20	269	mov loc35 = r20
243	mov loc36 = r21	270	mov loc36 = r21
244	mov loc37 = r22	271	mov loc37 = r22
245	mov loc38 = r23	272	mov loc38 = r23
246	mov loc39 = r24	273	mov loc39 = r24
247	mov loc40 = r25	274	mov loc40 = r25
248	mov loc41 = r26	275	mov loc41 = r26
249	mov loc42 = r27	276	mov loc42 = r27
250	mov loc43 = r28	277	mov loc43 = r28
251	mov loc44 = r29	278	mov loc44 = r29
252	mov loc45 = r30	279	mov loc45 = r30
253	mov loc46 = r31	280	mov loc46 = r31
254		281
255	/* 9. skipped (will not enable interrupts) */	282	/* 9. skipped (will not enable interrupts) */
256	/*	283	/*
257	* ssm PSR_I_MASK	284	* ssm PSR_I_MASK
258	* ;;	285	* ;;
259	* srlz.d	286	* srlz.d
260	*/	287	*/
261		288
262	/* 10. call handler */	289	/* 10. call handler */
263	mov b1 = loc2	290	mov b1 = loc2
264	br.call.sptk.many b0 = b1	291	br.call.sptk.many b0 = b1
265		292
266	/* 11. return from handler */	293	/* 11. return from handler */
267	0:	294	0:
268		295
269	/* 12. skipped (will not disable interrupts) */	296	/* 12. skipped (will not disable interrupts) */
270	/*	297	/*
271	* rsm PSR_I_MASK	298	* rsm PSR_I_MASK
272	* ;;	299	* ;;
273	* srlz.d	300	* srlz.d
274	*/	301	*/
275		302
276	/* 13. restore general and floating-point registers */	303	/* 13. restore general and floating-point registers */
277	/* TODO: restore floating-point context */	304	/* TODO: restore floating-point context */
278	mov r1 = loc17	305	mov r1 = loc17
279	mov r2 = loc18	306	mov r2 = loc18
280	mov r3 = loc19	307	mov r3 = loc19
281	mov r4 = loc20	308	mov r4 = loc20
282	mov r5 = loc21	309	mov r5 = loc21
283	mov r6 = loc22	310	mov r6 = loc22
284	mov r7 = loc23	311	mov r7 = loc23
285	mov r8 = loc24	312	mov r8 = loc24
286	mov r9 = loc25	313	mov r9 = loc25
287	mov r10 = loc26	314	mov r10 = loc26
288	mov r11 = loc27	315	mov r11 = loc27
289	/* skip r12 (stack pointer) */	316	/* skip r12 (stack pointer) */
290	mov r13 = loc28	317	mov r13 = loc28
291	mov r14 = loc29	318	mov r14 = loc29
292	mov r15 = loc30	319	mov r15 = loc30
293	mov r16 = loc31	320	mov r16 = loc31
294	mov r17 = loc32	321	mov r17 = loc32
295	mov r18 = loc33	322	mov r18 = loc33
296	mov r19 = loc34	323	mov r19 = loc34
297	mov r20 = loc35	324	mov r20 = loc35
298	mov r21 = loc36	325	mov r21 = loc36
299	mov r22 = loc37	326	mov r22 = loc37
300	mov r23 = loc38	327	mov r23 = loc38
301	mov r24 = loc39	328	mov r24 = loc39
302	mov r25 = loc40	329	mov r25 = loc40
303	mov r26 = loc41	330	mov r26 = loc41
304	mov r27 = loc42	331	mov r27 = loc42
305	mov r28 = loc43	332	mov r28 = loc43
306	mov r29 = loc44	333	mov r29 = loc44
307	mov r30 = loc45	334	mov r30 = loc45
308	mov r31 = loc46	335	mov r31 = loc46
309		336
310	/* 14. restore branch and application registers */	337	/* 14. restore branch and application registers */
311	mov ar.unat = loc3	338	mov ar.unat = loc3
312	mov ar.lc = loc4	339	mov ar.lc = loc4
313	mov ar.ec = loc5	340	mov ar.ec = loc5
314	mov ar.ccv = loc6	341	mov ar.ccv = loc6
315	mov ar.csd = loc7	342	mov ar.csd = loc7
316	mov ar.ssd = loc8	343	mov ar.ssd = loc8
317		344
318	mov b0 = loc9	345	mov b0 = loc9
319	mov b1 = loc10	346	mov b1 = loc10
320	mov b2 = loc11	347	mov b2 = loc11
321	mov b3 = loc12	348	mov b3 = loc12
322	mov b4 = loc13	349	mov b4 = loc13
323	mov b5 = loc14	350	mov b5 = loc14
324	mov b6 = loc15	351	mov b6 = loc15
325	mov b7 = loc16	352	mov b7 = loc16
326		353
327	/* 15. disable PSR.ic and switch to bank 0 */	354	/* 15. disable PSR.ic and switch to bank 0 */
328	rsm PSR_IC_MASK	355	rsm PSR_IC_MASK
329	bsw.0 ;;	356	bsw.0 ;;
330	srlz.d	357	srlz.d
331		358
332	mov R_RET = loc1	359	mov R_RET = loc1
333	mov ar.pfs = loc0	360	mov ar.pfs = loc0
334	br.ret.sptk.many b0	361	br.ret.sptk.many b0
335		362
336	.global ivt	363	.global ivt
337	.align 32768	364	.align 32768
338	ivt:	365	ivt:
339	HEAVYWEIGHT_HANDLER 0x0000	366	HEAVYWEIGHT_HANDLER 0x0000
340	HEAVYWEIGHT_HANDLER 0x0400	367	HEAVYWEIGHT_HANDLER 0x0400
341	HEAVYWEIGHT_HANDLER 0x0800	368	HEAVYWEIGHT_HANDLER 0x0800
342	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault	369	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
343	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault	370	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
344	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault	371	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
345	HEAVYWEIGHT_HANDLER 0x1800	372	HEAVYWEIGHT_HANDLER 0x1800
346	HEAVYWEIGHT_HANDLER 0x1c00	373	HEAVYWEIGHT_HANDLER 0x1c00
347	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault	374	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
348	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault	375	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
349	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault	376	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
350	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction	377	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
351	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */	378	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
352	HEAVYWEIGHT_HANDLER 0x3400	379	HEAVYWEIGHT_HANDLER 0x3400
353	HEAVYWEIGHT_HANDLER 0x3800	380	HEAVYWEIGHT_HANDLER 0x3800
354	HEAVYWEIGHT_HANDLER 0x3c00	381	HEAVYWEIGHT_HANDLER 0x3c00
355	HEAVYWEIGHT_HANDLER 0x4000	382	HEAVYWEIGHT_HANDLER 0x4000
356	HEAVYWEIGHT_HANDLER 0x4400	383	HEAVYWEIGHT_HANDLER 0x4400
357	HEAVYWEIGHT_HANDLER 0x4800	384	HEAVYWEIGHT_HANDLER 0x4800
358	HEAVYWEIGHT_HANDLER 0x4c00	385	HEAVYWEIGHT_HANDLER 0x4c00
359		386
360	HEAVYWEIGHT_HANDLER 0x5000 page_not_present	387	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
361	HEAVYWEIGHT_HANDLER 0x5100	388	HEAVYWEIGHT_HANDLER 0x5100
362	HEAVYWEIGHT_HANDLER 0x5200	389	HEAVYWEIGHT_HANDLER 0x5200
363	HEAVYWEIGHT_HANDLER 0x5300	390	HEAVYWEIGHT_HANDLER 0x5300
364	HEAVYWEIGHT_HANDLER 0x5400 general_exception	391	HEAVYWEIGHT_HANDLER 0x5400 general_exception
365	HEAVYWEIGHT_HANDLER 0x5500	392	HEAVYWEIGHT_HANDLER 0x5500
366	HEAVYWEIGHT_HANDLER 0x5600	393	HEAVYWEIGHT_HANDLER 0x5600
367	HEAVYWEIGHT_HANDLER 0x5700	394	HEAVYWEIGHT_HANDLER 0x5700
368	HEAVYWEIGHT_HANDLER 0x5800	395	HEAVYWEIGHT_HANDLER 0x5800
369	HEAVYWEIGHT_HANDLER 0x5900	396	HEAVYWEIGHT_HANDLER 0x5900
370	HEAVYWEIGHT_HANDLER 0x5a00	397	HEAVYWEIGHT_HANDLER 0x5a00
371	HEAVYWEIGHT_HANDLER 0x5b00	398	HEAVYWEIGHT_HANDLER 0x5b00
372	HEAVYWEIGHT_HANDLER 0x5c00	399	HEAVYWEIGHT_HANDLER 0x5c00
373	HEAVYWEIGHT_HANDLER 0x5d00	400	HEAVYWEIGHT_HANDLER 0x5d00
374	HEAVYWEIGHT_HANDLER 0x5e00	401	HEAVYWEIGHT_HANDLER 0x5e00
375	HEAVYWEIGHT_HANDLER 0x5f00	402	HEAVYWEIGHT_HANDLER 0x5f00
376		403
377	HEAVYWEIGHT_HANDLER 0x6000	404	HEAVYWEIGHT_HANDLER 0x6000
378	HEAVYWEIGHT_HANDLER 0x6100	405	HEAVYWEIGHT_HANDLER 0x6100
379	HEAVYWEIGHT_HANDLER 0x6200	406	HEAVYWEIGHT_HANDLER 0x6200
380	HEAVYWEIGHT_HANDLER 0x6300	407	HEAVYWEIGHT_HANDLER 0x6300
381	HEAVYWEIGHT_HANDLER 0x6400	408	HEAVYWEIGHT_HANDLER 0x6400
382	HEAVYWEIGHT_HANDLER 0x6500	409	HEAVYWEIGHT_HANDLER 0x6500
383	HEAVYWEIGHT_HANDLER 0x6600	410	HEAVYWEIGHT_HANDLER 0x6600
384	HEAVYWEIGHT_HANDLER 0x6700	411	HEAVYWEIGHT_HANDLER 0x6700
385	HEAVYWEIGHT_HANDLER 0x6800	412	HEAVYWEIGHT_HANDLER 0x6800
386	HEAVYWEIGHT_HANDLER 0x6900	413	HEAVYWEIGHT_HANDLER 0x6900
387	HEAVYWEIGHT_HANDLER 0x6a00	414	HEAVYWEIGHT_HANDLER 0x6a00
388	HEAVYWEIGHT_HANDLER 0x6b00	415	HEAVYWEIGHT_HANDLER 0x6b00
389	HEAVYWEIGHT_HANDLER 0x6c00	416	HEAVYWEIGHT_HANDLER 0x6c00
390	HEAVYWEIGHT_HANDLER 0x6d00	417	HEAVYWEIGHT_HANDLER 0x6d00
391	HEAVYWEIGHT_HANDLER 0x6e00	418	HEAVYWEIGHT_HANDLER 0x6e00
392	HEAVYWEIGHT_HANDLER 0x6f00	419	HEAVYWEIGHT_HANDLER 0x6f00
393		420
394	HEAVYWEIGHT_HANDLER 0x7000	421	HEAVYWEIGHT_HANDLER 0x7000
395	HEAVYWEIGHT_HANDLER 0x7100	422	HEAVYWEIGHT_HANDLER 0x7100
396	HEAVYWEIGHT_HANDLER 0x7200	423	HEAVYWEIGHT_HANDLER 0x7200
397	HEAVYWEIGHT_HANDLER 0x7300	424	HEAVYWEIGHT_HANDLER 0x7300
398	HEAVYWEIGHT_HANDLER 0x7400	425	HEAVYWEIGHT_HANDLER 0x7400
399	HEAVYWEIGHT_HANDLER 0x7500	426	HEAVYWEIGHT_HANDLER 0x7500
400	HEAVYWEIGHT_HANDLER 0x7600	427	HEAVYWEIGHT_HANDLER 0x7600
401	HEAVYWEIGHT_HANDLER 0x7700	428	HEAVYWEIGHT_HANDLER 0x7700
402	HEAVYWEIGHT_HANDLER 0x7800	429	HEAVYWEIGHT_HANDLER 0x7800
403	HEAVYWEIGHT_HANDLER 0x7900	430	HEAVYWEIGHT_HANDLER 0x7900
404	HEAVYWEIGHT_HANDLER 0x7a00	431	HEAVYWEIGHT_HANDLER 0x7a00
405	HEAVYWEIGHT_HANDLER 0x7b00	432	HEAVYWEIGHT_HANDLER 0x7b00
406	HEAVYWEIGHT_HANDLER 0x7c00	433	HEAVYWEIGHT_HANDLER 0x7c00
407	HEAVYWEIGHT_HANDLER 0x7d00	434	HEAVYWEIGHT_HANDLER 0x7d00
408	HEAVYWEIGHT_HANDLER 0x7e00	435	HEAVYWEIGHT_HANDLER 0x7e00
409	HEAVYWEIGHT_HANDLER 0x7f00	436	HEAVYWEIGHT_HANDLER 0x7f00
410		437

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(root)/kernel/trunk/arch/ia64/src/ivt.S – Rev 911 → 912