WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/ivt.S


#
# Copyright (C) 2005 Jakub Vana
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/stack.h>
#include <arch/register.h>
#include <arch/mm/page.h>
#include <align.h>
 
#define STACK_ITEMS		18
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
#if (STACK_ITEMS % 2 == 0)
#	define STACK_FRAME_BIAS	8
#else
#	define STACK_FRAME_BIAS 16
#endif
 
/** Partitioning of bank 0 registers. */
#define R_OFFS 		r16
#define R_HANDLER	r17
#define R_RET		r18
#define R_TMP		r19
#define R_KSTACK_BSP	r22	/* keep in sync with before_thread_runs_arch() */
#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
 
/** Heavyweight interrupt handler
 *
 * This macro roughly follows steps from 1 to 19 described in
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 *
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
 * This goal is achieved by using procedure calls after RSE becomes operational.
 *
 * Some steps are skipped (enabling and disabling interrupts).
 * Some steps are not fully supported yet (e.g. dealing with floating-point
 * context).
 *
 * @param offs Offset from the beginning of IVT.
 * @param handler Interrupt handler address.
 */
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
    .org ivt + \offs
	mov R_OFFS = \offs
	movl R_HANDLER = \handler ;;
	br heavyweight_handler
.endm
 
.global heavyweight_handler
heavyweight_handler:
    /* 1. copy interrupt registers into bank 0 */
    
	/*
	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
	 */
	mov r24 = cr.iip
	mov r25 = cr.ipsr
	mov r26 = cr.iipa
	mov r27 = cr.isr
	mov r28 = cr.ifa
	
    /* 2. preserve predicate register into bank 0 */
	mov r29 = pr ;;
	
    /* 3. switch to kernel memory stack */
    	mov r30 = cr.ipsr
	shr.u r31 = r12, VRN_SHIFT ;;
 
	shr.u r30 = r30, PSR_CPL_SHIFT ;;
	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
 
	/*
	 * Set p3 to true if the interrupted context executed in kernel mode.
	 * Set p4 to false if the interrupted context didn't execute in kernel mode.
	 */
	cmp.eq p3, p4 = r30, r0 ;;
	cmp.eq p1, p2 = r30, r0 ;;	/* remember IPSR setting in p1 and p2 */
 
	/*
	 * Set p3 to true if the stack register references kernel address space.
	 * Set p4 to false if the stack register doesn't reference kernel address space.
	 */
(p3)	cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
	
	/*
	 * Now, p4 is true iff the stack needs to be switched to kernel stack.
	 */
	mov r30 = r12
(p4)	mov r12 = R_KSTACK ;;
	
	add r31 = -STACK_FRAME_BIAS, r12 ;;
	add r12 = -STACK_FRAME_SIZE, r12
 
    /* 4. save registers in bank 0 into memory stack */
 
	/*
	 * If this is break_instruction handler,
	 * copy input parameters to stack.
	 */
    	mov R_TMP = 0x2c00 ;;
	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
	
	/*
	 * From now on, if this is break_instruction handler, p6 is true and p5 is false.
	 * Otherwise p6 is false and p5 is true.
	 * Note that p5 is a preserved predicate register and we make use of it.
	 */
	
(p6)	st8 [r31] = r35, -8 ;;		/* save in3 */
(p6) 	st8 [r31] = r34, -8 ;;		/* save in2 */
(p6)	st8 [r31] = r33, -8 ;;		/* save in1 */
(p6)	st8 [r31] = r32, -8 ;;		/* save in0 */
(p5)	add r31 = -32, r31 ;;
    
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
	
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
 
	st8 [r31] = r24, -8 ;;		/* save cr.iip */
	st8 [r31] = r25, -8 ;;		/* save cr.ipsr */
	st8 [r31] = r26, -8 ;;		/* save cr.iipa */
	st8 [r31] = r27, -8 ;;		/* save cr.isr */
	st8 [r31] = r28, -8 ;;		/* save cr.ifa */
 
    /* 5. RSE switch from interrupted context */
	mov r24 = ar.rsc
	mov r25 = ar.pfs
	cover
	mov r26 = cr.ifs
	
	st8 [r31] = r24, -8 ;;		/* save ar.rsc */
	st8 [r31] = r25, -8 ;;		/* save ar.pfs */
	st8 [r31] = r26, -8		/* save ar.ifs */
	
	and r24 = ~(RSC_PL_MASK), r24 ;;
	and r30 = ~(RSC_MODE_MASK), r24 ;;
	mov ar.rsc = r30 ;;		/* update RSE state */
	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/*
	 * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
	 */
(p1)	shr.u r30 = r28, VRN_SHIFT ;;
(p1)	cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
	
	/*
	 * If BSPSTORE needs to be switched, p1 is false and p2 is true.
	 */
(p1)	mov r30 = r28
(p2)	mov r30 = R_KSTACK_BSP ;;
(p2)	mov ar.bspstore = r30 ;;
	
	mov r29 = ar.bsp
	
	st8 [r31] = r27, -8 ;;		/* save ar.rnat */
	st8 [r31] = r30, -8 ;;		/* save new value written to ar.bspstore */
	st8 [r31] = r28, -8 ;;		/* save ar.bspstore */
	st8 [r31] = r29, -8 		/* save ar.bsp */
	
	mov ar.rsc = r24		/* restore RSE's setting + kernel privileges */
	
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
	mov R_RET = b0 			/* save b0 belonging to interrupted context */
	br.call.sptk.many b0 = heavyweight_handler_inner
0:	mov b0 = R_RET			/* restore b0 belonging to the interrupted context */
 
    /* 16. RSE switch to interrupted context */
	cover				/* allocate zerro size frame (step 1 (from Intel Docs)) */
 
	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
 
	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */
	shl r27 = r27, 16
 
	mov r24 = ar.rsc ;;
	and r30 = ~3, r24 ;;
	or  r24 = r30 , r27 ;;     
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
 
	loadrs 				/* (step 3) */
 
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
	mov ar.bspstore = r29 ;;	/* (step 4) */
	mov ar.rnat = r27		/* (step 5) */
 
	mov ar.pfs = r25		/* (step 6) */
	mov cr.ifs = r26	
 
	mov ar.rsc = r24		/* (step 7) */
 
    /* 17. restore interruption state from memory stack */
	ld8 r28 = [r31], +8 ;;		/* load cr.ifa */		
	ld8 r27 = [r31], +8 ;;		/* load cr.isr */
	ld8 r26 = [r31], +8 ;;		/* load cr.iipa */
	ld8 r25 = [r31], +8 ;;		/* load cr.ipsr */
	ld8 r24 = [r31], +8 ;;		/* load cr.iip */
 
	mov cr.iip = r24
	mov cr.ipsr = r25
	mov cr.iipa = r26
	mov cr.isr = r27
	mov cr.ifa = r28
 
    /* 18. restore predicate registers from memory stack */
	ld8 r29 = [r31], +8 ;;		/* load predicate registers */
	mov pr = r29
	
    /* 19. return from interruption */
    	ld8 r12 = [r31]			/* load stack pointer */ 
	rfi ;;
 
.global heavyweight_handler_inner
heavyweight_handler_inner:
	/*
	 * From this point, the rest of the interrupted context
	 * will be preserved in stacked registers and backing store.
	 */
	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
	
	/* bank 0 is going to be shadowed, copy essential data from there */
	mov loc1 = R_RET	/* b0 belonging to interrupted context */
	mov loc2 = R_HANDLER
	mov out0 = R_OFFS
	
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
    /* 6. switch to bank 1 and reenable PSR.ic */
	ssm PSR_IC_MASK
	bsw.1 ;;
	srlz.d
	
    /* 7. preserve branch and application registers */
    	mov loc3 = ar.unat
	mov loc4 = ar.lc
	mov loc5 = ar.ec
	mov loc6 = ar.ccv
	mov loc7 = ar.csd
	mov loc8 = ar.ssd
	
	mov loc9 = b0
	mov loc10 = b1
	mov loc11 = b2
	mov loc12 = b3
	mov loc13 = b4
	mov loc14 = b5
	mov loc15 = b6
	mov loc16 = b7
	
    /* 8. preserve general and floating-point registers */
	/* TODO: save floating-point context */
	mov loc17 = r1
	mov loc18 = r2
	mov loc19 = r3
	mov loc20 = r4
	mov loc21 = r5
	mov loc22 = r6
	mov loc23 = r7
(p5)	mov loc24 = r8		/* only if not in break_instruction handler */
	mov loc25 = r9
	mov loc26 = r10
	mov loc27 = r11
	/* skip r12 (stack pointer) */
	mov loc28 = r13
	mov loc29 = r14
	mov loc30 = r15
	mov loc31 = r16
	mov loc32 = r17
	mov loc33 = r18
	mov loc34 = r19
	mov loc35 = r20
	mov loc36 = r21
	mov loc37 = r22
	mov loc38 = r23
	mov loc39 = r24
	mov loc40 = r25
	mov loc41 = r26
	mov loc42 = r27
	mov loc43 = r28
	mov loc44 = r29
	mov loc45 = r30
	mov loc46 = r31
    
    /* 9. skipped (will not enable interrupts) */
	/*
    	 * ssm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 10. call handler */
    	movl r1 = _hardcoded_load_address
    
    	mov b1 = loc2
	br.call.sptk.many b0 = b1
 
    /* 11. return from handler */
0:
	
    /* 12. skipped (will not disable interrupts) */
	/*
    	 * rsm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 13. restore general and floating-point registers */
	/* TODO: restore floating-point context */
	mov r1 = loc17
	mov r2 = loc18
	mov r3 = loc19
	mov r4 = loc20
	mov r5 = loc21
	mov r6 = loc22
	mov r7 = loc23
(p5)	mov r8 = loc24		/* only if not in break_instruction handler */
	mov r9 = loc25
	mov r10 = loc26
	mov r11 = loc27
	/* skip r12 (stack pointer) */
	mov r13 = loc28
	mov r14 = loc29
	mov r15 = loc30
	mov r16 = loc31
	mov r17 = loc32
	mov r18 = loc33
	mov r19 = loc34
	mov r20 = loc35
	mov r21 = loc36
	mov r22 = loc37
	mov r23 = loc38
	mov r24 = loc39
	mov r25 = loc40
	mov r26 = loc41 
	mov r27 = loc42
	mov r28 = loc43
	mov r29 = loc44
	mov r30 = loc45
	mov r31 = loc46
	
    /* 14. restore branch and application registers */
    	mov ar.unat = loc3
	mov ar.lc = loc4
	mov ar.ec = loc5
	mov ar.ccv = loc6
	mov ar.csd = loc7
	mov ar.ssd = loc8
	
	mov b0 = loc9
	mov b1 = loc10
	mov b2 = loc11
	mov b3 = loc12
	mov b4 = loc13
	mov b5 = loc14
	mov b6 = loc15
	mov b7 = loc16
	
    /* 15. disable PSR.ic and switch to bank 0 */
	rsm PSR_IC_MASK
	bsw.0 ;;
	srlz.d
 
	mov R_RET = loc1
	mov ar.pfs = loc0
	br.ret.sptk.many b0
 
.global ivt
.align 32768
ivt:
	HEAVYWEIGHT_HANDLER 0x0000
	HEAVYWEIGHT_HANDLER 0x0400
	HEAVYWEIGHT_HANDLER 0x0800
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1800
	HEAVYWEIGHT_HANDLER 0x1c00
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
	HEAVYWEIGHT_HANDLER 0x3400
	HEAVYWEIGHT_HANDLER 0x3800
	HEAVYWEIGHT_HANDLER 0x3c00
	HEAVYWEIGHT_HANDLER 0x4000
	HEAVYWEIGHT_HANDLER 0x4400
	HEAVYWEIGHT_HANDLER 0x4800
	HEAVYWEIGHT_HANDLER 0x4c00
 
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
	HEAVYWEIGHT_HANDLER 0x5100
	HEAVYWEIGHT_HANDLER 0x5200
	HEAVYWEIGHT_HANDLER 0x5300
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
	HEAVYWEIGHT_HANDLER 0x5500
	HEAVYWEIGHT_HANDLER 0x5600
	HEAVYWEIGHT_HANDLER 0x5700
	HEAVYWEIGHT_HANDLER 0x5800
	HEAVYWEIGHT_HANDLER 0x5900
	HEAVYWEIGHT_HANDLER 0x5a00
	HEAVYWEIGHT_HANDLER 0x5b00
	HEAVYWEIGHT_HANDLER 0x5c00
	HEAVYWEIGHT_HANDLER 0x5d00
	HEAVYWEIGHT_HANDLER 0x5e00
	HEAVYWEIGHT_HANDLER 0x5f00
	
	HEAVYWEIGHT_HANDLER 0x6000
	HEAVYWEIGHT_HANDLER 0x6100
	HEAVYWEIGHT_HANDLER 0x6200
	HEAVYWEIGHT_HANDLER 0x6300
	HEAVYWEIGHT_HANDLER 0x6400
	HEAVYWEIGHT_HANDLER 0x6500
	HEAVYWEIGHT_HANDLER 0x6600
	HEAVYWEIGHT_HANDLER 0x6700
	HEAVYWEIGHT_HANDLER 0x6800
	HEAVYWEIGHT_HANDLER 0x6900
	HEAVYWEIGHT_HANDLER 0x6a00
	HEAVYWEIGHT_HANDLER 0x6b00
	HEAVYWEIGHT_HANDLER 0x6c00
	HEAVYWEIGHT_HANDLER 0x6d00
	HEAVYWEIGHT_HANDLER 0x6e00
	HEAVYWEIGHT_HANDLER 0x6f00
 
	HEAVYWEIGHT_HANDLER 0x7000
	HEAVYWEIGHT_HANDLER 0x7100
	HEAVYWEIGHT_HANDLER 0x7200
	HEAVYWEIGHT_HANDLER 0x7300
	HEAVYWEIGHT_HANDLER 0x7400
	HEAVYWEIGHT_HANDLER 0x7500
	HEAVYWEIGHT_HANDLER 0x7600
	HEAVYWEIGHT_HANDLER 0x7700
	HEAVYWEIGHT_HANDLER 0x7800
	HEAVYWEIGHT_HANDLER 0x7900
	HEAVYWEIGHT_HANDLER 0x7a00
	HEAVYWEIGHT_HANDLER 0x7b00
	HEAVYWEIGHT_HANDLER 0x7c00
	HEAVYWEIGHT_HANDLER 0x7d00
	HEAVYWEIGHT_HANDLER 0x7e00
	HEAVYWEIGHT_HANDLER 0x7f00
 

Rev 919	Rev 921
1	#	1	#
2	# Copyright (C) 2005 Jakub Vana	2	# Copyright (C) 2005 Jakub Vana
3	# Copyright (C) 2005 Jakub Jermar	3	# Copyright (C) 2005 Jakub Jermar
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <arch/stack.h>	30	#include <arch/stack.h>
31	#include <arch/register.h>	31	#include <arch/register.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <align.h>	33	#include <align.h>
34		34
35	#define STACK_ITEMS 14	35	#define STACK_ITEMS 18
36	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)	36	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
37		37
38	#if (STACK_ITEMS % 2 == 0)	38	#if (STACK_ITEMS % 2 == 0)
39	# define STACK_FRAME_BIAS 8	39	# define STACK_FRAME_BIAS 8
40	#else	40	#else
41	# define STACK_FRAME_BIAS 16	41	# define STACK_FRAME_BIAS 16
42	#endif	42	#endif
43		43
44	/** Partitioning of bank 0 registers. */	44	/** Partitioning of bank 0 registers. */
45	#define R_OFFS r16	45	#define R_OFFS r16
46	#define R_HANDLER r17	46	#define R_HANDLER r17
47	#define R_RET r18	47	#define R_RET r18
-		48	#define R_TMP r19
48	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */	49	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
49	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */	50	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
50		51
51	/** Heavyweight interrupt handler	52	/** Heavyweight interrupt handler
52	*	53	*
53	* This macro roughly follows steps from 1 to 19 described in	54	* This macro roughly follows steps from 1 to 19 described in
54	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.	55	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
55	*	56	*
56	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).	57	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
57	* This goal is achieved by using procedure calls after RSE becomes operational.	58	* This goal is achieved by using procedure calls after RSE becomes operational.
58	*	59	*
59	* Some steps are skipped (enabling and disabling interrupts).	60	* Some steps are skipped (enabling and disabling interrupts).
60	* Some steps are not fully supported yet (e.g. dealing with floating-point	61	* Some steps are not fully supported yet (e.g. dealing with floating-point
61	* context).	62	* context).
62	*	63	*
63	* @param offs Offset from the beginning of IVT.	64	* @param offs Offset from the beginning of IVT.
64	* @param handler Interrupt handler address.	65	* @param handler Interrupt handler address.
65	*/	66	*/
66	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler	67	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
67	.org ivt + \offs	68	.org ivt + \offs
68	mov R_OFFS = \offs	69	mov R_OFFS = \offs
69	movl R_HANDLER = \handler ;;	70	movl R_HANDLER = \handler ;;
70	br heavyweight_handler	71	br heavyweight_handler
71	.endm	72	.endm
72		73
73	.global heavyweight_handler	74	.global heavyweight_handler
74	heavyweight_handler:	75	heavyweight_handler:
75	/* 1. copy interrupt registers into bank 0 */	76	/* 1. copy interrupt registers into bank 0 */
76		77
77	/*	78	/*
78	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.	79	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
79	*/	80	*/
80	mov r24 = cr.iip	81	mov r24 = cr.iip
81	mov r25 = cr.ipsr	82	mov r25 = cr.ipsr
82	mov r26 = cr.iipa	83	mov r26 = cr.iipa
83	mov r27 = cr.isr	84	mov r27 = cr.isr
84	mov r28 = cr.ifa	85	mov r28 = cr.ifa
85		86
86	/* 2. preserve predicate register into bank 0 */	87	/* 2. preserve predicate register into bank 0 */
87	mov r29 = pr ;;	88	mov r29 = pr ;;
88		89
89	/* 3. switch to kernel memory stack */	90	/* 3. switch to kernel memory stack */
90	mov r30 = cr.ipsr	91	mov r30 = cr.ipsr
91	shr.u r31 = r12, VRN_SHIFT ;;	92	shr.u r31 = r12, VRN_SHIFT ;;
92		93
93	shr.u r30 = r30, PSR_CPL_SHIFT ;;	94	shr.u r30 = r30, PSR_CPL_SHIFT ;;
94	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;	95	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
95		96
96	/*	97	/*
97	* Set p3 to true if the interrupted context executed in kernel mode.	98	* Set p3 to true if the interrupted context executed in kernel mode.
98	* Set p4 to false if the interrupted context didn't execute in kernel mode.	99	* Set p4 to false if the interrupted context didn't execute in kernel mode.
99	*/	100	*/
100	cmp.eq p3, p4 = r30, r0 ;;	101	cmp.eq p3, p4 = r30, r0 ;;
101	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */	102	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
102		103
103	/*	104	/*
104	* Set p3 to true if the stack register references kernel address space.	105	* Set p3 to true if the stack register references kernel address space.
105	* Set p4 to false if the stack register doesn't reference kernel address space.	106	* Set p4 to false if the stack register doesn't reference kernel address space.
106	*/	107	*/
107	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;	108	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
108		109
109	/*	110	/*
110	* Now, p4 is true iff the stack needs to be switched to kernel stack.	111	* Now, p4 is true iff the stack needs to be switched to kernel stack.
111	*/	112	*/
112	mov r30 = r12	113	mov r30 = r12
113	(p4) mov r12 = R_KSTACK ;;	114	(p4) mov r12 = R_KSTACK ;;
114		115
115	add r31 = -STACK_FRAME_BIAS, r12 ;;	116	add r31 = -STACK_FRAME_BIAS, r12 ;;
116	add r12 = -STACK_FRAME_SIZE, r12	117	add r12 = -STACK_FRAME_SIZE, r12
117		118
118	/* 4. save registers in bank 0 into memory stack */	119	/* 4. save registers in bank 0 into memory stack */
-		120
-		121	/*
-		122	* If this is break_instruction handler,
-		123	* copy input parameters to stack.
-		124	*/
-		125	mov R_TMP = 0x2c00 ;;
-		126	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
-		127
-		128	/*
-		129	* From now on, if this is break_instruction handler, p6 is true and p5 is false.
-		130	* Otherwise p6 is false and p5 is true.
-		131	* Note that p5 is a preserved predicate register and we make use of it.
-		132	*/
-		133
-		134	(p6) st8 [r31] = r35, -8 ;; /* save in3 */
-		135	(p6) st8 [r31] = r34, -8 ;; /* save in2 */
-		136	(p6) st8 [r31] = r33, -8 ;; /* save in1 */
-		137	(p6) st8 [r31] = r32, -8 ;; /* save in0 */
-		138	(p5) add r31 = -32, r31 ;;
-		139
119	st8 [r31] = r30, -8 ;; /* save old stack pointer */	140	st8 [r31] = r30, -8 ;; /* save old stack pointer */
120		141
121	st8 [r31] = r29, -8 ;; /* save predicate registers */	142	st8 [r31] = r29, -8 ;; /* save predicate registers */
122		143
123	st8 [r31] = r24, -8 ;; /* save cr.iip */	144	st8 [r31] = r24, -8 ;; /* save cr.iip */
124	st8 [r31] = r25, -8 ;; /* save cr.ipsr */	145	st8 [r31] = r25, -8 ;; /* save cr.ipsr */
125	st8 [r31] = r26, -8 ;; /* save cr.iipa */	146	st8 [r31] = r26, -8 ;; /* save cr.iipa */
126	st8 [r31] = r27, -8 ;; /* save cr.isr */	147	st8 [r31] = r27, -8 ;; /* save cr.isr */
127	st8 [r31] = r28, -8 ;; /* save cr.ifa */	148	st8 [r31] = r28, -8 ;; /* save cr.ifa */
128		149
129	/* 5. RSE switch from interrupted context */	150	/* 5. RSE switch from interrupted context */
130	mov r24 = ar.rsc	151	mov r24 = ar.rsc
131	mov r25 = ar.pfs	152	mov r25 = ar.pfs
132	cover	153	cover
133	mov r26 = cr.ifs	154	mov r26 = cr.ifs
134		155
135	st8 [r31] = r24, -8 ;; /* save ar.rsc */	156	st8 [r31] = r24, -8 ;; /* save ar.rsc */
136	st8 [r31] = r25, -8 ;; /* save ar.pfs */	157	st8 [r31] = r25, -8 ;; /* save ar.pfs */
137	st8 [r31] = r26, -8 /* save ar.ifs */	158	st8 [r31] = r26, -8 /* save ar.ifs */
138		159
139	and r24 = ~(RSC_PL_MASK), r24 ;;	160	and r24 = ~(RSC_PL_MASK), r24 ;;
140	and r30 = ~(RSC_MODE_MASK), r24 ;;	161	and r30 = ~(RSC_MODE_MASK), r24 ;;
141	mov ar.rsc = r30 ;; /* update RSE state */	162	mov ar.rsc = r30 ;; /* update RSE state */
142		163
143	mov r27 = ar.rnat	164	mov r27 = ar.rnat
144	mov r28 = ar.bspstore ;;	165	mov r28 = ar.bspstore ;;
145		166
146	/*	167	/*
147	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.	168	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
148	*/	169	*/
149	(p1) shr.u r30 = r28, VRN_SHIFT ;;	170	(p1) shr.u r30 = r28, VRN_SHIFT ;;
150	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;	171	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
151		172
152	/*	173	/*
153	* If BSPSTORE needs to be switched, p1 is false and p2 is true.	174	* If BSPSTORE needs to be switched, p1 is false and p2 is true.
154	*/	175	*/
155	(p1) mov r30 = r28	176	(p1) mov r30 = r28
156	(p2) mov r30 = R_KSTACK_BSP ;;	177	(p2) mov r30 = R_KSTACK_BSP ;;
157	(p2) mov ar.bspstore = r30 ;;	178	(p2) mov ar.bspstore = r30 ;;
158		179
159	mov r29 = ar.bsp	180	mov r29 = ar.bsp
160		181
161	st8 [r31] = r27, -8 ;; /* save ar.rnat */	182	st8 [r31] = r27, -8 ;; /* save ar.rnat */
162	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */	183	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
163	st8 [r31] = r28, -8 ;; /* save ar.bspstore */	184	st8 [r31] = r28, -8 ;; /* save ar.bspstore */
164	st8 [r31] = r29, -8 /* save ar.bsp */	185	st8 [r31] = r29, -8 /* save ar.bsp */
165		186
166	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */	187	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
167		188
168	/* steps 6 - 15 are done by heavyweight_handler_inner() */	189	/* steps 6 - 15 are done by heavyweight_handler_inner() */
169	mov R_RET = b0 /* save b0 belonging to interrupted context */	190	mov R_RET = b0 /* save b0 belonging to interrupted context */
170	br.call.sptk.many b0 = heavyweight_handler_inner	191	br.call.sptk.many b0 = heavyweight_handler_inner
171	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */	192	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
172		193
173	/* 16. RSE switch to interrupted context */	194	/* 16. RSE switch to interrupted context */
174	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */	195	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
175		196
176	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;	197	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
177		198
178	ld8 r30 = [r31], +8 ;; /* load ar.bsp */	199	ld8 r30 = [r31], +8 ;; /* load ar.bsp */
179	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */	200	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
180	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */	201	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
181	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */	202	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
182	shl r27 = r27, 16	203	shl r27 = r27, 16
183		204
184	mov r24 = ar.rsc ;;	205	mov r24 = ar.rsc ;;
185	and r30 = ~3, r24 ;;	206	and r30 = ~3, r24 ;;
186	or r24 = r30 , r27 ;;	207	or r24 = r30 , r27 ;;
187	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */	208	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
188		209
189	loadrs /* (step 3) */	210	loadrs /* (step 3) */
190		211
191	ld8 r27 = [r31], +8 ;; /* load ar.rnat */	212	ld8 r27 = [r31], +8 ;; /* load ar.rnat */
192	ld8 r26 = [r31], +8 ;; /* load cr.ifs */	213	ld8 r26 = [r31], +8 ;; /* load cr.ifs */
193	ld8 r25 = [r31], +8 ;; /* load ar.pfs */	214	ld8 r25 = [r31], +8 ;; /* load ar.pfs */
194	ld8 r24 = [r31], +8 ;; /* load ar.rsc */	215	ld8 r24 = [r31], +8 ;; /* load ar.rsc */
195		216
196	mov ar.bspstore = r29 ;; /* (step 4) */	217	mov ar.bspstore = r29 ;; /* (step 4) */
197	mov ar.rnat = r27 /* (step 5) */	218	mov ar.rnat = r27 /* (step 5) */
198		219
199	mov ar.pfs = r25 /* (step 6) */	220	mov ar.pfs = r25 /* (step 6) */
200	mov cr.ifs = r26	221	mov cr.ifs = r26
201		222
202	mov ar.rsc = r24 /* (step 7) */	223	mov ar.rsc = r24 /* (step 7) */
203		224
204	/* 17. restore interruption state from memory stack */	225	/* 17. restore interruption state from memory stack */
205	ld8 r28 = [r31], +8 ;; /* load cr.ifa */	226	ld8 r28 = [r31], +8 ;; /* load cr.ifa */
206	ld8 r27 = [r31], +8 ;; /* load cr.isr */	227	ld8 r27 = [r31], +8 ;; /* load cr.isr */
207	ld8 r26 = [r31], +8 ;; /* load cr.iipa */	228	ld8 r26 = [r31], +8 ;; /* load cr.iipa */
208	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */	229	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
209	ld8 r24 = [r31], +8 ;; /* load cr.iip */	230	ld8 r24 = [r31], +8 ;; /* load cr.iip */
210		231
211	mov cr.iip = r24	232	mov cr.iip = r24
212	mov cr.ipsr = r25	233	mov cr.ipsr = r25
213	mov cr.iipa = r26	234	mov cr.iipa = r26
214	mov cr.isr = r27	235	mov cr.isr = r27
215	mov cr.ifa = r28	236	mov cr.ifa = r28
216		237
217	/* 18. restore predicate registers from memory stack */	238	/* 18. restore predicate registers from memory stack */
218	ld8 r29 = [r31], +8 ;; /* load predicate registers */	239	ld8 r29 = [r31], +8 ;; /* load predicate registers */
219	mov pr = r29	240	mov pr = r29
220		241
221	/* 19. return from interruption */	242	/* 19. return from interruption */
222	ld8 r12 = [r31] /* load stack pointer */	243	ld8 r12 = [r31] /* load stack pointer */
223	rfi ;;	244	rfi ;;
224		245
225	.global heavyweight_handler_inner	246	.global heavyweight_handler_inner
226	heavyweight_handler_inner:	247	heavyweight_handler_inner:
227	/*	248	/*
228	* From this point, the rest of the interrupted context	249	* From this point, the rest of the interrupted context
229	* will be preserved in stacked registers and backing store.	250	* will be preserved in stacked registers and backing store.
230	*/	251	*/
231	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;	252	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
232		253
233	/* bank 0 is going to be shadowed, copy essential data from there */	254	/* bank 0 is going to be shadowed, copy essential data from there */
234	mov loc1 = R_RET /* b0 belonging to interrupted context */	255	mov loc1 = R_RET /* b0 belonging to interrupted context */
235	mov loc2 = R_HANDLER	256	mov loc2 = R_HANDLER
236	mov out0 = R_OFFS	257	mov out0 = R_OFFS
237		258
238	add out1 = STACK_SCRATCH_AREA_SIZE, r12	259	add out1 = STACK_SCRATCH_AREA_SIZE, r12
239		260
240	/* 6. switch to bank 1 and reenable PSR.ic */	261	/* 6. switch to bank 1 and reenable PSR.ic */
241	ssm PSR_IC_MASK	262	ssm PSR_IC_MASK
242	bsw.1 ;;	263	bsw.1 ;;
243	srlz.d	264	srlz.d
244		265
245	/* 7. preserve branch and application registers */	266	/* 7. preserve branch and application registers */
246	mov loc3 = ar.unat	267	mov loc3 = ar.unat
247	mov loc4 = ar.lc	268	mov loc4 = ar.lc
248	mov loc5 = ar.ec	269	mov loc5 = ar.ec
249	mov loc6 = ar.ccv	270	mov loc6 = ar.ccv
250	mov loc7 = ar.csd	271	mov loc7 = ar.csd
251	mov loc8 = ar.ssd	272	mov loc8 = ar.ssd
252		273
253	mov loc9 = b0	274	mov loc9 = b0
254	mov loc10 = b1	275	mov loc10 = b1
255	mov loc11 = b2	276	mov loc11 = b2
256	mov loc12 = b3	277	mov loc12 = b3
257	mov loc13 = b4	278	mov loc13 = b4
258	mov loc14 = b5	279	mov loc14 = b5
259	mov loc15 = b6	280	mov loc15 = b6
260	mov loc16 = b7	281	mov loc16 = b7
261		282
262	/* 8. preserve general and floating-point registers */	283	/* 8. preserve general and floating-point registers */
263	/* TODO: save floating-point context */	284	/* TODO: save floating-point context */
264	mov loc17 = r1	285	mov loc17 = r1
265	mov loc18 = r2	286	mov loc18 = r2
266	mov loc19 = r3	287	mov loc19 = r3
267	mov loc20 = r4	288	mov loc20 = r4
268	mov loc21 = r5	289	mov loc21 = r5
269	mov loc22 = r6	290	mov loc22 = r6
270	mov loc23 = r7	291	mov loc23 = r7
271	mov loc24 = r8	292	(p5) mov loc24 = r8 /* only if not in break_instruction handler */
272	mov loc25 = r9	293	mov loc25 = r9
273	mov loc26 = r10	294	mov loc26 = r10
274	mov loc27 = r11	295	mov loc27 = r11
275	/* skip r12 (stack pointer) */	296	/* skip r12 (stack pointer) */
276	mov loc28 = r13	297	mov loc28 = r13
277	mov loc29 = r14	298	mov loc29 = r14
278	mov loc30 = r15	299	mov loc30 = r15
279	mov loc31 = r16	300	mov loc31 = r16
280	mov loc32 = r17	301	mov loc32 = r17
281	mov loc33 = r18	302	mov loc33 = r18
282	mov loc34 = r19	303	mov loc34 = r19
283	mov loc35 = r20	304	mov loc35 = r20
284	mov loc36 = r21	305	mov loc36 = r21
285	mov loc37 = r22	306	mov loc37 = r22
286	mov loc38 = r23	307	mov loc38 = r23
287	mov loc39 = r24	308	mov loc39 = r24
288	mov loc40 = r25	309	mov loc40 = r25
289	mov loc41 = r26	310	mov loc41 = r26
290	mov loc42 = r27	311	mov loc42 = r27
291	mov loc43 = r28	312	mov loc43 = r28
292	mov loc44 = r29	313	mov loc44 = r29
293	mov loc45 = r30	314	mov loc45 = r30
294	mov loc46 = r31	315	mov loc46 = r31
295		316
296	/* 9. skipped (will not enable interrupts) */	317	/* 9. skipped (will not enable interrupts) */
297	/*	318	/*
298	* ssm PSR_I_MASK	319	* ssm PSR_I_MASK
299	* ;;	320	* ;;
300	* srlz.d	321	* srlz.d
301	*/	322	*/
302		323
303	/* 10. call handler */	324	/* 10. call handler */
304	movl r1 = _hardcoded_load_address	325	movl r1 = _hardcoded_load_address
305		326
306	mov b1 = loc2	327	mov b1 = loc2
307	br.call.sptk.many b0 = b1	328	br.call.sptk.many b0 = b1
308		329
309	/* 11. return from handler */	330	/* 11. return from handler */
310	0:	331	0:
311		332
312	/* 12. skipped (will not disable interrupts) */	333	/* 12. skipped (will not disable interrupts) */
313	/*	334	/*
314	* rsm PSR_I_MASK	335	* rsm PSR_I_MASK
315	* ;;	336	* ;;
316	* srlz.d	337	* srlz.d
317	*/	338	*/
318		339
319	/* 13. restore general and floating-point registers */	340	/* 13. restore general and floating-point registers */
320	/* TODO: restore floating-point context */	341	/* TODO: restore floating-point context */
321	mov r1 = loc17	342	mov r1 = loc17
322	mov r2 = loc18	343	mov r2 = loc18
323	mov r3 = loc19	344	mov r3 = loc19
324	mov r4 = loc20	345	mov r4 = loc20
325	mov r5 = loc21	346	mov r5 = loc21
326	mov r6 = loc22	347	mov r6 = loc22
327	mov r7 = loc23	348	mov r7 = loc23
328	mov r8 = loc24	349	(p5) mov r8 = loc24 /* only if not in break_instruction handler */
329	mov r9 = loc25	350	mov r9 = loc25
330	mov r10 = loc26	351	mov r10 = loc26
331	mov r11 = loc27	352	mov r11 = loc27
332	/* skip r12 (stack pointer) */	353	/* skip r12 (stack pointer) */
333	mov r13 = loc28	354	mov r13 = loc28
334	mov r14 = loc29	355	mov r14 = loc29
335	mov r15 = loc30	356	mov r15 = loc30
336	mov r16 = loc31	357	mov r16 = loc31
337	mov r17 = loc32	358	mov r17 = loc32
338	mov r18 = loc33	359	mov r18 = loc33
339	mov r19 = loc34	360	mov r19 = loc34
340	mov r20 = loc35	361	mov r20 = loc35
341	mov r21 = loc36	362	mov r21 = loc36
342	mov r22 = loc37	363	mov r22 = loc37
343	mov r23 = loc38	364	mov r23 = loc38
344	mov r24 = loc39	365	mov r24 = loc39
345	mov r25 = loc40	366	mov r25 = loc40
346	mov r26 = loc41	367	mov r26 = loc41
347	mov r27 = loc42	368	mov r27 = loc42
348	mov r28 = loc43	369	mov r28 = loc43
349	mov r29 = loc44	370	mov r29 = loc44
350	mov r30 = loc45	371	mov r30 = loc45
351	mov r31 = loc46	372	mov r31 = loc46
352		373
353	/* 14. restore branch and application registers */	374	/* 14. restore branch and application registers */
354	mov ar.unat = loc3	375	mov ar.unat = loc3
355	mov ar.lc = loc4	376	mov ar.lc = loc4
356	mov ar.ec = loc5	377	mov ar.ec = loc5
357	mov ar.ccv = loc6	378	mov ar.ccv = loc6
358	mov ar.csd = loc7	379	mov ar.csd = loc7
359	mov ar.ssd = loc8	380	mov ar.ssd = loc8
360		381
361	mov b0 = loc9	382	mov b0 = loc9
362	mov b1 = loc10	383	mov b1 = loc10
363	mov b2 = loc11	384	mov b2 = loc11
364	mov b3 = loc12	385	mov b3 = loc12
365	mov b4 = loc13	386	mov b4 = loc13
366	mov b5 = loc14	387	mov b5 = loc14
367	mov b6 = loc15	388	mov b6 = loc15
368	mov b7 = loc16	389	mov b7 = loc16
369		390
370	/* 15. disable PSR.ic and switch to bank 0 */	391	/* 15. disable PSR.ic and switch to bank 0 */
371	rsm PSR_IC_MASK	392	rsm PSR_IC_MASK
372	bsw.0 ;;	393	bsw.0 ;;
373	srlz.d	394	srlz.d
374		395
375	mov R_RET = loc1	396	mov R_RET = loc1
376	mov ar.pfs = loc0	397	mov ar.pfs = loc0
377	br.ret.sptk.many b0	398	br.ret.sptk.many b0
378		399
379	.global ivt	400	.global ivt
380	.align 32768	401	.align 32768
381	ivt:	402	ivt:
382	HEAVYWEIGHT_HANDLER 0x0000	403	HEAVYWEIGHT_HANDLER 0x0000
383	HEAVYWEIGHT_HANDLER 0x0400	404	HEAVYWEIGHT_HANDLER 0x0400
384	HEAVYWEIGHT_HANDLER 0x0800	405	HEAVYWEIGHT_HANDLER 0x0800
385	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault	406	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
386	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault	407	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
387	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault	408	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
388	HEAVYWEIGHT_HANDLER 0x1800	409	HEAVYWEIGHT_HANDLER 0x1800
389	HEAVYWEIGHT_HANDLER 0x1c00	410	HEAVYWEIGHT_HANDLER 0x1c00
390	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault	411	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
391	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault	412	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
392	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault	413	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
393	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction	414	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
394	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */	415	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
395	HEAVYWEIGHT_HANDLER 0x3400	416	HEAVYWEIGHT_HANDLER 0x3400
396	HEAVYWEIGHT_HANDLER 0x3800	417	HEAVYWEIGHT_HANDLER 0x3800
397	HEAVYWEIGHT_HANDLER 0x3c00	418	HEAVYWEIGHT_HANDLER 0x3c00
398	HEAVYWEIGHT_HANDLER 0x4000	419	HEAVYWEIGHT_HANDLER 0x4000
399	HEAVYWEIGHT_HANDLER 0x4400	420	HEAVYWEIGHT_HANDLER 0x4400
400	HEAVYWEIGHT_HANDLER 0x4800	421	HEAVYWEIGHT_HANDLER 0x4800
401	HEAVYWEIGHT_HANDLER 0x4c00	422	HEAVYWEIGHT_HANDLER 0x4c00
402		423
403	HEAVYWEIGHT_HANDLER 0x5000 page_not_present	424	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
404	HEAVYWEIGHT_HANDLER 0x5100	425	HEAVYWEIGHT_HANDLER 0x5100
405	HEAVYWEIGHT_HANDLER 0x5200	426	HEAVYWEIGHT_HANDLER 0x5200
406	HEAVYWEIGHT_HANDLER 0x5300	427	HEAVYWEIGHT_HANDLER 0x5300
407	HEAVYWEIGHT_HANDLER 0x5400 general_exception	428	HEAVYWEIGHT_HANDLER 0x5400 general_exception
408	HEAVYWEIGHT_HANDLER 0x5500	429	HEAVYWEIGHT_HANDLER 0x5500
409	HEAVYWEIGHT_HANDLER 0x5600	430	HEAVYWEIGHT_HANDLER 0x5600
410	HEAVYWEIGHT_HANDLER 0x5700	431	HEAVYWEIGHT_HANDLER 0x5700
411	HEAVYWEIGHT_HANDLER 0x5800	432	HEAVYWEIGHT_HANDLER 0x5800
412	HEAVYWEIGHT_HANDLER 0x5900	433	HEAVYWEIGHT_HANDLER 0x5900
413	HEAVYWEIGHT_HANDLER 0x5a00	434	HEAVYWEIGHT_HANDLER 0x5a00
414	HEAVYWEIGHT_HANDLER 0x5b00	435	HEAVYWEIGHT_HANDLER 0x5b00
415	HEAVYWEIGHT_HANDLER 0x5c00	436	HEAVYWEIGHT_HANDLER 0x5c00
416	HEAVYWEIGHT_HANDLER 0x5d00	437	HEAVYWEIGHT_HANDLER 0x5d00
417	HEAVYWEIGHT_HANDLER 0x5e00	438	HEAVYWEIGHT_HANDLER 0x5e00
418	HEAVYWEIGHT_HANDLER 0x5f00	439	HEAVYWEIGHT_HANDLER 0x5f00
419		440
420	HEAVYWEIGHT_HANDLER 0x6000	441	HEAVYWEIGHT_HANDLER 0x6000
421	HEAVYWEIGHT_HANDLER 0x6100	442	HEAVYWEIGHT_HANDLER 0x6100
422	HEAVYWEIGHT_HANDLER 0x6200	443	HEAVYWEIGHT_HANDLER 0x6200
423	HEAVYWEIGHT_HANDLER 0x6300	444	HEAVYWEIGHT_HANDLER 0x6300
424	HEAVYWEIGHT_HANDLER 0x6400	445	HEAVYWEIGHT_HANDLER 0x6400
425	HEAVYWEIGHT_HANDLER 0x6500	446	HEAVYWEIGHT_HANDLER 0x6500
426	HEAVYWEIGHT_HANDLER 0x6600	447	HEAVYWEIGHT_HANDLER 0x6600
427	HEAVYWEIGHT_HANDLER 0x6700	448	HEAVYWEIGHT_HANDLER 0x6700
428	HEAVYWEIGHT_HANDLER 0x6800	449	HEAVYWEIGHT_HANDLER 0x6800
429	HEAVYWEIGHT_HANDLER 0x6900	450	HEAVYWEIGHT_HANDLER 0x6900
430	HEAVYWEIGHT_HANDLER 0x6a00	451	HEAVYWEIGHT_HANDLER 0x6a00
431	HEAVYWEIGHT_HANDLER 0x6b00	452	HEAVYWEIGHT_HANDLER 0x6b00
432	HEAVYWEIGHT_HANDLER 0x6c00	453	HEAVYWEIGHT_HANDLER 0x6c00
433	HEAVYWEIGHT_HANDLER 0x6d00	454	HEAVYWEIGHT_HANDLER 0x6d00
434	HEAVYWEIGHT_HANDLER 0x6e00	455	HEAVYWEIGHT_HANDLER 0x6e00
435	HEAVYWEIGHT_HANDLER 0x6f00	456	HEAVYWEIGHT_HANDLER 0x6f00
436		457
437	HEAVYWEIGHT_HANDLER 0x7000	458	HEAVYWEIGHT_HANDLER 0x7000
438	HEAVYWEIGHT_HANDLER 0x7100	459	HEAVYWEIGHT_HANDLER 0x7100
439	HEAVYWEIGHT_HANDLER 0x7200	460	HEAVYWEIGHT_HANDLER 0x7200
440	HEAVYWEIGHT_HANDLER 0x7300	461	HEAVYWEIGHT_HANDLER 0x7300
441	HEAVYWEIGHT_HANDLER 0x7400	462	HEAVYWEIGHT_HANDLER 0x7400
442	HEAVYWEIGHT_HANDLER 0x7500	463	HEAVYWEIGHT_HANDLER 0x7500
443	HEAVYWEIGHT_HANDLER 0x7600	464	HEAVYWEIGHT_HANDLER 0x7600
444	HEAVYWEIGHT_HANDLER 0x7700	465	HEAVYWEIGHT_HANDLER 0x7700
445	HEAVYWEIGHT_HANDLER 0x7800	466	HEAVYWEIGHT_HANDLER 0x7800
446	HEAVYWEIGHT_HANDLER 0x7900	467	HEAVYWEIGHT_HANDLER 0x7900
447	HEAVYWEIGHT_HANDLER 0x7a00	468	HEAVYWEIGHT_HANDLER 0x7a00
448	HEAVYWEIGHT_HANDLER 0x7b00	469	HEAVYWEIGHT_HANDLER 0x7b00
449	HEAVYWEIGHT_HANDLER 0x7c00	470	HEAVYWEIGHT_HANDLER 0x7c00
450	HEAVYWEIGHT_HANDLER 0x7d00	471	HEAVYWEIGHT_HANDLER 0x7d00
451	HEAVYWEIGHT_HANDLER 0x7e00	472	HEAVYWEIGHT_HANDLER 0x7e00
452	HEAVYWEIGHT_HANDLER 0x7f00	473	HEAVYWEIGHT_HANDLER 0x7f00
453		474

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/ivt.S – Rev 919 → 921