WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/ivt.S


#
# Copyright (C) 2005 Jakub Vana
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/stack.h>
#include <arch/register.h>
#include <arch/mm/page.h>
#include <align.h>
 
#define STACK_ITEMS		14
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
#if (STACK_ITEMS % 2 == 0)
#	define STACK_FRAME_BIAS	8
#else
#	define STACK_FRAME_BIAS 16
#endif
 
/** Partitioning of bank 0 registers. */
#define R_OFFS 		r16
#define R_HANDLER	r17
#define R_RET		r18
#define R_KSTACK_BSP	r22	/* keep in sync with before_thread_runs_arch() */
#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
 
/** Heavyweight interrupt handler
 *
 * This macro roughly follows steps from 1 to 19 described in
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 *
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
 * This goal is achieved by using procedure calls after RSE becomes operational.
 *
 * Some steps are skipped (enabling and disabling interrupts).
 * Some steps are not fully supported yet (e.g. dealing with floating-point
 * context).
 *
 * @param offs Offset from the beginning of IVT.
 * @param handler Interrupt handler address.
 */
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
    .org ivt + \offs
	mov R_OFFS = \offs
	movl R_HANDLER = \handler ;;
	br heavyweight_handler
.endm
 
.global heavyweight_handler
heavyweight_handler:
    /* 1. copy interrupt registers into bank 0 */
    
	/*
	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
	 */
	mov r24 = cr.iip
	mov r25 = cr.ipsr
	mov r26 = cr.iipa
	mov r27 = cr.isr
	mov r28 = cr.ifa
	
    /* 2. preserve predicate register into bank 0 */
	mov r29 = pr ;;
	
    /* 3. switch to kernel memory stack */
    	mov r30 = cr.ipsr
	shr.u r31 = r12, VRN_SHIFT ;;
 
	shr.u r30 = r30, PSR_CPL_SHIFT ;;
	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
 
	/*
	 * Set p3 to true if the interrupted context executed in kernel mode.
	 * Set p4 to false if the interrupted context didn't execute in kernel mode.
	 */
	cmp.eq p3, p4 = r30, r0 ;;
	cmp.eq p1, p2 = r30, r0 ;;	/* remember IPSR setting in p1 and p2 */
 
	/*
	 * Set p3 to true if the stack register references kernel address space.
	 * Set p4 to false if the stack register doesn't reference kernel address space.
	 */
	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
	
	/*
	 * Now, p4 is true iff the stack needs to be switched to kernel stack.
	 */
	mov r30 = r12
	(p4) mov r12 = R_KSTACK ;;
	
	add r31 = -STACK_FRAME_BIAS, r12 ;;
	add r12 = -STACK_FRAME_SIZE, r12
 
    /* 4. save registers in bank 0 into memory stack */	
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
	
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
 
	st8 [r31] = r24, -8 ;;		/* save cr.iip */
	st8 [r31] = r25, -8 ;;		/* save cr.ipsr */
	st8 [r31] = r26, -8 ;;		/* save cr.iipa */
	st8 [r31] = r27, -8 ;;		/* save cr.isr */
	st8 [r31] = r28, -8 ;;		/* save cr.ifa */
 
    /* 5. RSE switch from interrupted context */
	mov r24 = ar.rsc
	mov r25 = ar.pfs
	cover
	mov r26 = cr.ifs
	
	st8 [r31] = r24, -8 ;;		/* save ar.rsc */
	st8 [r31] = r25, -8 ;;		/* save ar.pfs */
	st8 [r31] = r26, -8		/* save ar.ifs */
	
	and r24 = ~(RSC_PL_MASK), r24 ;;
	and r30 = ~(RSC_MODE_MASK), r24 ;;
	mov ar.rsc = r30 ;;		/* update RSE state */
	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/*
	 * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
	 */
	(p1) shr.u r30 = r28, VRN_SHIFT ;;
	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
	
	/*
	 * If BSPSTORE needs to be switched, p1 is false and p2 is true.
	 */
	(p1) mov r30 = r28
	(p2) mov r30 = R_KSTACK_BSP ;;
	(p2) mov ar.bspstore = r30 ;;
	
	mov r29 = ar.bsp
	
	st8 [r31] = r27, -8 ;;		/* save ar.rnat */
	st8 [r31] = r30, -8 ;;		/* save new value written to ar.bspstore */
	st8 [r31] = r28, -8 ;;		/* save ar.bspstore */
	st8 [r31] = r29, -8 		/* save ar.bsp */
	
	mov ar.rsc = r24		/* restore RSE's setting + kernel privileges */
	
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
	mov R_RET = b0 			/* save b0 belonging to interrupted context */
	br.call.sptk.many b0 = heavyweight_handler_inner
0:	mov b0 = R_RET			/* restore b0 belonging to the interrupted context */
 
    /* 16. RSE switch to interrupted context */
	cover				/* allocate zerro size frame (step 1 (from Intel Docs)) */
 
	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
 
	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */
	shl r27 = r27, 16
 
	mov r24 = ar.rsc ;;
	and r30 = ~3, r24 ;;
	or  r24 = r30 , r27 ;;     
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
 
	loadrs 				/* (step 3) */
 
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
	mov ar.bspstore = r29 ;;	/* (step 4) */
	mov ar.rnat = r27		/* (step 5) */
 
	mov ar.pfs = r25		/* (step 6) */
	mov cr.ifs = r26	
 
	mov ar.rsc = r24		/* (step 7) */
 
    /* 17. restore interruption state from memory stack */
	ld8 r28 = [r31], +8 ;;		/* load cr.ifa */		
	ld8 r27 = [r31], +8 ;;		/* load cr.isr */
	ld8 r26 = [r31], +8 ;;		/* load cr.iipa */
	ld8 r25 = [r31], +8 ;;		/* load cr.ipsr */
	ld8 r24 = [r31], +8 ;;		/* load cr.iip */
 
	mov cr.iip = r24
	mov cr.ipsr = r25
	mov cr.iipa = r26
	mov cr.isr = r27
	mov cr.ifa = r28
 
    /* 18. restore predicate registers from memory stack */
	ld8 r29 = [r31], +8 ;;		/* load predicate registers */
	mov pr = r29
	
    /* 19. return from interruption */
    	ld8 r12 = [r31]			/* load stack pointer */ 
	rfi ;;
 
.global heavyweight_handler_inner
heavyweight_handler_inner:
	/*
	 * From this point, the rest of the interrupted context
	 * will be preserved in stacked registers and backing store.
	 */
	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
	
	/* bank 0 is going to be shadowed, copy essential data from there */
	mov loc1 = R_RET	/* b0 belonging to interrupted context */
	mov loc2 = R_HANDLER
	mov out0 = R_OFFS
	
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
    /* 6. switch to bank 1 and reenable PSR.ic */
	ssm PSR_IC_MASK
	bsw.1 ;;
	srlz.d
	
    /* 7. preserve branch and application registers */
    	mov loc3 = ar.unat
	mov loc4 = ar.lc
	mov loc5 = ar.ec
	mov loc6 = ar.ccv
	mov loc7 = ar.csd
	mov loc8 = ar.ssd
	
	mov loc9 = b0
	mov loc10 = b1
	mov loc11 = b2
	mov loc12 = b3
	mov loc13 = b4
	mov loc14 = b5
	mov loc15 = b6
	mov loc16 = b7
	
    /* 8. preserve general and floating-point registers */
	/* TODO: save floating-point context */
	mov loc17 = r1
	mov loc18 = r2
	mov loc19 = r3
	mov loc20 = r4
	mov loc21 = r5
	mov loc22 = r6
	mov loc23 = r7
	mov loc24 = r8
	mov loc25 = r9
	mov loc26 = r10
	mov loc27 = r11
	/* skip r12 (stack pointer) */
	mov loc28 = r13
	mov loc29 = r14
	mov loc30 = r15
	mov loc31 = r16
	mov loc32 = r17
	mov loc33 = r18
	mov loc34 = r19
	mov loc35 = r20
	mov loc36 = r21
	mov loc37 = r22
	mov loc38 = r23
	mov loc39 = r24
	mov loc40 = r25
	mov loc41 = r26
	mov loc42 = r27
	mov loc43 = r28
	mov loc44 = r29
	mov loc45 = r30
	mov loc46 = r31
    
    /* 9. skipped (will not enable interrupts) */
	/*
    	 * ssm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 10. call handler */
    	movl r1 = _hardcoded_load_address
    
    	mov b1 = loc2
	br.call.sptk.many b0 = b1
 
    /* 11. return from handler */
0:
	
    /* 12. skipped (will not disable interrupts) */
	/*
    	 * rsm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 13. restore general and floating-point registers */
	/* TODO: restore floating-point context */
	mov r1 = loc17
	mov r2 = loc18
	mov r3 = loc19
	mov r4 = loc20
	mov r5 = loc21
	mov r6 = loc22
	mov r7 = loc23
	mov r8 = loc24
	mov r9 = loc25
	mov r10 = loc26
	mov r11 = loc27
	/* skip r12 (stack pointer) */
	mov r13 = loc28
	mov r14 = loc29
	mov r15 = loc30
	mov r16 = loc31
	mov r17 = loc32
	mov r18 = loc33
	mov r19 = loc34
	mov r20 = loc35
	mov r21 = loc36
	mov r22 = loc37
	mov r23 = loc38
	mov r24 = loc39
	mov r25 = loc40
	mov r26 = loc41 
	mov r27 = loc42
	mov r28 = loc43
	mov r29 = loc44
	mov r30 = loc45
	mov r31 = loc46
	
    /* 14. restore branch and application registers */
    	mov ar.unat = loc3
	mov ar.lc = loc4
	mov ar.ec = loc5
	mov ar.ccv = loc6
	mov ar.csd = loc7
	mov ar.ssd = loc8
	
	mov b0 = loc9
	mov b1 = loc10
	mov b2 = loc11
	mov b3 = loc12
	mov b4 = loc13
	mov b5 = loc14
	mov b6 = loc15
	mov b7 = loc16
	
    /* 15. disable PSR.ic and switch to bank 0 */
	rsm PSR_IC_MASK
	bsw.0 ;;
	srlz.d
 
	mov R_RET = loc1
	mov ar.pfs = loc0
	br.ret.sptk.many b0
 
.global ivt
.align 32768
ivt:
	HEAVYWEIGHT_HANDLER 0x0000
	HEAVYWEIGHT_HANDLER 0x0400
	HEAVYWEIGHT_HANDLER 0x0800
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1800
	HEAVYWEIGHT_HANDLER 0x1c00
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
	HEAVYWEIGHT_HANDLER 0x3400
	HEAVYWEIGHT_HANDLER 0x3800
	HEAVYWEIGHT_HANDLER 0x3c00
	HEAVYWEIGHT_HANDLER 0x4000
	HEAVYWEIGHT_HANDLER 0x4400
	HEAVYWEIGHT_HANDLER 0x4800
	HEAVYWEIGHT_HANDLER 0x4c00
 
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
	HEAVYWEIGHT_HANDLER 0x5100
	HEAVYWEIGHT_HANDLER 0x5200
	HEAVYWEIGHT_HANDLER 0x5300
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
	HEAVYWEIGHT_HANDLER 0x5500
	HEAVYWEIGHT_HANDLER 0x5600
	HEAVYWEIGHT_HANDLER 0x5700
	HEAVYWEIGHT_HANDLER 0x5800
	HEAVYWEIGHT_HANDLER 0x5900
	HEAVYWEIGHT_HANDLER 0x5a00
	HEAVYWEIGHT_HANDLER 0x5b00
	HEAVYWEIGHT_HANDLER 0x5c00
	HEAVYWEIGHT_HANDLER 0x5d00
	HEAVYWEIGHT_HANDLER 0x5e00
	HEAVYWEIGHT_HANDLER 0x5f00
	
	HEAVYWEIGHT_HANDLER 0x6000
	HEAVYWEIGHT_HANDLER 0x6100
	HEAVYWEIGHT_HANDLER 0x6200
	HEAVYWEIGHT_HANDLER 0x6300
	HEAVYWEIGHT_HANDLER 0x6400
	HEAVYWEIGHT_HANDLER 0x6500
	HEAVYWEIGHT_HANDLER 0x6600
	HEAVYWEIGHT_HANDLER 0x6700
	HEAVYWEIGHT_HANDLER 0x6800
	HEAVYWEIGHT_HANDLER 0x6900
	HEAVYWEIGHT_HANDLER 0x6a00
	HEAVYWEIGHT_HANDLER 0x6b00
	HEAVYWEIGHT_HANDLER 0x6c00
	HEAVYWEIGHT_HANDLER 0x6d00
	HEAVYWEIGHT_HANDLER 0x6e00
	HEAVYWEIGHT_HANDLER 0x6f00
 
	HEAVYWEIGHT_HANDLER 0x7000
	HEAVYWEIGHT_HANDLER 0x7100
	HEAVYWEIGHT_HANDLER 0x7200
	HEAVYWEIGHT_HANDLER 0x7300
	HEAVYWEIGHT_HANDLER 0x7400
	HEAVYWEIGHT_HANDLER 0x7500
	HEAVYWEIGHT_HANDLER 0x7600
	HEAVYWEIGHT_HANDLER 0x7700
	HEAVYWEIGHT_HANDLER 0x7800
	HEAVYWEIGHT_HANDLER 0x7900
	HEAVYWEIGHT_HANDLER 0x7a00
	HEAVYWEIGHT_HANDLER 0x7b00
	HEAVYWEIGHT_HANDLER 0x7c00
	HEAVYWEIGHT_HANDLER 0x7d00
	HEAVYWEIGHT_HANDLER 0x7e00
	HEAVYWEIGHT_HANDLER 0x7f00
 

Rev 916	Rev 919
1	#	1	#
2	# Copyright (C) 2005 Jakub Vana	2	# Copyright (C) 2005 Jakub Vana
3	# Copyright (C) 2005 Jakub Jermar	3	# Copyright (C) 2005 Jakub Jermar
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <arch/stack.h>	30	#include <arch/stack.h>
31	#include <arch/register.h>	31	#include <arch/register.h>
32	#include <arch/mm/page.h>	32	#include <arch/mm/page.h>
33	#include <align.h>	33	#include <align.h>
34		34
35	#define STACK_ITEMS 14	35	#define STACK_ITEMS 14
36	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)	36	#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
37		37
38	#if (STACK_ITEMS % 2 == 0)	38	#if (STACK_ITEMS % 2 == 0)
39	# define STACK_FRAME_BIAS 8	39	# define STACK_FRAME_BIAS 8
40	#else	40	#else
41	# define STACK_FRAME_BIAS 16	41	# define STACK_FRAME_BIAS 16
42	#endif	42	#endif
43		43
44	/** Partitioning of bank 0 registers. */	44	/** Partitioning of bank 0 registers. */
45	#define R_OFFS r16	45	#define R_OFFS r16
46	#define R_HANDLER r17	46	#define R_HANDLER r17
47	#define R_RET r18	47	#define R_RET r18
48	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */	48	#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
49	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */	49	#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
50		50
51	/** Heavyweight interrupt handler	51	/** Heavyweight interrupt handler
52	*	52	*
53	* This macro roughly follows steps from 1 to 19 described in	53	* This macro roughly follows steps from 1 to 19 described in
54	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.	54	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
55	*	55	*
56	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).	56	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
57	* This goal is achieved by using procedure calls after RSE becomes operational.	57	* This goal is achieved by using procedure calls after RSE becomes operational.
58	*	58	*
59	* Some steps are skipped (enabling and disabling interrupts).	59	* Some steps are skipped (enabling and disabling interrupts).
60	* Some steps are not fully supported yet (e.g. dealing with floating-point	60	* Some steps are not fully supported yet (e.g. dealing with floating-point
61	* context).	61	* context).
62	*	62	*
63	* @param offs Offset from the beginning of IVT.	63	* @param offs Offset from the beginning of IVT.
64	* @param handler Interrupt handler address.	64	* @param handler Interrupt handler address.
65	*/	65	*/
66	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler	66	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
67	.org ivt + \offs	67	.org ivt + \offs
68	mov R_OFFS = \offs	68	mov R_OFFS = \offs
69	movl R_HANDLER = \handler ;;	69	movl R_HANDLER = \handler ;;
70	br heavyweight_handler	70	br heavyweight_handler
71	.endm	71	.endm
72		72
73	.global heavyweight_handler	73	.global heavyweight_handler
74	heavyweight_handler:	74	heavyweight_handler:
75	/* 1. copy interrupt registers into bank 0 */	75	/* 1. copy interrupt registers into bank 0 */
76		76
77	/*	77	/*
78	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.	78	* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
79	*/	79	*/
80	mov r24 = cr.iip	80	mov r24 = cr.iip
81	mov r25 = cr.ipsr	81	mov r25 = cr.ipsr
82	mov r26 = cr.iipa	82	mov r26 = cr.iipa
83	mov r27 = cr.isr	83	mov r27 = cr.isr
84	mov r28 = cr.ifa	84	mov r28 = cr.ifa
85		85
86	/* 2. preserve predicate register into bank 0 */	86	/* 2. preserve predicate register into bank 0 */
87	mov r29 = pr ;;	87	mov r29 = pr ;;
88		88
89	/* 3. switch to kernel memory stack */	89	/* 3. switch to kernel memory stack */
90	mov r30 = cr.ipsr	90	mov r30 = cr.ipsr
91	shr.u r31 = r12, VRN_SHIFT ;;	91	shr.u r31 = r12, VRN_SHIFT ;;
92		92
93	shr.u r30 = r30, PSR_CPL_SHIFT ;;	93	shr.u r30 = r30, PSR_CPL_SHIFT ;;
94	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;	94	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
95		95
96	/*	96	/*
97	* Set p3 to true if the interrupted context executed in kernel mode.	97	* Set p3 to true if the interrupted context executed in kernel mode.
98	* Set p4 to false if the interrupted context didn't execute in kernel mode.	98	* Set p4 to false if the interrupted context didn't execute in kernel mode.
99	*/	99	*/
100	cmp.eq p3, p4 = r30, r0 ;;	100	cmp.eq p3, p4 = r30, r0 ;;
101	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */	101	cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
102		102
103	/*	103	/*
104	* Set p3 to true if the stack register references kernel address space.	104	* Set p3 to true if the stack register references kernel address space.
105	* Set p4 to false if the stack register doesn't reference kernel address space.	105	* Set p4 to false if the stack register doesn't reference kernel address space.
106	*/	106	*/
107	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;	107	(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
108		108
109	/*	109	/*
110	* Now, p4 is true iff the stack needs to be switched to kernel stack.	110	* Now, p4 is true iff the stack needs to be switched to kernel stack.
111	*/	111	*/
112	mov r30 = r12	112	mov r30 = r12
113	(p4) mov r12 = R_KSTACK ;;	113	(p4) mov r12 = R_KSTACK ;;
114		114
115	add r31 = -STACK_FRAME_BIAS, r12 ;;	115	add r31 = -STACK_FRAME_BIAS, r12 ;;
116	add r12 = -STACK_FRAME_SIZE, r12	116	add r12 = -STACK_FRAME_SIZE, r12
117		117
118	/* 4. save registers in bank 0 into memory stack */	118	/* 4. save registers in bank 0 into memory stack */
119	st8 [r31] = r30, -8 ;; /* save old stack pointer */	119	st8 [r31] = r30, -8 ;; /* save old stack pointer */
120		120
121	st8 [r31] = r29, -8 ;; /* save predicate registers */	121	st8 [r31] = r29, -8 ;; /* save predicate registers */
122		122
123	st8 [r31] = r24, -8 ;; /* save cr.iip */	123	st8 [r31] = r24, -8 ;; /* save cr.iip */
124	st8 [r31] = r25, -8 ;; /* save cr.ipsr */	124	st8 [r31] = r25, -8 ;; /* save cr.ipsr */
125	st8 [r31] = r26, -8 ;; /* save cr.iipa */	125	st8 [r31] = r26, -8 ;; /* save cr.iipa */
126	st8 [r31] = r27, -8 ;; /* save cr.isr */	126	st8 [r31] = r27, -8 ;; /* save cr.isr */
127	st8 [r31] = r28, -8 ;; /* save cr.ifa */	127	st8 [r31] = r28, -8 ;; /* save cr.ifa */
128		128
129	/* 5. RSE switch from interrupted context */	129	/* 5. RSE switch from interrupted context */
130	mov r24 = ar.rsc	130	mov r24 = ar.rsc
131	mov r25 = ar.pfs	131	mov r25 = ar.pfs
132	cover	132	cover
133	mov r26 = cr.ifs	133	mov r26 = cr.ifs
134		134
135	st8 [r31] = r24, -8 ;; /* save ar.rsc */	135	st8 [r31] = r24, -8 ;; /* save ar.rsc */
136	st8 [r31] = r25, -8 ;; /* save ar.pfs */	136	st8 [r31] = r25, -8 ;; /* save ar.pfs */
137	st8 [r31] = r26, -8 /* save ar.ifs */	137	st8 [r31] = r26, -8 /* save ar.ifs */
138		138
-		139	and r24 = ~(RSC_PL_MASK), r24 ;;
139	and r30 = ~3, r24 ;;	140	and r30 = ~(RSC_MODE_MASK), r24 ;;
140	mov ar.rsc = r30 ;; /* place RSE in enforced lazy mode */	141	mov ar.rsc = r30 ;; /* update RSE state */
141		142
142	mov r27 = ar.rnat	143	mov r27 = ar.rnat
143	mov r28 = ar.bspstore ;;	144	mov r28 = ar.bspstore ;;
144		145
145	/*	146	/*
146	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.	147	* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
147	*/	148	*/
148	(p1) shr.u r30 = r28, VRN_SHIFT ;;	149	(p1) shr.u r30 = r28, VRN_SHIFT ;;
149	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;	150	(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
150		151
151	/*	152	/*
152	* If BSPSTORE needs to be switched, p1 is false and p2 is true.	153	* If BSPSTORE needs to be switched, p1 is false and p2 is true.
153	*/	154	*/
154	(p1) mov r30 = r28	155	(p1) mov r30 = r28
155	(p2) mov r30 = R_KSTACK_BSP ;;	156	(p2) mov r30 = R_KSTACK_BSP ;;
156	(p2) mov ar.bspstore = r30 ;;	157	(p2) mov ar.bspstore = r30 ;;
157		158
158	mov r29 = ar.bsp	159	mov r29 = ar.bsp
159		160
160	st8 [r31] = r27, -8 ;; /* save ar.rnat */	161	st8 [r31] = r27, -8 ;; /* save ar.rnat */
161	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */	162	st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
162	st8 [r31] = r28, -8 ;; /* save ar.bspstore */	163	st8 [r31] = r28, -8 ;; /* save ar.bspstore */
163	st8 [r31] = r29, -8 /* save ar.bsp */	164	st8 [r31] = r29, -8 /* save ar.bsp */
164		165
165	mov ar.rsc = r24 /* restore RSE's setting */	166	mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
166		167
167	/* steps 6 - 15 are done by heavyweight_handler_inner() */	168	/* steps 6 - 15 are done by heavyweight_handler_inner() */
168	mov R_RET = b0 /* save b0 belonging to interrupted context */	169	mov R_RET = b0 /* save b0 belonging to interrupted context */
169	br.call.sptk.many b0 = heavyweight_handler_inner	170	br.call.sptk.many b0 = heavyweight_handler_inner
170	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */	171	0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
171		172
172	/* 16. RSE switch to interrupted context */	173	/* 16. RSE switch to interrupted context */
173	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */	174	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
174		175
175	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;	176	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
176		177
177	ld8 r30 = [r31], +8 ;; /* load ar.bsp */	178	ld8 r30 = [r31], +8 ;; /* load ar.bsp */
178	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */	179	ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
179	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */	180	ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
180	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */	181	sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
181	shl r27 = r27, 16	182	shl r27 = r27, 16
182		183
183	mov r24 = ar.rsc ;;	184	mov r24 = ar.rsc ;;
184	and r30 = ~3, r24 ;;	185	and r30 = ~3, r24 ;;
185	or r24 = r30 , r27 ;;	186	or r24 = r30 , r27 ;;
186	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */	187	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
187		188
188	loadrs /* (step 3) */	189	loadrs /* (step 3) */
189		190
190	ld8 r27 = [r31], +8 ;; /* load ar.rnat */	191	ld8 r27 = [r31], +8 ;; /* load ar.rnat */
191	ld8 r26 = [r31], +8 ;; /* load cr.ifs */	192	ld8 r26 = [r31], +8 ;; /* load cr.ifs */
192	ld8 r25 = [r31], +8 ;; /* load ar.pfs */	193	ld8 r25 = [r31], +8 ;; /* load ar.pfs */
193	ld8 r24 = [r31], +8 ;; /* load ar.rsc */	194	ld8 r24 = [r31], +8 ;; /* load ar.rsc */
194		195
195	mov ar.bspstore = r29 ;; /* (step 4) */	196	mov ar.bspstore = r29 ;; /* (step 4) */
196	mov ar.rnat = r27 /* (step 5) */	197	mov ar.rnat = r27 /* (step 5) */
197		198
198	mov ar.pfs = r25 /* (step 6) */	199	mov ar.pfs = r25 /* (step 6) */
199	mov cr.ifs = r26	200	mov cr.ifs = r26
200		201
201	mov ar.rsc = r24 /* (step 7) */	202	mov ar.rsc = r24 /* (step 7) */
202		203
203	/* 17. restore interruption state from memory stack */	204	/* 17. restore interruption state from memory stack */
204	ld8 r28 = [r31], +8 ;; /* load cr.ifa */	205	ld8 r28 = [r31], +8 ;; /* load cr.ifa */
205	ld8 r27 = [r31], +8 ;; /* load cr.isr */	206	ld8 r27 = [r31], +8 ;; /* load cr.isr */
206	ld8 r26 = [r31], +8 ;; /* load cr.iipa */	207	ld8 r26 = [r31], +8 ;; /* load cr.iipa */
207	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */	208	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
208	ld8 r24 = [r31], +8 ;; /* load cr.iip */	209	ld8 r24 = [r31], +8 ;; /* load cr.iip */
209		210
210	mov cr.iip = r24	211	mov cr.iip = r24
211	mov cr.ipsr = r25	212	mov cr.ipsr = r25
212	mov cr.iipa = r26	213	mov cr.iipa = r26
213	mov cr.isr = r27	214	mov cr.isr = r27
214	mov cr.ifa = r28	215	mov cr.ifa = r28
215		216
216	/* 18. restore predicate registers from memory stack */	217	/* 18. restore predicate registers from memory stack */
217	ld8 r29 = [r31], +8 ;; /* load predicate registers */	218	ld8 r29 = [r31], +8 ;; /* load predicate registers */
218	mov pr = r29	219	mov pr = r29
219		220
220	/* 19. return from interruption */	221	/* 19. return from interruption */
221	ld8 r12 = [r31] /* load stack pointer */	222	ld8 r12 = [r31] /* load stack pointer */
222	rfi ;;	223	rfi ;;
223		224
224	.global heavyweight_handler_inner	225	.global heavyweight_handler_inner
225	heavyweight_handler_inner:	226	heavyweight_handler_inner:
226	/*	227	/*
227	* From this point, the rest of the interrupted context	228	* From this point, the rest of the interrupted context
228	* will be preserved in stacked registers and backing store.	229	* will be preserved in stacked registers and backing store.
229	*/	230	*/
230	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;	231	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
231		232
232	/* bank 0 is going to be shadowed, copy essential data from there */	233	/* bank 0 is going to be shadowed, copy essential data from there */
233	mov loc1 = R_RET /* b0 belonging to interrupted context */	234	mov loc1 = R_RET /* b0 belonging to interrupted context */
234	mov loc2 = R_HANDLER	235	mov loc2 = R_HANDLER
235	mov out0 = R_OFFS	236	mov out0 = R_OFFS
236		237
237	add out1 = STACK_SCRATCH_AREA_SIZE, r12	238	add out1 = STACK_SCRATCH_AREA_SIZE, r12
238		239
239	/* 6. switch to bank 1 and reenable PSR.ic */	240	/* 6. switch to bank 1 and reenable PSR.ic */
240	ssm PSR_IC_MASK	241	ssm PSR_IC_MASK
241	bsw.1 ;;	242	bsw.1 ;;
242	srlz.d	243	srlz.d
243		244
244	/* 7. preserve branch and application registers */	245	/* 7. preserve branch and application registers */
245	mov loc3 = ar.unat	246	mov loc3 = ar.unat
246	mov loc4 = ar.lc	247	mov loc4 = ar.lc
247	mov loc5 = ar.ec	248	mov loc5 = ar.ec
248	mov loc6 = ar.ccv	249	mov loc6 = ar.ccv
249	mov loc7 = ar.csd	250	mov loc7 = ar.csd
250	mov loc8 = ar.ssd	251	mov loc8 = ar.ssd
251		252
252	mov loc9 = b0	253	mov loc9 = b0
253	mov loc10 = b1	254	mov loc10 = b1
254	mov loc11 = b2	255	mov loc11 = b2
255	mov loc12 = b3	256	mov loc12 = b3
256	mov loc13 = b4	257	mov loc13 = b4
257	mov loc14 = b5	258	mov loc14 = b5
258	mov loc15 = b6	259	mov loc15 = b6
259	mov loc16 = b7	260	mov loc16 = b7
260		261
261	/* 8. preserve general and floating-point registers */	262	/* 8. preserve general and floating-point registers */
262	/* TODO: save floating-point context */	263	/* TODO: save floating-point context */
263	mov loc17 = r1	264	mov loc17 = r1
264	mov loc18 = r2	265	mov loc18 = r2
265	mov loc19 = r3	266	mov loc19 = r3
266	mov loc20 = r4	267	mov loc20 = r4
267	mov loc21 = r5	268	mov loc21 = r5
268	mov loc22 = r6	269	mov loc22 = r6
269	mov loc23 = r7	270	mov loc23 = r7
270	mov loc24 = r8	271	mov loc24 = r8
271	mov loc25 = r9	272	mov loc25 = r9
272	mov loc26 = r10	273	mov loc26 = r10
273	mov loc27 = r11	274	mov loc27 = r11
274	/* skip r12 (stack pointer) */	275	/* skip r12 (stack pointer) */
275	mov loc28 = r13	276	mov loc28 = r13
276	mov loc29 = r14	277	mov loc29 = r14
277	mov loc30 = r15	278	mov loc30 = r15
278	mov loc31 = r16	279	mov loc31 = r16
279	mov loc32 = r17	280	mov loc32 = r17
280	mov loc33 = r18	281	mov loc33 = r18
281	mov loc34 = r19	282	mov loc34 = r19
282	mov loc35 = r20	283	mov loc35 = r20
283	mov loc36 = r21	284	mov loc36 = r21
284	mov loc37 = r22	285	mov loc37 = r22
285	mov loc38 = r23	286	mov loc38 = r23
286	mov loc39 = r24	287	mov loc39 = r24
287	mov loc40 = r25	288	mov loc40 = r25
288	mov loc41 = r26	289	mov loc41 = r26
289	mov loc42 = r27	290	mov loc42 = r27
290	mov loc43 = r28	291	mov loc43 = r28
291	mov loc44 = r29	292	mov loc44 = r29
292	mov loc45 = r30	293	mov loc45 = r30
293	mov loc46 = r31	294	mov loc46 = r31
294		295
295	/* 9. skipped (will not enable interrupts) */	296	/* 9. skipped (will not enable interrupts) */
296	/*	297	/*
297	* ssm PSR_I_MASK	298	* ssm PSR_I_MASK
298	* ;;	299	* ;;
299	* srlz.d	300	* srlz.d
300	*/	301	*/
301		302
302	/* 10. call handler */	303	/* 10. call handler */
-		304	movl r1 = _hardcoded_load_address
-		305
303	mov b1 = loc2	306	mov b1 = loc2
304	br.call.sptk.many b0 = b1	307	br.call.sptk.many b0 = b1
305		308
306	/* 11. return from handler */	309	/* 11. return from handler */
307	0:	310	0:
308		311
309	/* 12. skipped (will not disable interrupts) */	312	/* 12. skipped (will not disable interrupts) */
310	/*	313	/*
311	* rsm PSR_I_MASK	314	* rsm PSR_I_MASK
312	* ;;	315	* ;;
313	* srlz.d	316	* srlz.d
314	*/	317	*/
315		318
316	/* 13. restore general and floating-point registers */	319	/* 13. restore general and floating-point registers */
317	/* TODO: restore floating-point context */	320	/* TODO: restore floating-point context */
318	mov r1 = loc17	321	mov r1 = loc17
319	mov r2 = loc18	322	mov r2 = loc18
320	mov r3 = loc19	323	mov r3 = loc19
321	mov r4 = loc20	324	mov r4 = loc20
322	mov r5 = loc21	325	mov r5 = loc21
323	mov r6 = loc22	326	mov r6 = loc22
324	mov r7 = loc23	327	mov r7 = loc23
325	mov r8 = loc24	328	mov r8 = loc24
326	mov r9 = loc25	329	mov r9 = loc25
327	mov r10 = loc26	330	mov r10 = loc26
328	mov r11 = loc27	331	mov r11 = loc27
329	/* skip r12 (stack pointer) */	332	/* skip r12 (stack pointer) */
330	mov r13 = loc28	333	mov r13 = loc28
331	mov r14 = loc29	334	mov r14 = loc29
332	mov r15 = loc30	335	mov r15 = loc30
333	mov r16 = loc31	336	mov r16 = loc31
334	mov r17 = loc32	337	mov r17 = loc32
335	mov r18 = loc33	338	mov r18 = loc33
336	mov r19 = loc34	339	mov r19 = loc34
337	mov r20 = loc35	340	mov r20 = loc35
338	mov r21 = loc36	341	mov r21 = loc36
339	mov r22 = loc37	342	mov r22 = loc37
340	mov r23 = loc38	343	mov r23 = loc38
341	mov r24 = loc39	344	mov r24 = loc39
342	mov r25 = loc40	345	mov r25 = loc40
343	mov r26 = loc41	346	mov r26 = loc41
344	mov r27 = loc42	347	mov r27 = loc42
345	mov r28 = loc43	348	mov r28 = loc43
346	mov r29 = loc44	349	mov r29 = loc44
347	mov r30 = loc45	350	mov r30 = loc45
348	mov r31 = loc46	351	mov r31 = loc46
349		352
350	/* 14. restore branch and application registers */	353	/* 14. restore branch and application registers */
351	mov ar.unat = loc3	354	mov ar.unat = loc3
352	mov ar.lc = loc4	355	mov ar.lc = loc4
353	mov ar.ec = loc5	356	mov ar.ec = loc5
354	mov ar.ccv = loc6	357	mov ar.ccv = loc6
355	mov ar.csd = loc7	358	mov ar.csd = loc7
356	mov ar.ssd = loc8	359	mov ar.ssd = loc8
357		360
358	mov b0 = loc9	361	mov b0 = loc9
359	mov b1 = loc10	362	mov b1 = loc10
360	mov b2 = loc11	363	mov b2 = loc11
361	mov b3 = loc12	364	mov b3 = loc12
362	mov b4 = loc13	365	mov b4 = loc13
363	mov b5 = loc14	366	mov b5 = loc14
364	mov b6 = loc15	367	mov b6 = loc15
365	mov b7 = loc16	368	mov b7 = loc16
366		369
367	/* 15. disable PSR.ic and switch to bank 0 */	370	/* 15. disable PSR.ic and switch to bank 0 */
368	rsm PSR_IC_MASK	371	rsm PSR_IC_MASK
369	bsw.0 ;;	372	bsw.0 ;;
370	srlz.d	373	srlz.d
371		374
372	mov R_RET = loc1	375	mov R_RET = loc1
373	mov ar.pfs = loc0	376	mov ar.pfs = loc0
374	br.ret.sptk.many b0	377	br.ret.sptk.many b0
375		378
376	.global ivt	379	.global ivt
377	.align 32768	380	.align 32768
378	ivt:	381	ivt:
379	HEAVYWEIGHT_HANDLER 0x0000	382	HEAVYWEIGHT_HANDLER 0x0000
380	HEAVYWEIGHT_HANDLER 0x0400	383	HEAVYWEIGHT_HANDLER 0x0400
381	HEAVYWEIGHT_HANDLER 0x0800	384	HEAVYWEIGHT_HANDLER 0x0800
382	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault	385	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
383	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault	386	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
384	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault	387	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
385	HEAVYWEIGHT_HANDLER 0x1800	388	HEAVYWEIGHT_HANDLER 0x1800
386	HEAVYWEIGHT_HANDLER 0x1c00	389	HEAVYWEIGHT_HANDLER 0x1c00
387	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault	390	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
388	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault	391	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
389	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault	392	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
390	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction	393	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
391	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */	394	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
392	HEAVYWEIGHT_HANDLER 0x3400	395	HEAVYWEIGHT_HANDLER 0x3400
393	HEAVYWEIGHT_HANDLER 0x3800	396	HEAVYWEIGHT_HANDLER 0x3800
394	HEAVYWEIGHT_HANDLER 0x3c00	397	HEAVYWEIGHT_HANDLER 0x3c00
395	HEAVYWEIGHT_HANDLER 0x4000	398	HEAVYWEIGHT_HANDLER 0x4000
396	HEAVYWEIGHT_HANDLER 0x4400	399	HEAVYWEIGHT_HANDLER 0x4400
397	HEAVYWEIGHT_HANDLER 0x4800	400	HEAVYWEIGHT_HANDLER 0x4800
398	HEAVYWEIGHT_HANDLER 0x4c00	401	HEAVYWEIGHT_HANDLER 0x4c00
399		402
400	HEAVYWEIGHT_HANDLER 0x5000 page_not_present	403	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
401	HEAVYWEIGHT_HANDLER 0x5100	404	HEAVYWEIGHT_HANDLER 0x5100
402	HEAVYWEIGHT_HANDLER 0x5200	405	HEAVYWEIGHT_HANDLER 0x5200
403	HEAVYWEIGHT_HANDLER 0x5300	406	HEAVYWEIGHT_HANDLER 0x5300
404	HEAVYWEIGHT_HANDLER 0x5400 general_exception	407	HEAVYWEIGHT_HANDLER 0x5400 general_exception
405	HEAVYWEIGHT_HANDLER 0x5500	408	HEAVYWEIGHT_HANDLER 0x5500
406	HEAVYWEIGHT_HANDLER 0x5600	409	HEAVYWEIGHT_HANDLER 0x5600
407	HEAVYWEIGHT_HANDLER 0x5700	410	HEAVYWEIGHT_HANDLER 0x5700
408	HEAVYWEIGHT_HANDLER 0x5800	411	HEAVYWEIGHT_HANDLER 0x5800
409	HEAVYWEIGHT_HANDLER 0x5900	412	HEAVYWEIGHT_HANDLER 0x5900
410	HEAVYWEIGHT_HANDLER 0x5a00	413	HEAVYWEIGHT_HANDLER 0x5a00
411	HEAVYWEIGHT_HANDLER 0x5b00	414	HEAVYWEIGHT_HANDLER 0x5b00
412	HEAVYWEIGHT_HANDLER 0x5c00	415	HEAVYWEIGHT_HANDLER 0x5c00
413	HEAVYWEIGHT_HANDLER 0x5d00	416	HEAVYWEIGHT_HANDLER 0x5d00
414	HEAVYWEIGHT_HANDLER 0x5e00	417	HEAVYWEIGHT_HANDLER 0x5e00
415	HEAVYWEIGHT_HANDLER 0x5f00	418	HEAVYWEIGHT_HANDLER 0x5f00
416		419
417	HEAVYWEIGHT_HANDLER 0x6000	420	HEAVYWEIGHT_HANDLER 0x6000
418	HEAVYWEIGHT_HANDLER 0x6100	421	HEAVYWEIGHT_HANDLER 0x6100
419	HEAVYWEIGHT_HANDLER 0x6200	422	HEAVYWEIGHT_HANDLER 0x6200
420	HEAVYWEIGHT_HANDLER 0x6300	423	HEAVYWEIGHT_HANDLER 0x6300
421	HEAVYWEIGHT_HANDLER 0x6400	424	HEAVYWEIGHT_HANDLER 0x6400
422	HEAVYWEIGHT_HANDLER 0x6500	425	HEAVYWEIGHT_HANDLER 0x6500
423	HEAVYWEIGHT_HANDLER 0x6600	426	HEAVYWEIGHT_HANDLER 0x6600
424	HEAVYWEIGHT_HANDLER 0x6700	427	HEAVYWEIGHT_HANDLER 0x6700
425	HEAVYWEIGHT_HANDLER 0x6800	428	HEAVYWEIGHT_HANDLER 0x6800
426	HEAVYWEIGHT_HANDLER 0x6900	429	HEAVYWEIGHT_HANDLER 0x6900
427	HEAVYWEIGHT_HANDLER 0x6a00	430	HEAVYWEIGHT_HANDLER 0x6a00
428	HEAVYWEIGHT_HANDLER 0x6b00	431	HEAVYWEIGHT_HANDLER 0x6b00
429	HEAVYWEIGHT_HANDLER 0x6c00	432	HEAVYWEIGHT_HANDLER 0x6c00
430	HEAVYWEIGHT_HANDLER 0x6d00	433	HEAVYWEIGHT_HANDLER 0x6d00
431	HEAVYWEIGHT_HANDLER 0x6e00	434	HEAVYWEIGHT_HANDLER 0x6e00
432	HEAVYWEIGHT_HANDLER 0x6f00	435	HEAVYWEIGHT_HANDLER 0x6f00
433		436
434	HEAVYWEIGHT_HANDLER 0x7000	437	HEAVYWEIGHT_HANDLER 0x7000
435	HEAVYWEIGHT_HANDLER 0x7100	438	HEAVYWEIGHT_HANDLER 0x7100
436	HEAVYWEIGHT_HANDLER 0x7200	439	HEAVYWEIGHT_HANDLER 0x7200
437	HEAVYWEIGHT_HANDLER 0x7300	440	HEAVYWEIGHT_HANDLER 0x7300
438	HEAVYWEIGHT_HANDLER 0x7400	441	HEAVYWEIGHT_HANDLER 0x7400
439	HEAVYWEIGHT_HANDLER 0x7500	442	HEAVYWEIGHT_HANDLER 0x7500
440	HEAVYWEIGHT_HANDLER 0x7600	443	HEAVYWEIGHT_HANDLER 0x7600
441	HEAVYWEIGHT_HANDLER 0x7700	444	HEAVYWEIGHT_HANDLER 0x7700
442	HEAVYWEIGHT_HANDLER 0x7800	445	HEAVYWEIGHT_HANDLER 0x7800
443	HEAVYWEIGHT_HANDLER 0x7900	446	HEAVYWEIGHT_HANDLER 0x7900
444	HEAVYWEIGHT_HANDLER 0x7a00	447	HEAVYWEIGHT_HANDLER 0x7a00
445	HEAVYWEIGHT_HANDLER 0x7b00	448	HEAVYWEIGHT_HANDLER 0x7b00
446	HEAVYWEIGHT_HANDLER 0x7c00	449	HEAVYWEIGHT_HANDLER 0x7c00
447	HEAVYWEIGHT_HANDLER 0x7d00	450	HEAVYWEIGHT_HANDLER 0x7d00
448	HEAVYWEIGHT_HANDLER 0x7e00	451	HEAVYWEIGHT_HANDLER 0x7e00
449	HEAVYWEIGHT_HANDLER 0x7f00	452	HEAVYWEIGHT_HANDLER 0x7f00
450		453

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/ivt.S – Rev 916 → 919