WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/src/ivt.S


#
# Copyright (C) 2005 Jakub Vana
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/stack.h>
#include <arch/register.h>
 
#define STACK_ITEMS		12
#define STACK_FRAME_SIZE	((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
 
#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
#error Memory stack must be 16-byte aligned.
#endif
 
/** Heavyweight interrupt handler
 *
 * This macro roughly follows steps from 1 to 19 described in
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 *
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
 * This goal is achieved by using procedure calls after RSE becomes operational.
 *
 * Some steps are skipped (enabling and disabling interrupts).
 * Some steps are not fully supported yet (e.g. interruptions
 * from userspace and floating-point context).
 *
 * @param offs Offset from the beginning of IVT.
 * @param handler Interrupt handler address.
 */
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
    .org ivt + \offs
	mov r24 = \offs
	movl r25 = \handler ;;
	mov ar.k0 = r24
	mov ar.k1 = r25
	br heavyweight_handler
.endm
 
.global heavyweight_handler
heavyweight_handler:
    /* 1. copy interrupt registers into bank 0 */
	mov r24 = cr.iip
	mov r25 = cr.ipsr
	mov r26 = cr.iipa
	mov r27 = cr.isr
	mov r28 = cr.ifa
	
    /* 2. preserve predicate register into bank 0 */
	mov r29 = pr ;;
	
    /* 3. switch to kernel memory stack */
	/* TODO: support interruptions from userspace */
	/* assume kernel stack */
	
	add r31 = -8, r12 ;;
	add r12 = -STACK_FRAME_SIZE, r12
 
    /* 4. save registers in bank 0 into memory stack */	
	st8 [r31] = r29, -8 ;;	/* save predicate registers */
 
	st8 [r31] = r24, -8 ;;	/* save cr.iip */
	st8 [r31] = r25, -8 ;;	/* save cr.ipsr */
	st8 [r31] = r26, -8 ;;	/* save cr.iipa */
	st8 [r31] = r27, -8 ;;	/* save cr.isr */
	st8 [r31] = r28, -8	/* save cr.ifa */		
 
    /* 5. RSE switch from interrupted context */
	mov r24 = ar.rsc
	mov r25 = ar.pfs
	cover
	mov r26 = cr.ifs
	
	st8 [r31] = r24, -8;;	/* save ar.rsc */
	st8 [r31] = r25, -8;;	/* save ar.pfs */
	st8 [r31] = r26, -8	/* save ar.ifs */
	
	and r30 = ~3, r24 ;;
	mov ar.rsc = r30 ;;	/* place RSE in enforced lazy mode */
	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/* assume kernel backing store */
	/* mov ar.bspstore = r28 ;; */
	
	mov r29 = ar.bsp
	
	st8 [r31] = r27, -8 ;;	/* save ar.rnat */
	st8 [r31] = r28, -8 ;;	/* save ar.bspstore */
	st8 [r31] = r29, -8	/* save ar.bsp */
	
	mov ar.rsc = r24	/* restore RSE's setting */
	
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
	mov r24 = b0 		/* save b0 belonging to interrupted context */
	mov r26 = ar.k0
	mov r25 = ar.k1
	br.call.sptk.many rp = heavyweight_handler_inner
0:	mov b0 = r24		/* restore b0 belonging to the interrupted context */
 
    /* 16. RSE switch to interrupted context */
	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
 
	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
 
	mov r28 = ar.bspstore   	/* calculate loadrs (step 2) */
	ld8 r29 = [r31], +8 ;;		/* load ar.bsp */
	sub r27 = r29 , r28 ;;
	shl r27 = r27, 16
 
	mov r24 = ar.rsc ;;
	and r30 = ~3, r24 ;;
	or  r24 = r30 , r27 ;;     
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
 
	loadrs 				/* (step 3) */
 
	ld8 r28 = [r31], +8 ;;    	/* load ar.bspstore */
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
	/* mov ar.bspstore = r28 ;; */	/* (step 4) */
	/* mov ar.rnat = r27 */		/* (step 5) */
 
	mov ar.pfs = r25		/* (step 6) */
	mov cr.ifs = r26	
 
	mov ar.rsc = r24		/* (step 7) */
 
    /* 17. restore interruption state from memory stack */
	ld8 r28 = [r31], +8 ;;	/* load cr.ifa */		
	ld8 r27 = [r31], +8 ;;	/* load cr.isr */
	ld8 r26 = [r31], +8 ;;	/* load cr.iipa */
	ld8 r25 = [r31], +8 ;;	/* load cr.ipsr */
	ld8 r24 = [r31], +8 ;;	/* load cr.iip */
 
	mov cr.iip = r24
	mov cr.ipsr = r25
	mov cr.iipa = r26
	mov cr.isr = r27
	mov cr.ifa = r28
 
    /* 18. restore predicate registers from memory stack */
	ld8 r29 = [r31] , -8 ;;	/* load predicate registers */
	mov pr = r29
	
    /* 19. return from interruption */
    	add r12 = STACK_FRAME_SIZE, r12
	rfi ;;
 
.global heavyweight_handler_inner
heavyweight_handler_inner:
	/*
	 * From this point, the rest of the interrupted context
	 * will be preserved in stacked registers and backing store.
	 */
	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
	
	/* bank 0 is going to be shadowed, copy essential data from there */
	mov loc1 = r24	/* b0 belonging to interrupted context */
	mov loc2 = r25
	mov out0 = r26
	
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
    /* 6. switch to bank 1 and reenable PSR.ic */
	ssm PSR_IC_MASK
	bsw.1 ;;
	srlz.d
	
    /* 7. preserve branch and application registers */
    	mov loc3 = ar.unat
	mov loc4 = ar.lc
	mov loc5 = ar.ec
	mov loc6 = ar.ccv
	mov loc7 = ar.csd
	mov loc8 = ar.ssd
	
	mov loc9 = b0
	mov loc10 = b1
	mov loc11 = b2
	mov loc12 = b3
	mov loc13 = b4
	mov loc14 = b5
	mov loc15 = b6
	mov loc16 = b7
	
    /* 8. preserve general and floating-point registers */
	/* TODO: save floating-point context */
	mov loc17 = r1
	mov loc18 = r2
	mov loc19 = r3
	mov loc20 = r4
	mov loc21 = r5
	mov loc22 = r6
	mov loc23 = r7
	mov loc24 = r8
	mov loc25 = r9
	mov loc26 = r10
	mov loc27 = r11
	/* skip r12 (stack pointer) */
	mov loc28 = r13
	mov loc29 = r14
	mov loc30 = r15
	mov loc31 = r16
	mov loc32 = r17
	mov loc33 = r18
	mov loc34 = r19
	mov loc35 = r20
	mov loc36 = r21
	mov loc37 = r22
	mov loc38 = r23
	mov loc39 = r24
	mov loc40 = r25
	mov loc41 = r26
	mov loc42 = r27
	mov loc43 = r28
	mov loc44 = r29
	mov loc45 = r30
	mov loc46 = r31
    
    /* 9. skipped (will not enable interrupts) */
	/*
    	 * ssm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 10. call handler */
    	mov b1 = loc2
	br.call.sptk.many b0 = b1
 
    /* 11. return from handler */
0:
	
    /* 12. skipped (will not disable interrupts) */
	/*
    	 * rsm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 13. restore general and floating-point registers */
	/* TODO: restore floating-point context */
	mov r1 = loc17
	mov r2 = loc18
	mov r3 = loc19
	mov r4 = loc20
	mov r5 = loc21
	mov r6 = loc22
	mov r7 = loc23
	mov r8 = loc24
	mov r9 = loc25
	mov r10 = loc26
	mov r11 = loc27
	/* skip r12 (stack pointer) */
	mov r13 = loc28
	mov r14 = loc29
	mov r15 = loc30
	mov r16 = loc31
	mov r17 = loc32
	mov r18 = loc33
	mov r19 = loc34
	mov r20 = loc35
	mov r21 = loc36
	mov r22 = loc37
	mov r23 = loc38
	mov r24 = loc39
	mov r25 = loc40
	mov r26 = loc41 
	mov r27 = loc42
	mov r28 = loc43
	mov r29 = loc44
	mov r30 = loc45
	mov r31 = loc46
	
    /* 14. restore branch and application registers */
    	mov ar.unat = loc3
	mov ar.lc = loc4
	mov ar.ec = loc5
	mov ar.ccv = loc6
	mov ar.csd = loc7
	mov ar.ssd = loc8
	
	mov b0 = loc9
	mov b1 = loc10
	mov b2 = loc11
	mov b3 = loc12
	mov b4 = loc13
	mov b5 = loc14
	mov b6 = loc15
	mov b7 = loc16
	
    /* 15. disable PSR.ic and switch to bank 0 */
	rsm PSR_IC_MASK
	bsw.0 ;;
	srlz.d
 
	mov r24 = loc1
	mov ar.pfs = loc0
	br.ret.sptk.many b0
 
.global ivt
.align 32768
ivt:
	HEAVYWEIGHT_HANDLER 0x0000
	HEAVYWEIGHT_HANDLER 0x0400
	HEAVYWEIGHT_HANDLER 0x0800
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
	HEAVYWEIGHT_HANDLER 0x1800
	HEAVYWEIGHT_HANDLER 0x1c00
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
	HEAVYWEIGHT_HANDLER 0x3400
	HEAVYWEIGHT_HANDLER 0x3800
	HEAVYWEIGHT_HANDLER 0x3c00
	HEAVYWEIGHT_HANDLER 0x4000
	HEAVYWEIGHT_HANDLER 0x4400
	HEAVYWEIGHT_HANDLER 0x4800
	HEAVYWEIGHT_HANDLER 0x4c00
 
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
	HEAVYWEIGHT_HANDLER 0x5100
	HEAVYWEIGHT_HANDLER 0x5200
	HEAVYWEIGHT_HANDLER 0x5300
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
	HEAVYWEIGHT_HANDLER 0x5500
	HEAVYWEIGHT_HANDLER 0x5600
	HEAVYWEIGHT_HANDLER 0x5700
	HEAVYWEIGHT_HANDLER 0x5800
	HEAVYWEIGHT_HANDLER 0x5900
	HEAVYWEIGHT_HANDLER 0x5a00
	HEAVYWEIGHT_HANDLER 0x5b00
	HEAVYWEIGHT_HANDLER 0x5c00
	HEAVYWEIGHT_HANDLER 0x5d00
	HEAVYWEIGHT_HANDLER 0x5e00
	HEAVYWEIGHT_HANDLER 0x5f00
	
	HEAVYWEIGHT_HANDLER 0x6000
	HEAVYWEIGHT_HANDLER 0x6100
	HEAVYWEIGHT_HANDLER 0x6200
	HEAVYWEIGHT_HANDLER 0x6300
	HEAVYWEIGHT_HANDLER 0x6400
	HEAVYWEIGHT_HANDLER 0x6500
	HEAVYWEIGHT_HANDLER 0x6600
	HEAVYWEIGHT_HANDLER 0x6700
	HEAVYWEIGHT_HANDLER 0x6800
	HEAVYWEIGHT_HANDLER 0x6900
	HEAVYWEIGHT_HANDLER 0x6a00
	HEAVYWEIGHT_HANDLER 0x6b00
	HEAVYWEIGHT_HANDLER 0x6c00
	HEAVYWEIGHT_HANDLER 0x6d00
	HEAVYWEIGHT_HANDLER 0x6e00
	HEAVYWEIGHT_HANDLER 0x6f00
 
	HEAVYWEIGHT_HANDLER 0x7000
	HEAVYWEIGHT_HANDLER 0x7100
	HEAVYWEIGHT_HANDLER 0x7200
	HEAVYWEIGHT_HANDLER 0x7300
	HEAVYWEIGHT_HANDLER 0x7400
	HEAVYWEIGHT_HANDLER 0x7500
	HEAVYWEIGHT_HANDLER 0x7600
	HEAVYWEIGHT_HANDLER 0x7700
	HEAVYWEIGHT_HANDLER 0x7800
	HEAVYWEIGHT_HANDLER 0x7900
	HEAVYWEIGHT_HANDLER 0x7a00
	HEAVYWEIGHT_HANDLER 0x7b00
	HEAVYWEIGHT_HANDLER 0x7c00
	HEAVYWEIGHT_HANDLER 0x7d00
	HEAVYWEIGHT_HANDLER 0x7e00
	HEAVYWEIGHT_HANDLER 0x7f00
 

Rev 534	Rev 899
1	#	1	#
2	# Copyright (C) 2005 Jakub Vana	2	# Copyright (C) 2005 Jakub Vana
3	# Copyright (C) 2005 Jakub Jermar	3	# Copyright (C) 2005 Jakub Jermar
4	# All rights reserved.	4	# All rights reserved.
5	#	5	#
6	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
7	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
8	# are met:	8	# are met:
9	#	9	#
10	# - Redistributions of source code must retain the above copyright	10	# - Redistributions of source code must retain the above copyright
11	# notice, this list of conditions and the following disclaimer.	11	# notice, this list of conditions and the following disclaimer.
12	# - Redistributions in binary form must reproduce the above copyright	12	# - Redistributions in binary form must reproduce the above copyright
13	# notice, this list of conditions and the following disclaimer in the	13	# notice, this list of conditions and the following disclaimer in the
14	# documentation and/or other materials provided with the distribution.	14	# documentation and/or other materials provided with the distribution.
15	# - The name of the author may not be used to endorse or promote products	15	# - The name of the author may not be used to endorse or promote products
16	# derived from this software without specific prior written permission.	16	# derived from this software without specific prior written permission.
17	#	17	#
18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	#	28	#
29		29
30	#include <arch/stack.h>	30	#include <arch/stack.h>
31	#include <arch/register.h>	31	#include <arch/register.h>
32		32
33	#define STACK_ITEMS 12	33	#define STACK_ITEMS 12
34	#define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)	34	#define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
35		35
36	#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)	36	#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
37	#error Memory stack must be 16-byte aligned.	37	#error Memory stack must be 16-byte aligned.
38	#endif	38	#endif
39		39
40	/** Heavyweight interrupt handler	40	/** Heavyweight interrupt handler
41	*	41	*
42	* This macro roughly follows steps from 1 to 19 described in	42	* This macro roughly follows steps from 1 to 19 described in
43	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.	43	* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
44	*	44	*
45	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).	45	* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
46	* This goal is achieved by using procedure calls after RSE becomes operational.	46	* This goal is achieved by using procedure calls after RSE becomes operational.
47	*	47	*
48	* Some steps are skipped (enabling and disabling interrupts).	48	* Some steps are skipped (enabling and disabling interrupts).
49	* Some steps are not fully supported yet (e.g. interruptions	49	* Some steps are not fully supported yet (e.g. interruptions
50	* from userspace and floating-point context).	50	* from userspace and floating-point context).
51	*	51	*
52	* @param offs Offset from the beginning of IVT.	52	* @param offs Offset from the beginning of IVT.
53	* @param handler Interrupt handler address.	53	* @param handler Interrupt handler address.
54	*/	54	*/
55	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler	55	.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
56	.org ivt + \offs	56	.org ivt + \offs
57	mov r24 = \offs	57	mov r24 = \offs
58	movl r25 = \handler ;;	58	movl r25 = \handler ;;
59	mov ar.k0 = r24	59	mov ar.k0 = r24
60	mov ar.k1 = r25	60	mov ar.k1 = r25
61	br heavyweight_handler	61	br heavyweight_handler
62	.endm	62	.endm
63		63
64	.global heavyweight_handler	64	.global heavyweight_handler
65	heavyweight_handler:	65	heavyweight_handler:
66	/* 1. copy interrupt registers into bank 0 */	66	/* 1. copy interrupt registers into bank 0 */
67	mov r24 = cr.iip	67	mov r24 = cr.iip
68	mov r25 = cr.ipsr	68	mov r25 = cr.ipsr
69	mov r26 = cr.iipa	69	mov r26 = cr.iipa
70	mov r27 = cr.isr	70	mov r27 = cr.isr
71	mov r28 = cr.ifa	71	mov r28 = cr.ifa
72		72
73	/* 2. preserve predicate register into bank 0 */	73	/* 2. preserve predicate register into bank 0 */
74	mov r29 = pr ;;	74	mov r29 = pr ;;
75		75
76	/* 3. switch to kernel memory stack */	76	/* 3. switch to kernel memory stack */
77	/* TODO: support interruptions from userspace */	77	/* TODO: support interruptions from userspace */
78	/* assume kernel stack */	78	/* assume kernel stack */
79		79
80	add r31 = -8, r12 ;;	80	add r31 = -8, r12 ;;
81	add r12 = -STACK_FRAME_SIZE, r12	81	add r12 = -STACK_FRAME_SIZE, r12
82		82
83	/* 4. save registers in bank 0 into memory stack */	83	/* 4. save registers in bank 0 into memory stack */
84	st8 [r31] = r29, -8 ;; /* save predicate registers */	84	st8 [r31] = r29, -8 ;; /* save predicate registers */
85		85
86	st8 [r31] = r24, -8 ;; /* save cr.iip */	86	st8 [r31] = r24, -8 ;; /* save cr.iip */
87	st8 [r31] = r25, -8 ;; /* save cr.ipsr */	87	st8 [r31] = r25, -8 ;; /* save cr.ipsr */
88	st8 [r31] = r26, -8 ;; /* save cr.iipa */	88	st8 [r31] = r26, -8 ;; /* save cr.iipa */
89	st8 [r31] = r27, -8 ;; /* save cr.isr */	89	st8 [r31] = r27, -8 ;; /* save cr.isr */
90	st8 [r31] = r28, -8 /* save cr.ifa */	90	st8 [r31] = r28, -8 /* save cr.ifa */
91		91
92	/* 5. RSE switch from interrupted context */	92	/* 5. RSE switch from interrupted context */
93	mov r24 = ar.rsc	93	mov r24 = ar.rsc
94	mov r25 = ar.pfs	94	mov r25 = ar.pfs
95	cover	95	cover
96	mov r26 = cr.ifs	96	mov r26 = cr.ifs
97		97
98	st8 [r31] = r24, -8;; /* save ar.rsc */	98	st8 [r31] = r24, -8;; /* save ar.rsc */
99	st8 [r31] = r25, -8;; /* save ar.pfs */	99	st8 [r31] = r25, -8;; /* save ar.pfs */
100	st8 [r31] = r26, -8 /* save ar.ifs */	100	st8 [r31] = r26, -8 /* save ar.ifs */
101		101
102	and r30 = ~3, r24 ;;	102	and r30 = ~3, r24 ;;
103	mov ar.rsc = r30 ;; /* place RSE in enforced lazy mode */	103	mov ar.rsc = r30 ;; /* place RSE in enforced lazy mode */
104		104
105	mov r27 = ar.rnat	105	mov r27 = ar.rnat
106	mov r28 = ar.bspstore ;;	106	mov r28 = ar.bspstore ;;
107		107
108	/* assume kernel backing store */	108	/* assume kernel backing store */
109	/* mov ar.bspstore = r28 ;; */	109	/* mov ar.bspstore = r28 ;; */
110		110
111	mov r29 = ar.bsp	111	mov r29 = ar.bsp
112		112
113	st8 [r31] = r27, -8 ;; /* save ar.rnat */	113	st8 [r31] = r27, -8 ;; /* save ar.rnat */
114	st8 [r31] = r28, -8 ;; /* save ar.bspstore */	114	st8 [r31] = r28, -8 ;; /* save ar.bspstore */
115	st8 [r31] = r29, -8 /* save ar.bsp */	115	st8 [r31] = r29, -8 /* save ar.bsp */
116		116
117	mov ar.rsc = r24 /* restore RSE's setting */	117	mov ar.rsc = r24 /* restore RSE's setting */
118		118
119	/* steps 6 - 15 are done by heavyweight_handler_inner() */	119	/* steps 6 - 15 are done by heavyweight_handler_inner() */
120	mov r24 = b0 /* save b0 belonging to interrupted context */	120	mov r24 = b0 /* save b0 belonging to interrupted context */
121	mov r26 = ar.k0	121	mov r26 = ar.k0
122	mov r25 = ar.k1	122	mov r25 = ar.k1
123	br.call.sptk.many rp = heavyweight_handler_inner	123	br.call.sptk.many rp = heavyweight_handler_inner
124	0: mov b0 = r24 /* restore b0 belonging to the interrupted context */	124	0: mov b0 = r24 /* restore b0 belonging to the interrupted context */
125		125
126	/* 16. RSE switch to interrupted context */	126	/* 16. RSE switch to interrupted context */
127	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */	127	cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
128		128
129	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;	129	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
130		130
131	mov r28 = ar.bspstore /* calculate loadrs (step 2) */	131	mov r28 = ar.bspstore /* calculate loadrs (step 2) */
132	ld8 r29 = [r31], +8 ;; /* load ar.bsp */	132	ld8 r29 = [r31], +8 ;; /* load ar.bsp */
133	sub r27 = r29 , r28 ;;	133	sub r27 = r29 , r28 ;;
134	shl r27 = r27, 16	134	shl r27 = r27, 16
135		135
136	mov r24 = ar.rsc ;;	136	mov r24 = ar.rsc ;;
137	and r30 = ~3, r24 ;;	137	and r30 = ~3, r24 ;;
138	or r24 = r30 , r27 ;;	138	or r24 = r30 , r27 ;;
139	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */	139	mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
140		140
141	loadrs /* (step 3) */	141	loadrs /* (step 3) */
142		142
143	ld8 r28 = [r31], +8 ;; /* load ar.bspstore */	143	ld8 r28 = [r31], +8 ;; /* load ar.bspstore */
144	ld8 r27 = [r31], +8 ;; /* load ar.rnat */	144	ld8 r27 = [r31], +8 ;; /* load ar.rnat */
145	ld8 r26 = [r31], +8 ;; /* load cr.ifs */	145	ld8 r26 = [r31], +8 ;; /* load cr.ifs */
146	ld8 r25 = [r31], +8 ;; /* load ar.pfs */	146	ld8 r25 = [r31], +8 ;; /* load ar.pfs */
147	ld8 r24 = [r31], +8 ;; /* load ar.rsc */	147	ld8 r24 = [r31], +8 ;; /* load ar.rsc */
148		148
149	/* mov ar.bspstore = r28 ;; / / (step 4) */	149	/* mov ar.bspstore = r28 ;; / / (step 4) */
150	/* mov ar.rnat = r27 / / (step 5) */	150	/* mov ar.rnat = r27 / / (step 5) */
151		151
152	mov ar.pfs = r25 /* (step 6) */	152	mov ar.pfs = r25 /* (step 6) */
153	mov cr.ifs = r26	153	mov cr.ifs = r26
154		154
155	mov ar.rsc = r24 /* (step 7) */	155	mov ar.rsc = r24 /* (step 7) */
156		156
157	/* 17. restore interruption state from memory stack */	157	/* 17. restore interruption state from memory stack */
158	ld8 r28 = [r31], +8 ;; /* load cr.ifa */	158	ld8 r28 = [r31], +8 ;; /* load cr.ifa */
159	ld8 r27 = [r31], +8 ;; /* load cr.isr */	159	ld8 r27 = [r31], +8 ;; /* load cr.isr */
160	ld8 r26 = [r31], +8 ;; /* load cr.iipa */	160	ld8 r26 = [r31], +8 ;; /* load cr.iipa */
161	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */	161	ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
162	ld8 r24 = [r31], +8 ;; /* load cr.iip */	162	ld8 r24 = [r31], +8 ;; /* load cr.iip */
163		163
164	mov cr.iip = r24	164	mov cr.iip = r24
165	mov cr.ipsr = r25	165	mov cr.ipsr = r25
166	mov cr.iipa = r26	166	mov cr.iipa = r26
167	mov cr.isr = r27	167	mov cr.isr = r27
168	mov cr.ifa = r28	168	mov cr.ifa = r28
169		169
170	/* 18. restore predicate registers from memory stack */	170	/* 18. restore predicate registers from memory stack */
171	ld8 r29 = [r31] , -8 ;; /* load predicate registers */	171	ld8 r29 = [r31] , -8 ;; /* load predicate registers */
172	mov pr = r29	172	mov pr = r29
173		173
174	/* 19. return from interruption */	174	/* 19. return from interruption */
175	add r12 = STACK_FRAME_SIZE, r12	175	add r12 = STACK_FRAME_SIZE, r12
176	rfi ;;	176	rfi ;;
177		177
178	.global heavyweight_handler_inner	178	.global heavyweight_handler_inner
179	heavyweight_handler_inner:	179	heavyweight_handler_inner:
180	/*	180	/*
181	* From this point, the rest of the interrupted context	181	* From this point, the rest of the interrupted context
182	* will be preserved in stacked registers and backing store.	182	* will be preserved in stacked registers and backing store.
183	*/	183	*/
184	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;	184	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
185		185
186	/* bank 0 is going to be shadowed, copy essential data from there */	186	/* bank 0 is going to be shadowed, copy essential data from there */
187	mov loc1 = r24 /* b0 belonging to interrupted context */	187	mov loc1 = r24 /* b0 belonging to interrupted context */
188	mov loc2 = r25	188	mov loc2 = r25
189	mov out0 = r26	189	mov out0 = r26
190		190
191	add out1 = STACK_SCRATCH_AREA_SIZE, r12	191	add out1 = STACK_SCRATCH_AREA_SIZE, r12
192		192
193	/* 6. switch to bank 1 and reenable PSR.ic */	193	/* 6. switch to bank 1 and reenable PSR.ic */
194	ssm PSR_IC_MASK	194	ssm PSR_IC_MASK
195	bsw.1 ;;	195	bsw.1 ;;
196	srlz.d	196	srlz.d
197		197
198	/* 7. preserve branch and application registers */	198	/* 7. preserve branch and application registers */
199	mov loc3 = ar.unat	199	mov loc3 = ar.unat
200	mov loc4 = ar.lc	200	mov loc4 = ar.lc
201	mov loc5 = ar.ec	201	mov loc5 = ar.ec
202	mov loc6 = ar.ccv	202	mov loc6 = ar.ccv
203	mov loc7 = ar.csd	203	mov loc7 = ar.csd
204	mov loc8 = ar.ssd	204	mov loc8 = ar.ssd
205		205
206	mov loc9 = b0	206	mov loc9 = b0
207	mov loc10 = b1	207	mov loc10 = b1
208	mov loc11 = b2	208	mov loc11 = b2
209	mov loc12 = b3	209	mov loc12 = b3
210	mov loc13 = b4	210	mov loc13 = b4
211	mov loc14 = b5	211	mov loc14 = b5
212	mov loc15 = b6	212	mov loc15 = b6
213	mov loc16 = b7	213	mov loc16 = b7
214		214
215	/* 8. preserve general and floating-point registers */	215	/* 8. preserve general and floating-point registers */
216	/* TODO: save floating-point context */	216	/* TODO: save floating-point context */
217	mov loc17 = r1	217	mov loc17 = r1
218	mov loc18 = r2	218	mov loc18 = r2
219	mov loc19 = r3	219	mov loc19 = r3
220	mov loc20 = r4	220	mov loc20 = r4
221	mov loc21 = r5	221	mov loc21 = r5
222	mov loc22 = r6	222	mov loc22 = r6
223	mov loc23 = r7	223	mov loc23 = r7
224	mov loc24 = r8	224	mov loc24 = r8
225	mov loc25 = r9	225	mov loc25 = r9
226	mov loc26 = r10	226	mov loc26 = r10
227	mov loc27 = r11	227	mov loc27 = r11
228	/* skip r12 (stack pointer) */	228	/* skip r12 (stack pointer) */
229	mov loc28 = r13	229	mov loc28 = r13
230	mov loc29 = r14	230	mov loc29 = r14
231	mov loc30 = r15	231	mov loc30 = r15
232	mov loc31 = r16	232	mov loc31 = r16
233	mov loc32 = r17	233	mov loc32 = r17
234	mov loc33 = r18	234	mov loc33 = r18
235	mov loc34 = r19	235	mov loc34 = r19
236	mov loc35 = r20	236	mov loc35 = r20
237	mov loc36 = r21	237	mov loc36 = r21
238	mov loc37 = r22	238	mov loc37 = r22
239	mov loc38 = r23	239	mov loc38 = r23
240	mov loc39 = r24	240	mov loc39 = r24
241	mov loc40 = r25	241	mov loc40 = r25
242	mov loc41 = r26	242	mov loc41 = r26
243	mov loc42 = r27	243	mov loc42 = r27
244	mov loc43 = r28	244	mov loc43 = r28
245	mov loc44 = r29	245	mov loc44 = r29
246	mov loc45 = r30	246	mov loc45 = r30
247	mov loc46 = r31	247	mov loc46 = r31
248		248
249	/* 9. skipped (will not enable interrupts) */	249	/* 9. skipped (will not enable interrupts) */
250	/*	250	/*
251	* ssm PSR_I_MASK	251	* ssm PSR_I_MASK
252	* ;;	252	* ;;
253	* srlz.d	253	* srlz.d
254	*/	254	*/
255		255
256	/* 10. call handler */	256	/* 10. call handler */
257	mov b1 = loc2	257	mov b1 = loc2
258	br.call.sptk.many b0 = b1	258	br.call.sptk.many b0 = b1
259		259
260	/* 11. return from handler */	260	/* 11. return from handler */
261	0:	261	0:
262		262
263	/* 12. skipped (will not disable interrupts) */	263	/* 12. skipped (will not disable interrupts) */
264	/*	264	/*
265	* rsm PSR_I_MASK	265	* rsm PSR_I_MASK
266	* ;;	266	* ;;
267	* srlz.d	267	* srlz.d
268	*/	268	*/
269		269
270	/* 13. restore general and floating-point registers */	270	/* 13. restore general and floating-point registers */
271	/* TODO: restore floating-point context */	271	/* TODO: restore floating-point context */
272	mov r1 = loc17	272	mov r1 = loc17
273	mov r2 = loc18	273	mov r2 = loc18
274	mov r3 = loc19	274	mov r3 = loc19
275	mov r4 = loc20	275	mov r4 = loc20
276	mov r5 = loc21	276	mov r5 = loc21
277	mov r6 = loc22	277	mov r6 = loc22
278	mov r7 = loc23	278	mov r7 = loc23
279	mov r8 = loc24	279	mov r8 = loc24
280	mov r9 = loc25	280	mov r9 = loc25
281	mov r10 = loc26	281	mov r10 = loc26
282	mov r11 = loc27	282	mov r11 = loc27
283	/* skip r12 (stack pointer) */	283	/* skip r12 (stack pointer) */
284	mov r13 = loc28	284	mov r13 = loc28
285	mov r14 = loc29	285	mov r14 = loc29
286	mov r15 = loc30	286	mov r15 = loc30
287	mov r16 = loc31	287	mov r16 = loc31
288	mov r17 = loc32	288	mov r17 = loc32
289	mov r18 = loc33	289	mov r18 = loc33
290	mov r19 = loc34	290	mov r19 = loc34
291	mov r20 = loc35	291	mov r20 = loc35
292	mov r21 = loc36	292	mov r21 = loc36
293	mov r22 = loc37	293	mov r22 = loc37
294	mov r23 = loc38	294	mov r23 = loc38
295	mov r24 = loc39	295	mov r24 = loc39
296	mov r25 = loc40	296	mov r25 = loc40
297	mov r26 = loc41	297	mov r26 = loc41
298	mov r27 = loc42	298	mov r27 = loc42
299	mov r28 = loc43	299	mov r28 = loc43
300	mov r29 = loc44	300	mov r29 = loc44
301	mov r30 = loc45	301	mov r30 = loc45
302	mov r31 = loc46	302	mov r31 = loc46
303		303
304	/* 14. restore branch and application registers */	304	/* 14. restore branch and application registers */
305	mov ar.unat = loc3	305	mov ar.unat = loc3
306	mov ar.lc = loc4	306	mov ar.lc = loc4
307	mov ar.ec = loc5	307	mov ar.ec = loc5
308	mov ar.ccv = loc6	308	mov ar.ccv = loc6
309	mov ar.csd = loc7	309	mov ar.csd = loc7
310	mov ar.ssd = loc8	310	mov ar.ssd = loc8
311		311
312	mov b0 = loc9	312	mov b0 = loc9
313	mov b1 = loc10	313	mov b1 = loc10
314	mov b2 = loc11	314	mov b2 = loc11
315	mov b3 = loc12	315	mov b3 = loc12
316	mov b4 = loc13	316	mov b4 = loc13
317	mov b5 = loc14	317	mov b5 = loc14
318	mov b6 = loc15	318	mov b6 = loc15
319	mov b7 = loc16	319	mov b7 = loc16
320		320
321	/* 15. disable PSR.ic and switch to bank 0 */	321	/* 15. disable PSR.ic and switch to bank 0 */
322	rsm PSR_IC_MASK	322	rsm PSR_IC_MASK
323	bsw.0 ;;	323	bsw.0 ;;
324	srlz.d	324	srlz.d
325		325
326	mov r24 = loc1	326	mov r24 = loc1
327	mov ar.pfs = loc0	327	mov ar.pfs = loc0
328	br.ret.sptk.many b0	328	br.ret.sptk.many b0
329		329
330	.global ivt	330	.global ivt
331	.align 32768	331	.align 32768
332	ivt:	332	ivt:
333	HEAVYWEIGHT_HANDLER 0x0000	333	HEAVYWEIGHT_HANDLER 0x0000
334	HEAVYWEIGHT_HANDLER 0x0400	334	HEAVYWEIGHT_HANDLER 0x0400
335	HEAVYWEIGHT_HANDLER 0x0800	335	HEAVYWEIGHT_HANDLER 0x0800
336	HEAVYWEIGHT_HANDLER 0x0c00	336	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
337	HEAVYWEIGHT_HANDLER 0x1000	337	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
338	HEAVYWEIGHT_HANDLER 0x1400	338	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
339	HEAVYWEIGHT_HANDLER 0x1800	339	HEAVYWEIGHT_HANDLER 0x1800
340	HEAVYWEIGHT_HANDLER 0x1c00	340	HEAVYWEIGHT_HANDLER 0x1c00
341	HEAVYWEIGHT_HANDLER 0x2000	341	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
342	HEAVYWEIGHT_HANDLER 0x2400	342	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
343	HEAVYWEIGHT_HANDLER 0x2800	343	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
344	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction	344	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
345	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */	345	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
346	HEAVYWEIGHT_HANDLER 0x3400	346	HEAVYWEIGHT_HANDLER 0x3400
347	HEAVYWEIGHT_HANDLER 0x3800	347	HEAVYWEIGHT_HANDLER 0x3800
348	HEAVYWEIGHT_HANDLER 0x3c00	348	HEAVYWEIGHT_HANDLER 0x3c00
349	HEAVYWEIGHT_HANDLER 0x4000	349	HEAVYWEIGHT_HANDLER 0x4000
350	HEAVYWEIGHT_HANDLER 0x4400	350	HEAVYWEIGHT_HANDLER 0x4400
351	HEAVYWEIGHT_HANDLER 0x4800	351	HEAVYWEIGHT_HANDLER 0x4800
352	HEAVYWEIGHT_HANDLER 0x4c00	352	HEAVYWEIGHT_HANDLER 0x4c00
353		353
354	HEAVYWEIGHT_HANDLER 0x5000	354	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
355	HEAVYWEIGHT_HANDLER 0x5100	355	HEAVYWEIGHT_HANDLER 0x5100
356	HEAVYWEIGHT_HANDLER 0x5200	356	HEAVYWEIGHT_HANDLER 0x5200
357	HEAVYWEIGHT_HANDLER 0x5300	357	HEAVYWEIGHT_HANDLER 0x5300
358	HEAVYWEIGHT_HANDLER 0x5400 general_exception	358	HEAVYWEIGHT_HANDLER 0x5400 general_exception
359	HEAVYWEIGHT_HANDLER 0x5500	359	HEAVYWEIGHT_HANDLER 0x5500
360	HEAVYWEIGHT_HANDLER 0x5600	360	HEAVYWEIGHT_HANDLER 0x5600
361	HEAVYWEIGHT_HANDLER 0x5700	361	HEAVYWEIGHT_HANDLER 0x5700
362	HEAVYWEIGHT_HANDLER 0x5800	362	HEAVYWEIGHT_HANDLER 0x5800
363	HEAVYWEIGHT_HANDLER 0x5900	363	HEAVYWEIGHT_HANDLER 0x5900
364	HEAVYWEIGHT_HANDLER 0x5a00	364	HEAVYWEIGHT_HANDLER 0x5a00
365	HEAVYWEIGHT_HANDLER 0x5b00	365	HEAVYWEIGHT_HANDLER 0x5b00
366	HEAVYWEIGHT_HANDLER 0x5c00	366	HEAVYWEIGHT_HANDLER 0x5c00
367	HEAVYWEIGHT_HANDLER 0x5d00	367	HEAVYWEIGHT_HANDLER 0x5d00
368	HEAVYWEIGHT_HANDLER 0x5e00	368	HEAVYWEIGHT_HANDLER 0x5e00
369	HEAVYWEIGHT_HANDLER 0x5f00	369	HEAVYWEIGHT_HANDLER 0x5f00
370		370
371	HEAVYWEIGHT_HANDLER 0x6000	371	HEAVYWEIGHT_HANDLER 0x6000
372	HEAVYWEIGHT_HANDLER 0x6100	372	HEAVYWEIGHT_HANDLER 0x6100
373	HEAVYWEIGHT_HANDLER 0x6200	373	HEAVYWEIGHT_HANDLER 0x6200
374	HEAVYWEIGHT_HANDLER 0x6300	374	HEAVYWEIGHT_HANDLER 0x6300
375	HEAVYWEIGHT_HANDLER 0x6400	375	HEAVYWEIGHT_HANDLER 0x6400
376	HEAVYWEIGHT_HANDLER 0x6500	376	HEAVYWEIGHT_HANDLER 0x6500
377	HEAVYWEIGHT_HANDLER 0x6600	377	HEAVYWEIGHT_HANDLER 0x6600
378	HEAVYWEIGHT_HANDLER 0x6700	378	HEAVYWEIGHT_HANDLER 0x6700
379	HEAVYWEIGHT_HANDLER 0x6800	379	HEAVYWEIGHT_HANDLER 0x6800
380	HEAVYWEIGHT_HANDLER 0x6900	380	HEAVYWEIGHT_HANDLER 0x6900
381	HEAVYWEIGHT_HANDLER 0x6a00	381	HEAVYWEIGHT_HANDLER 0x6a00
382	HEAVYWEIGHT_HANDLER 0x6b00	382	HEAVYWEIGHT_HANDLER 0x6b00
383	HEAVYWEIGHT_HANDLER 0x6c00	383	HEAVYWEIGHT_HANDLER 0x6c00
384	HEAVYWEIGHT_HANDLER 0x6d00	384	HEAVYWEIGHT_HANDLER 0x6d00
385	HEAVYWEIGHT_HANDLER 0x6e00	385	HEAVYWEIGHT_HANDLER 0x6e00
386	HEAVYWEIGHT_HANDLER 0x6f00	386	HEAVYWEIGHT_HANDLER 0x6f00
387		387
388	HEAVYWEIGHT_HANDLER 0x7000	388	HEAVYWEIGHT_HANDLER 0x7000
389	HEAVYWEIGHT_HANDLER 0x7100	389	HEAVYWEIGHT_HANDLER 0x7100
390	HEAVYWEIGHT_HANDLER 0x7200	390	HEAVYWEIGHT_HANDLER 0x7200
391	HEAVYWEIGHT_HANDLER 0x7300	391	HEAVYWEIGHT_HANDLER 0x7300
392	HEAVYWEIGHT_HANDLER 0x7400	392	HEAVYWEIGHT_HANDLER 0x7400
393	HEAVYWEIGHT_HANDLER 0x7500	393	HEAVYWEIGHT_HANDLER 0x7500
394	HEAVYWEIGHT_HANDLER 0x7600	394	HEAVYWEIGHT_HANDLER 0x7600
395	HEAVYWEIGHT_HANDLER 0x7700	395	HEAVYWEIGHT_HANDLER 0x7700
396	HEAVYWEIGHT_HANDLER 0x7800	396	HEAVYWEIGHT_HANDLER 0x7800
397	HEAVYWEIGHT_HANDLER 0x7900	397	HEAVYWEIGHT_HANDLER 0x7900
398	HEAVYWEIGHT_HANDLER 0x7a00	398	HEAVYWEIGHT_HANDLER 0x7a00
399	HEAVYWEIGHT_HANDLER 0x7b00	399	HEAVYWEIGHT_HANDLER 0x7b00
400	HEAVYWEIGHT_HANDLER 0x7c00	400	HEAVYWEIGHT_HANDLER 0x7c00
401	HEAVYWEIGHT_HANDLER 0x7d00	401	HEAVYWEIGHT_HANDLER 0x7d00
402	HEAVYWEIGHT_HANDLER 0x7e00	402	HEAVYWEIGHT_HANDLER 0x7e00
403	HEAVYWEIGHT_HANDLER 0x7f00	403	HEAVYWEIGHT_HANDLER 0x7f00
404		404

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/src/ivt.S – Rev 534 → 899