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1 
#
 1 
#
2 
# Copyright (C) 2005 Jakub Vana
 2 
# Copyright (C) 2005 Jakub Vana
3 
# All rights reserved.
 3 
# All rights reserved.
4 
#
 4 
#
5 
# Redistribution and use in source and binary forms, with or without
 5 
# Redistribution and use in source and binary forms, with or without
6 
# modification, are permitted provided that the following conditions
 6 
# modification, are permitted provided that the following conditions
7 
# are met:
 7 
# are met:
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#
 8 
#
9 
# - Redistributions of source code must retain the above copyright
 9 
# - Redistributions of source code must retain the above copyright
10 
#   notice, this list of conditions and the following disclaimer.
 10 
#   notice, this list of conditions and the following disclaimer.
11 
# - Redistributions in binary form must reproduce the above copyright
 11 
# - Redistributions in binary form must reproduce the above copyright
12 
#   notice, this list of conditions and the following disclaimer in the
 12 
#   notice, this list of conditions and the following disclaimer in the
13 
#   documentation and/or other materials provided with the distribution.
 13 
#   documentation and/or other materials provided with the distribution.
14 
# - The name of the author may not be used to endorse or promote products
 14 
# - The name of the author may not be used to endorse or promote products
15 
#   derived from this software without specific prior written permission.
 15 
#   derived from this software without specific prior written permission.
16 
#
 16 
#
17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 
#
 27 
#
28 
 
 28 
 
29 
#include <arch/stack.h>
 29 
#include <arch/stack.h>
30 
 
 30 
 
31 
#define STACK_ITEMS		12
 31 
#define STACK_ITEMS		12
32 
#define STACK_FRAME_SIZE	((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
 32 
#define STACK_FRAME_SIZE	((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
33 
 
 33 
 
34 
#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
 34 
#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
35 
#error Memory stack must be 16-byte aligned.
 35 
#error Memory stack must be 16-byte aligned.
36 
#endif
 36 
#endif
37 
 
 37 
 
38 
/** Heavyweight interrupt handler
 38 
/** Heavyweight interrupt handler
39 
 *
 39 
 *
40 
 * This macro roughly follows steps from 1 to 19 described in
 40 
 * This macro roughly follows steps from 1 to 19 described in
41 
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 41 
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
42 
 *
 42 
 *
43 
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
 43 
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
44 
 * This goal is achieved by using procedure calls after RSE becomes operational.
 44 
 * This goal is achieved by using procedure calls after RSE becomes operational.
45 
 *
 45 
 *
46 
 * Some steps are skipped (enabling and disabling interrupts).
 46 
 * Some steps are skipped (enabling and disabling interrupts).
47 
 * Some steps are not fully supported yet (e.g. interruptions
 47 
 * Some steps are not fully supported yet (e.g. interruptions
48 
 * from userspace and floating-point context).
 48 
 * from userspace and floating-point context).
49 
 */
 49 
 */
50 
.macro HEAVYWEIGHT_HANDLER offs handler
 50 
.macro HEAVYWEIGHT_HANDLER offs handler
51 
    .org IVT + \offs
 51 
    .org IVT + \offs
52 
 
 52 
 
53 
    /* 1. copy interrupt registers into bank 0 */
 53 
    /* 1. copy interrupt registers into bank 0 */
54 
	mov r24 = cr.iip
 54 
	mov r24 = cr.iip
55 
	mov r25 = cr.ipsr
 55 
	mov r25 = cr.ipsr
56 
	mov r26 = cr.iipa
 56 
	mov r26 = cr.iipa
57 
	mov r27 = cr.isr
 57 
	mov r27 = cr.isr
58 
	mov r28 = cr.ifa
 58 
	mov r28 = cr.ifa
59
59
60 
    /* 2. preserve predicate register into bank 0 */
 60 
    /* 2. preserve predicate register into bank 0 */
61 
	mov r29 = pr ;;
 61 
	mov r29 = pr ;;
62
62
63 
    /* 3. switch to kernel memory stack */
 63 
    /* 3. switch to kernel memory stack */
64 
	/* TODO: support interruptions from userspace */
 64 
	/* TODO: support interruptions from userspace */
65 
	/* assume kernel stack */
 65 
	/* assume kernel stack */
66
66
67 
    /* 4. save registers in bank 0 into memory stack */
 67 
    /* 4. save registers in bank 0 into memory stack */
68 
	add r31 = -8, r12 ;;
 68 
	add r31 = -8, r12 ;;
69 
	add r12 = -STACK_FRAME_SIZE, r12 ;;
 69 
	add r12 = -STACK_FRAME_SIZE, r12 ;;
70
70
71 
	st8 [r31] = r29, -8 ;;	/* save predicate registers */
 71 
	st8 [r31] = r29, -8 ;;	/* save predicate registers */
72 
 
 72 
 
73 
	st8 [r31] = r24, -8 ;;	/* save cr.iip */
 73 
	st8 [r31] = r24, -8 ;;	/* save cr.iip */
74 
	st8 [r31] = r25, -8 ;;	/* save cr.ipsr */
 74 
	st8 [r31] = r25, -8 ;;	/* save cr.ipsr */
75 
	st8 [r31] = r26, -8 ;;	/* save cr.iipa */
 75 
	st8 [r31] = r26, -8 ;;	/* save cr.iipa */
76 
	st8 [r31] = r27, -8 ;;	/* save cr.isr */
 76 
	st8 [r31] = r27, -8 ;;	/* save cr.isr */
77 
	st8 [r31] = r28, -8 ;;	/* save cr.ifa */
77 
	st8 [r31] = r28, -8 ;;	/* save cr.ifa */
78 
 
 78 
 
79 
    /* 5. RSE switch from interrupted context */
 79 
    /* 5. RSE switch from interrupted context */
80 
    	.auto
 80 
    	.auto
81 
	mov r24 = ar.rsc
 81 
	mov r24 = ar.rsc
82 
	mov r25 = ar.pfs
 82 
	mov r25 = ar.pfs
83 
	cover
 83 
	cover
84 
	mov r26 = cr.ifs
 84 
	mov r26 = cr.ifs
85
85
86 
	st8 [r31] = r24, -8	/* save ar.rsc */
 86 
	st8 [r31] = r24, -8	/* save ar.rsc */
87 
	st8 [r31] = r25, -8	/* save ar.pfs */
 87 
	st8 [r31] = r25, -8	/* save ar.pfs */
88 
	st8 [r31] = r26, -8	/* save ar.ifs */
 88 
	st8 [r31] = r26, -8	/* save ar.ifs */
89
89
90 
	and r30 = ~3, r24
 90 
	and r30 = ~3, r24
91 
	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
 91 
	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
92
92
93 
	mov r27 = ar.rnat
 93 
	mov r27 = ar.rnat
94 
	mov r28 = ar.bspstore
 94 
	mov r28 = ar.bspstore
95
95
96 
	/* assume kernel backing store */
 96 
	/* assume kernel backing store */
97 
	mov ar.bspstore = r28
 97 
	mov ar.bspstore = r28
98
98
99 
	mov r29 = ar.bsp
 99 
	mov r29 = ar.bsp
100
100
101 
	st8 [r31] = r27, -8	/* save ar.rnat */
 101 
	st8 [r31] = r27, -8	/* save ar.rnat */
102 
	st8 [r31] = r28, -8	/* save ar.bspstore */
 102 
	st8 [r31] = r28, -8	/* save ar.bspstore */
103 
	st8 [r31] = r29		/* save ar.bsp */
 103 
	st8 [r31] = r29		/* save ar.bsp */
104
104
105 
	mov ar.rsc = r24	/* restore RSE's setting */
 105 
	mov ar.rsc = r24	/* restore RSE's setting */
106 
	.explicit
 106 
	.explicit
107
107
108 
    /* the rest of the save-handler can be kept outside IVT */
 108 
    /* the rest of the save-handler can be kept outside IVT */
109 
 
 109 
 
110 
	movl r24 = \handler
 110 
	movl r24 = \handler
111 
	mov r25 = b0
 111 
	mov r25 = b0
112 
	br.call.sptk.many rp = heavyweight_handler_inner
 112 
	br.call.sptk.many rp = heavyweight_handler_inner
113 
0:	mov b0 = r25
113 
0:	mov b0 = r25
114 
 
 114 
 
115 
	br heavyweight_handler_finalize
 115 
	br heavyweight_handler_finalize
116 
.endm
 116 
.endm
117 
 
 117 
 
118 
.global heavyweight_handler_inner
 118 
.global heavyweight_handler_inner
119 
heavyweight_handler_inner:
 119 
heavyweight_handler_inner:
120 
	/*
 120 
	/*
121 
	 * From this point, the rest of the interrupted context
 121 
	 * From this point, the rest of the interrupted context
122 
	 * will be preserved in stacked registers and backing store.
 122 
	 * will be preserved in stacked registers and backing store.
123 
	 */
 123 
	 */
124 
	alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
 124 
	alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
125
125
126 
	/* copy handler address (r24 from bank 0 will be invisible soon) */
 126 
	/* copy handler address (r24 from bank 0 will be invisible soon) */
127 
	mov loc1 = r24
 127 
	mov loc1 = r24
128 
 
 128 
 
129 
    /* 6. switch to bank 1 and reenable PSR.ic */
 129 
    /* 6. switch to bank 1 and reenable PSR.ic */
130 
	ssm 0x2000
 130 
	ssm 0x2000
131 
	bsw.1 ;;
 131 
	bsw.1 ;;
132 
	srlz.d
 132 
	srlz.d
133
133
134 
    /* 7. preserve branch and application registers */
 134 
    /* 7. preserve branch and application registers */
135 
    	mov loc2 = ar.unat
 135 
    	mov loc2 = ar.unat
136 
	mov loc3 = ar.lc
 136 
	mov loc3 = ar.lc
137 
	mov loc4 = ar.ec
 137 
	mov loc4 = ar.ec
138 
	mov loc5 = ar.ccv
 138 
	mov loc5 = ar.ccv
139 
	mov loc6 = ar.csd
 139 
	mov loc6 = ar.csd
140 
	mov loc7 = ar.ssd
 140 
	mov loc7 = ar.ssd
141
141
142 
	mov loc8 = b0
 142 
	mov loc8 = b0
143 
	mov loc9 = b1
 143 
	mov loc9 = b1
144 
	mov loc10 = b2
 144 
	mov loc10 = b2
145 
	mov loc11 = b3
 145 
	mov loc11 = b3
146 
	mov loc12 = b4
 146 
	mov loc12 = b4
147 
	mov loc13 = b5
 147 
	mov loc13 = b5
148 
	mov loc14 = b6
 148 
	mov loc14 = b6
149 
	mov loc15 = b7
 149 
	mov loc15 = b7
150
150
151 
    /* 8. preserve general and floating-point registers */
 151 
    /* 8. preserve general and floating-point registers */
152 
	/* TODO: save floating-point context */
 152 
	/* TODO: save floating-point context */
153 
	mov loc16 = r1
 153 
	mov loc16 = r1
154 
	mov loc17 = r2
 154 
	mov loc17 = r2
155 
	mov loc18 = r3
 155 
	mov loc18 = r3
156 
	mov loc19 = r4
 156 
	mov loc19 = r4
157 
	mov loc20 = r5
 157 
	mov loc20 = r5
158 
	mov loc21 = r6
 158 
	mov loc21 = r6
159 
	mov loc22 = r7
 159 
	mov loc22 = r7
160 
	mov loc23 = r8
 160 
	mov loc23 = r8
161 
	mov loc24 = r9
 161 
	mov loc24 = r9
162 
	mov loc25 = r10
 162 
	mov loc25 = r10
163 
	mov loc26 = r11
 163 
	mov loc26 = r11
164 
	/* skip r12 (stack pointer) */
 164 
	/* skip r12 (stack pointer) */
165 
	mov loc27 = r13
 165 
	mov loc27 = r13
166 
	mov loc28 = r14
 166 
	mov loc28 = r14
167 
	mov loc29 = r15
 167 
	mov loc29 = r15
168 
	mov loc30 = r16
 168 
	mov loc30 = r16
169 
	mov loc31 = r17
 169 
	mov loc31 = r17
170 
	mov loc32 = r18
 170 
	mov loc32 = r18
171 
	mov loc33 = r19
 171 
	mov loc33 = r19
172 
	mov loc34 = r20
 172 
	mov loc34 = r20
173 
	mov loc35 = r21
 173 
	mov loc35 = r21
174 
	mov loc36 = r22
 174 
	mov loc36 = r22
175 
	mov loc37 = r23
 175 
	mov loc37 = r23
176 
	mov loc38 = r24
 176 
	mov loc38 = r24
177 
	mov loc39 = r25
 177 
	mov loc39 = r25
178 
	mov loc40 = r26
 178 
	mov loc40 = r26
179 
	mov loc41 = r27
 179 
	mov loc41 = r27
180 
	mov loc42 = r28
 180 
	mov loc42 = r28
181 
	mov loc43 = r29
 181 
	mov loc43 = r29
182 
	mov loc44 = r30
 182 
	mov loc44 = r30
183 
	mov loc45 = r31
 183 
	mov loc45 = r31
184
184
185 
    /* 9. skipped (will not enable interrupts) */
 185 
    /* 9. skipped (will not enable interrupts) */
186 
 
 186 
 
187 
    /* 10. call handler */
 187 
    /* 10. call handler */
188 
    	mov b1 = loc1
 188 
    	mov b1 = loc1
189 
	br.call.sptk.many b0 = b1
 189 
	br.call.sptk.many b0 = b1
190 
 
 190 
 
191 
    /* 11. return from handler */
 191 
    /* 11. return from handler */
192 
0:
 192 
0:
193
193
194 
    /* 12. skipped (will not disable interrupts) */
 194 
    /* 12. skipped (will not disable interrupts) */
195 
 
 195 
 
196 
    /* 13. restore general and floating-point registers */
 196 
    /* 13. restore general and floating-point registers */
197 
	/* TODO: restore floating-point context */
 197 
	/* TODO: restore floating-point context */
198 
	mov r1 = loc16
 198 
	mov r1 = loc16
199 
	mov r2 = loc17
 199 
	mov r2 = loc17
200 
	mov r3 = loc18
 200 
	mov r3 = loc18
201 
	mov r4 = loc19
 201 
	mov r4 = loc19
202 
	mov r5 = loc20
 202 
	mov r5 = loc20
203 
	mov r6 = loc21
 203 
	mov r6 = loc21
204 
	mov r7 = loc22
 204 
	mov r7 = loc22
205 
	mov r8 = loc23
 205 
	mov r8 = loc23
206 
	mov r9 = loc24
 206 
	mov r9 = loc24
207 
	mov r10 = loc25
 207 
	mov r10 = loc25
208 
	mov r11 = loc26
 208 
	mov r11 = loc26
209 
	/* skip r12 (stack pointer) */
 209 
	/* skip r12 (stack pointer) */
210 
	mov r13 = loc27
 210 
	mov r13 = loc27
211 
	mov r14 = loc28
 211 
	mov r14 = loc28
212 
	mov r15 = loc29
 212 
	mov r15 = loc29
213 
	mov r16 = loc30
 213 
	mov r16 = loc30
214 
	mov r17 = loc31
 214 
	mov r17 = loc31
215 
	mov r18 = loc32
 215 
	mov r18 = loc32
216 
	mov r19 = loc33
 216 
	mov r19 = loc33
217 
	mov r20 = loc34
 217 
	mov r20 = loc34
218 
	mov r21 = loc35
 218 
	mov r21 = loc35
219 
	mov r22 = loc36
 219 
	mov r22 = loc36
220 
	mov r23 = loc37
 220 
	mov r23 = loc37
221 
	mov r24 = loc38
 221 
	mov r24 = loc38
222 
	mov r25 = loc39
 222 
	mov r25 = loc39
223 
	mov r26 = loc40
 223 
	mov r26 = loc40
224 
	mov r27 = loc41
 224 
	mov r27 = loc41
225 
	mov r28 = loc42
 225 
	mov r28 = loc42
226 
	mov r29 = loc43
 226 
	mov r29 = loc43
227 
	mov r30 = loc44
 227 
	mov r30 = loc44
228 
	mov r31 = loc45
 228 
	mov r31 = loc45
229
229
230 
    /* 14. restore branch and application registers */
 230 
    /* 14. restore branch and application registers */
231 
    	mov ar.unat = loc2
 231 
    	mov ar.unat = loc2
232 
	mov ar.lc = loc3
 232 
	mov ar.lc = loc3
233 
	mov ar.ec = loc4
 233 
	mov ar.ec = loc4
234 
	mov ar.ccv = loc5
 234 
	mov ar.ccv = loc5
235 
	mov ar.csd = loc6
 235 
	mov ar.csd = loc6
236 
	mov ar.ssd = loc7
 236 
	mov ar.ssd = loc7
237
237
238 
	mov b0 = loc8
 238 
	mov b0 = loc8
239 
	mov b1 = loc9
 239 
	mov b1 = loc9
240 
	mov b2 = loc10
 240 
	mov b2 = loc10
241 
	mov b3 = loc11
 241 
	mov b3 = loc11
242 
	mov b4 = loc12
 242 
	mov b4 = loc12
243 
	mov b5 = loc13
 243 
	mov b5 = loc13
244 
	mov b6 = loc14
 244 
	mov b6 = loc14
245 
	mov b7 = loc15
 245 
	mov b7 = loc15
246
246
247 
    /* 15. disable PSR.ic and switch to bank 0 */
 247 
    /* 15. disable PSR.ic and switch to bank 0 */
248 
	rsm 0x2000
 248 
	rsm 0x2000
249 
	bsw.0 ;;
 249 
	bsw.0 ;;
250 
	srlz.d
 250 
	srlz.d
251 
 
 251 
 
252 
	mov ar.pfs = loc0
 252 
	mov ar.pfs = loc0
253 
	br.ret.sptk.many rp
 253 
	br.ret.sptk.many rp
254 
 
 254 
 
255 
.global heavyweight_handler_finalize
 255 
.global heavyweight_handler_finalize
256 
heavyweight_handler_finalize:
 256 
heavyweight_handler_finalize:
257 
    /* 16. RSE switch to interrupted context */
 257 
    /* 16. RSE switch to interrupted context */
258 
 
 258 
 
259 
/********************************************************************************************/
 259 
/********************************************************************************************/
260 
 
 260 
 
261 
 
 261 
 
262 
 
 262 
 
263 
	.auto
 263 
	.auto
264 
	cover			/*Allocate zerro size frame (Step 1(from Intel Docs))*/
 264 
	cover			/*Allocate zerro size frame (Step 1(from Intel Docs))*/
265 
 
 265 
 
266 
	add r31 = STACK_SCRATCH_AREA_SIZE, r12;;
 266 
	add r31 = STACK_SCRATCH_AREA_SIZE, r12
267 
 
 267 
 
268 
	mov r28 = ar.bspstore   /*Calculate loadrs (step 2)*/
 268 
	mov r28 = ar.bspstore   /*Calculate loadrs (step 2)*/
269 
	ld8 r29 = [r31], +8
269 
	ld8 r29 = [r31], +8
270 
	sub r27 = r29 , r28
 270 
	sub r27 = r29 , r28
271 
	shl r27 = r27, 16
 271 
	shl r27 = r27, 16
272 
 
 272 
 
273 
	mov r24 = ar.rsc
 273 
	mov r24 = ar.rsc
274 
	and r30 = ~3, r24
 274 
	and r30 = ~3, r24
275 
	or  r24 = r30 , r27
275 
	or  r24 = r30 , r27
276 
	mov ar.rsc = r24	/* place RSE in enforced lazy mode */
 276 
	mov ar.rsc = r24	/* place RSE in enforced lazy mode */
277 
 
 277 
 
278 
 
 278 
 
279 
 
 279 
 
280 
	loadrs 			/*(Step 3)*/
 280 
	loadrs 			/*(Step 3)*/
281 
 
 281 
 
282 
 
 282 
 
283 
				/*Read saved registers*/
 283 
				/*Read saved registers*/
284 
	ld8 r28 = [r31], +8     /*ar.bspstore*/
 284 
	ld8 r28 = [r31], +8     /*ar.bspstore*/
285 
	ld8 r27 = [r31], +8 	/*ar.rnat*/
 285 
	ld8 r27 = [r31], +8 	/*ar.rnat*/
286 
	ld8 r26 = [r31], +8 	/*cr.ifs*/
 286 
	ld8 r26 = [r31], +8 	/*cr.ifs*/
287 
	ld8 r25 = [r31], +8 	/*ar.pfs*/
 287 
	ld8 r25 = [r31], +8 	/*ar.pfs*/
288 
	ld8 r24 = [r31], +8 	/*ar.rsc*/
 288 
	ld8 r24 = [r31], +8 	/*ar.rsc*/
289 
 
 289 
 
290 
 
 290 
 
291 
	mov ar.bspstore = r28	/*(Step 4)*/
 291 
	mov ar.bspstore = r28	/*(Step 4)*/
292 
	mov ar.rnat = r27	/*(Step 5)*/
 292 
	mov ar.rnat = r27	/*(Step 5)*/
293 
 
 293 
 
294 
	mov ar.pfs = r25	/*(Step 6)*/
 294 
	mov ar.pfs = r25	/*(Step 6)*/
295 
	mov cr.ifs = r26
295 
	mov cr.ifs = r26
296 
 
 296 
 
297 
	mov ar.rsc = r24	/*(Step 7)*/
 297 
	mov ar.rsc = r24	/*(Step 7)*/
298 
 
 298 
 
299 
 
 299 
 
300 
	.explicit
300 
	.explicit
301 
 
 301 
 
302 
 
 302 
 
303 
/********************************************************************************************/
 303 
/********************************************************************************************/
304 
 
 304 
 
305 
 
 305 
 
306 
 
 306 
 
307 
    /* 17. restore interruption state from memory stack */
 307 
    /* 17. restore interruption state from memory stack */
308 
 
 308 
 
309 
	ld8 r28 = [r31] , +8 ;;	/* load cr.ifa */
309 
	ld8 r28 = [r31] , +8 ;;	/* load cr.ifa */
310 
	ld8 r27 = [r31] , +8 ;;	/* load cr.isr */
 310 
	ld8 r27 = [r31] , +8 ;;	/* load cr.isr */
311 
	ld8 r26 = [r31] , +8 ;;	/* load cr.iipa */
 311 
	ld8 r26 = [r31] , +8 ;;	/* load cr.iipa */
312 
	ld8 r25 = [r31] , +8 ;;	/* load cr.ipsr */
 312 
	ld8 r25 = [r31] , +8 ;;	/* load cr.ipsr */
313 
	ld8 r24 = [r31] , +8 ;;	/* load cr.iip */
 313 
	ld8 r24 = [r31] , +8 ;;	/* load cr.iip */
314 
 
 314 
 
315 
 
 315 
 
316 
	mov cr.iip = r24
 316 
	mov cr.iip = r24
317 
	mov cr.ipsr = r25
 317 
	mov cr.ipsr = r25
318 
	mov cr.iipa = r26
 318 
	mov cr.iipa = r26
319 
	mov cr.isr = r27
 319 
	mov cr.isr = r27
320 
	mov cr.ifa = r28
 320 
	mov cr.ifa = r28
321 
 
 321 
 
322 
 
 322 
 
323
323
324 
    /* 18. restore predicate registers from memory stack */
 324 
    /* 18. restore predicate registers from memory stack */
325 
 
 325 
 
326 
 
 326 
 
327 
	ld8 r29 = [r31] , -8 ;;	/* load predicate registers */
 327 
	ld8 r29 = [r31] , -8 ;;	/* load predicate registers */
328 
	mov pr =r29 ;;
 328 
	mov pr =r29 ;;
329
329
330 
	add r12 = STACK_FRAME_SIZE,r12;;
 330 
	add r12 = STACK_FRAME_SIZE,r12;;
331
331
332 
    /* 19. return from interruption */
 332 
    /* 19. return from interruption */
333 
	rfi;;
 333 
	rfi;;
334 
 
 334 
 
335 
 
 335 
 
336 
dump_gregs:
 336 
dump_gregs:
337 
mov r16 = REG_DUMP;;
 337 
mov r16 = REG_DUMP;;
338 
st8 [r16] = r0;;
 338 
st8 [r16] = r0;;
339 
add r16 = 8,r16 ;;
 339 
add r16 = 8,r16 ;;
340 
st8 [r16] = r1;;
 340 
st8 [r16] = r1;;
341 
add r16 = 8,r16 ;;
 341 
add r16 = 8,r16 ;;
342 
st8 [r16] = r2;;
 342 
st8 [r16] = r2;;
343 
add r16 = 8,r16 ;;
 343 
add r16 = 8,r16 ;;
344 
st8 [r16] = r3;;
 344 
st8 [r16] = r3;;
345 
add r16 = 8,r16 ;;
 345 
add r16 = 8,r16 ;;
346 
st8 [r16] = r4;;
 346 
st8 [r16] = r4;;
347 
add r16 = 8,r16 ;;
 347 
add r16 = 8,r16 ;;
348 
st8 [r16] = r5;;
 348 
st8 [r16] = r5;;
349 
add r16 = 8,r16 ;;
 349 
add r16 = 8,r16 ;;
350 
st8 [r16] = r6;;
 350 
st8 [r16] = r6;;
351 
add r16 = 8,r16 ;;
 351 
add r16 = 8,r16 ;;
352 
st8 [r16] = r7;;
 352 
st8 [r16] = r7;;
353 
add r16 = 8,r16 ;;
 353 
add r16 = 8,r16 ;;
354 
st8 [r16] = r8;;
 354 
st8 [r16] = r8;;
355 
add r16 = 8,r16 ;;
 355 
add r16 = 8,r16 ;;
356 
st8 [r16] = r9;;
 356 
st8 [r16] = r9;;
357 
add r16 = 8,r16 ;;
 357 
add r16 = 8,r16 ;;
358 
st8 [r16] = r10;;
 358 
st8 [r16] = r10;;
359 
add r16 = 8,r16 ;;
 359 
add r16 = 8,r16 ;;
360 
st8 [r16] = r11;;
 360 
st8 [r16] = r11;;
361 
add r16 = 8,r16 ;;
 361 
add r16 = 8,r16 ;;
362 
st8 [r16] = r12;;
 362 
st8 [r16] = r12;;
363 
add r16 = 8,r16 ;;
 363 
add r16 = 8,r16 ;;
364 
st8 [r16] = r13;;
 364 
st8 [r16] = r13;;
365 
add r16 = 8,r16 ;;
 365 
add r16 = 8,r16 ;;
366 
st8 [r16] = r14;;
 366 
st8 [r16] = r14;;
367 
add r16 = 8,r16 ;;
 367 
add r16 = 8,r16 ;;
368 
st8 [r16] = r15;;
 368 
st8 [r16] = r15;;
369 
add r16 = 8,r16 ;;
 369 
add r16 = 8,r16 ;;
370 
 
 370 
 
371 
bsw.1;;
 371 
bsw.1;;
372 
mov r15 = r16;;
 372 
mov r15 = r16;;
373 
bsw.0;;
 373 
bsw.0;;
374 
st8 [r16] = r15;;
 374 
st8 [r16] = r15;;
375 
add r16 = 8,r16 ;;
 375 
add r16 = 8,r16 ;;
376 
bsw.1;;
 376 
bsw.1;;
377 
mov r15 = r17;;
 377 
mov r15 = r17;;
378 
bsw.0;;
 378 
bsw.0;;
379 
st8 [r16] = r15;;
 379 
st8 [r16] = r15;;
380 
add r16 = 8,r16 ;;
 380 
add r16 = 8,r16 ;;
381 
bsw.1;;
 381 
bsw.1;;
382 
mov r15 = r18;;
 382 
mov r15 = r18;;
383 
bsw.0;;
 383 
bsw.0;;
384 
st8 [r16] = r15;;
 384 
st8 [r16] = r15;;
385 
add r16 = 8,r16 ;;
 385 
add r16 = 8,r16 ;;
386 
bsw.1;;
 386 
bsw.1;;
387 
mov r15 = r19;;
 387 
mov r15 = r19;;
388 
bsw.0;;
 388 
bsw.0;;
389 
st8 [r16] = r15;;
 389 
st8 [r16] = r15;;
390 
add r16 = 8,r16 ;;
 390 
add r16 = 8,r16 ;;
391 
bsw.1;;
 391 
bsw.1;;
392 
mov r15 = r20;;
 392 
mov r15 = r20;;
393 
bsw.0;;
 393 
bsw.0;;
394 
st8 [r16] = r15;;
 394 
st8 [r16] = r15;;
395 
add r16 = 8,r16 ;;
 395 
add r16 = 8,r16 ;;
396 
bsw.1;;
 396 
bsw.1;;
397 
mov r15 = r21;;
 397 
mov r15 = r21;;
398 
bsw.0;;
 398 
bsw.0;;
399 
st8 [r16] = r15;;
 399 
st8 [r16] = r15;;
400 
add r16 = 8,r16 ;;
 400 
add r16 = 8,r16 ;;
401 
bsw.1;;
 401 
bsw.1;;
402 
mov r15 = r22;;
 402 
mov r15 = r22;;
403 
bsw.0;;
 403 
bsw.0;;
404 
st8 [r16] = r15;;
 404 
st8 [r16] = r15;;
405 
add r16 = 8,r16 ;;
 405 
add r16 = 8,r16 ;;
406 
bsw.1;;
 406 
bsw.1;;
407 
mov r15 = r23;;
 407 
mov r15 = r23;;
408 
bsw.0;;
 408 
bsw.0;;
409 
st8 [r16] = r15;;
 409 
st8 [r16] = r15;;
410 
add r16 = 8,r16 ;;
 410 
add r16 = 8,r16 ;;
411 
bsw.1;;
 411 
bsw.1;;
412 
mov r15 = r24;;
 412 
mov r15 = r24;;
413 
bsw.0;;
 413 
bsw.0;;
414 
st8 [r16] = r15;;
 414 
st8 [r16] = r15;;
415 
add r16 = 8,r16 ;;
 415 
add r16 = 8,r16 ;;
416 
bsw.1;;
 416 
bsw.1;;
417 
mov r15 = r25;;
 417 
mov r15 = r25;;
418 
bsw.0;;
 418 
bsw.0;;
419 
st8 [r16] = r15;;
 419 
st8 [r16] = r15;;
420 
add r16 = 8,r16 ;;
 420 
add r16 = 8,r16 ;;
421 
bsw.1;;
 421 
bsw.1;;
422 
mov r15 = r26;;
 422 
mov r15 = r26;;
423 
bsw.0;;
 423 
bsw.0;;
424 
st8 [r16] = r15;;
 424 
st8 [r16] = r15;;
425 
add r16 = 8,r16 ;;
 425 
add r16 = 8,r16 ;;
426 
bsw.1;;
 426 
bsw.1;;
427 
mov r15 = r27;;
 427 
mov r15 = r27;;
428 
bsw.0;;
 428 
bsw.0;;
429 
st8 [r16] = r15;;
 429 
st8 [r16] = r15;;
430 
add r16 = 8,r16 ;;
 430 
add r16 = 8,r16 ;;
431 
bsw.1;;
 431 
bsw.1;;
432 
mov r15 = r28;;
 432 
mov r15 = r28;;
433 
bsw.0;;
 433 
bsw.0;;
434 
st8 [r16] = r15;;
 434 
st8 [r16] = r15;;
435 
add r16 = 8,r16 ;;
 435 
add r16 = 8,r16 ;;
436 
bsw.1;;
 436 
bsw.1;;
437 
mov r15 = r29;;
 437 
mov r15 = r29;;
438 
bsw.0;;
 438 
bsw.0;;
439 
st8 [r16] = r15;;
 439 
st8 [r16] = r15;;
440 
add r16 = 8,r16 ;;
 440 
add r16 = 8,r16 ;;
441 
bsw.1;;
 441 
bsw.1;;
442 
mov r15 = r30;;
 442 
mov r15 = r30;;
443 
bsw.0;;
 443 
bsw.0;;
444 
st8 [r16] = r15;;
 444 
st8 [r16] = r15;;
445 
add r16 = 8,r16 ;;
 445 
add r16 = 8,r16 ;;
446 
bsw.1;;
 446 
bsw.1;;
447 
mov r15 = r31;;
 447 
mov r15 = r31;;
448 
bsw.0;;
 448 
bsw.0;;
449 
st8 [r16] = r15;;
 449 
st8 [r16] = r15;;
450 
add r16 = 8,r16 ;;
 450 
add r16 = 8,r16 ;;
451 
 
 451 
 
452 
 
 452 
 
453 
st8 [r16] = r32;;
 453 
st8 [r16] = r32;;
454 
add r16 = 8,r16 ;;
 454 
add r16 = 8,r16 ;;
455 
st8 [r16] = r33;;
 455 
st8 [r16] = r33;;
456 
add r16 = 8,r16 ;;
 456 
add r16 = 8,r16 ;;
457 
st8 [r16] = r34;;
 457 
st8 [r16] = r34;;
458 
add r16 = 8,r16 ;;
 458 
add r16 = 8,r16 ;;
459 
st8 [r16] = r35;;
 459 
st8 [r16] = r35;;
460 
add r16 = 8,r16 ;;
 460 
add r16 = 8,r16 ;;
461 
st8 [r16] = r36;;
 461 
st8 [r16] = r36;;
462 
add r16 = 8,r16 ;;
 462 
add r16 = 8,r16 ;;
463 
st8 [r16] = r37;;
 463 
st8 [r16] = r37;;
464 
add r16 = 8,r16 ;;
 464 
add r16 = 8,r16 ;;
465 
st8 [r16] = r38;;
 465 
st8 [r16] = r38;;
466 
add r16 = 8,r16 ;;
 466 
add r16 = 8,r16 ;;
467 
st8 [r16] = r39;;
 467 
st8 [r16] = r39;;
468 
add r16 = 8,r16 ;;
 468 
add r16 = 8,r16 ;;
469 
st8 [r16] = r40;;
 469 
st8 [r16] = r40;;
470 
add r16 = 8,r16 ;;
 470 
add r16 = 8,r16 ;;
471 
st8 [r16] = r41;;
 471 
st8 [r16] = r41;;
472 
add r16 = 8,r16 ;;
 472 
add r16 = 8,r16 ;;
473 
st8 [r16] = r42;;
 473 
st8 [r16] = r42;;
474 
add r16 = 8,r16 ;;
 474 
add r16 = 8,r16 ;;
475 
st8 [r16] = r43;;
 475 
st8 [r16] = r43;;
476 
add r16 = 8,r16 ;;
 476 
add r16 = 8,r16 ;;
477 
st8 [r16] = r44;;
 477 
st8 [r16] = r44;;
478 
add r16 = 8,r16 ;;
 478 
add r16 = 8,r16 ;;
479 
st8 [r16] = r45;;
 479 
st8 [r16] = r45;;
480 
add r16 = 8,r16 ;;
 480 
add r16 = 8,r16 ;;
481 
st8 [r16] = r46;;
 481 
st8 [r16] = r46;;
482 
add r16 = 8,r16 ;;
 482 
add r16 = 8,r16 ;;
483 
st8 [r16] = r47;;
 483 
st8 [r16] = r47;;
484 
add r16 = 8,r16 ;;
 484 
add r16 = 8,r16 ;;
485 
st8 [r16] = r48;;
 485 
st8 [r16] = r48;;
486 
add r16 = 8,r16 ;;
 486 
add r16 = 8,r16 ;;
487 
st8 [r16] = r49;;
 487 
st8 [r16] = r49;;
488 
add r16 = 8,r16 ;;
 488 
add r16 = 8,r16 ;;
489 
st8 [r16] = r50;;
 489 
st8 [r16] = r50;;
490 
add r16 = 8,r16 ;;
 490 
add r16 = 8,r16 ;;
491 
st8 [r16] = r51;;
 491 
st8 [r16] = r51;;
492 
add r16 = 8,r16 ;;
 492 
add r16 = 8,r16 ;;
493 
st8 [r16] = r52;;
 493 
st8 [r16] = r52;;
494 
add r16 = 8,r16 ;;
 494 
add r16 = 8,r16 ;;
495 
st8 [r16] = r53;;
 495 
st8 [r16] = r53;;
496 
add r16 = 8,r16 ;;
 496 
add r16 = 8,r16 ;;
497 
st8 [r16] = r54;;
 497 
st8 [r16] = r54;;
498 
add r16 = 8,r16 ;;
 498 
add r16 = 8,r16 ;;
499 
st8 [r16] = r55;;
 499 
st8 [r16] = r55;;
500 
add r16 = 8,r16 ;;
 500 
add r16 = 8,r16 ;;
501 
st8 [r16] = r56;;
 501 
st8 [r16] = r56;;
502 
add r16 = 8,r16 ;;
 502 
add r16 = 8,r16 ;;
503 
st8 [r16] = r57;;
 503 
st8 [r16] = r57;;
504 
add r16 = 8,r16 ;;
 504 
add r16 = 8,r16 ;;
505 
st8 [r16] = r58;;
 505 
st8 [r16] = r58;;
506 
add r16 = 8,r16 ;;
 506 
add r16 = 8,r16 ;;
507 
st8 [r16] = r59;;
 507 
st8 [r16] = r59;;
508 
add r16 = 8,r16 ;;
 508 
add r16 = 8,r16 ;;
509 
st8 [r16] = r60;;
 509 
st8 [r16] = r60;;
510 
add r16 = 8,r16 ;;
 510 
add r16 = 8,r16 ;;
511 
st8 [r16] = r61;;
 511 
st8 [r16] = r61;;
512 
add r16 = 8,r16 ;;
 512 
add r16 = 8,r16 ;;
513 
st8 [r16] = r62;;
 513 
st8 [r16] = r62;;
514 
add r16 = 8,r16 ;;
 514 
add r16 = 8,r16 ;;
515 
st8 [r16] = r63;;
 515 
st8 [r16] = r63;;
516 
add r16 = 8,r16 ;;
 516 
add r16 = 8,r16 ;;
517 
 
 517 
 
518 
 
 518 
 
519 
 
 519 
 
520 
st8 [r16] = r64;;
 520 
st8 [r16] = r64;;
521 
add r16 = 8,r16 ;;
 521 
add r16 = 8,r16 ;;
522 
st8 [r16] = r65;;
 522 
st8 [r16] = r65;;
523 
add r16 = 8,r16 ;;
 523 
add r16 = 8,r16 ;;
524 
st8 [r16] = r66;;
 524 
st8 [r16] = r66;;
525 
add r16 = 8,r16 ;;
 525 
add r16 = 8,r16 ;;
526 
st8 [r16] = r67;;
 526 
st8 [r16] = r67;;
527 
add r16 = 8,r16 ;;
 527 
add r16 = 8,r16 ;;
528 
st8 [r16] = r68;;
 528 
st8 [r16] = r68;;
529 
add r16 = 8,r16 ;;
 529 
add r16 = 8,r16 ;;
530 
st8 [r16] = r69;;
 530 
st8 [r16] = r69;;
531 
add r16 = 8,r16 ;;
 531 
add r16 = 8,r16 ;;
532 
st8 [r16] = r70;;
 532 
st8 [r16] = r70;;
533 
add r16 = 8,r16 ;;
 533 
add r16 = 8,r16 ;;
534 
st8 [r16] = r71;;
 534 
st8 [r16] = r71;;
535 
add r16 = 8,r16 ;;
 535 
add r16 = 8,r16 ;;
536 
st8 [r16] = r72;;
 536 
st8 [r16] = r72;;
537 
add r16 = 8,r16 ;;
 537 
add r16 = 8,r16 ;;
538 
st8 [r16] = r73;;
 538 
st8 [r16] = r73;;
539 
add r16 = 8,r16 ;;
 539 
add r16 = 8,r16 ;;
540 
st8 [r16] = r74;;
 540 
st8 [r16] = r74;;
541 
add r16 = 8,r16 ;;
 541 
add r16 = 8,r16 ;;
542 
st8 [r16] = r75;;
 542 
st8 [r16] = r75;;
543 
add r16 = 8,r16 ;;
 543 
add r16 = 8,r16 ;;
544 
st8 [r16] = r76;;
 544 
st8 [r16] = r76;;
545 
add r16 = 8,r16 ;;
 545 
add r16 = 8,r16 ;;
546 
st8 [r16] = r77;;
 546 
st8 [r16] = r77;;
547 
add r16 = 8,r16 ;;
 547 
add r16 = 8,r16 ;;
548 
st8 [r16] = r78;;
 548 
st8 [r16] = r78;;
549 
add r16 = 8,r16 ;;
 549 
add r16 = 8,r16 ;;
550 
st8 [r16] = r79;;
 550 
st8 [r16] = r79;;
551 
add r16 = 8,r16 ;;
 551 
add r16 = 8,r16 ;;
552 
st8 [r16] = r80;;
 552 
st8 [r16] = r80;;
553 
add r16 = 8,r16 ;;
 553 
add r16 = 8,r16 ;;
554 
st8 [r16] = r81;;
 554 
st8 [r16] = r81;;
555 
add r16 = 8,r16 ;;
 555 
add r16 = 8,r16 ;;
556 
st8 [r16] = r82;;
 556 
st8 [r16] = r82;;
557 
add r16 = 8,r16 ;;
 557 
add r16 = 8,r16 ;;
558 
st8 [r16] = r83;;
 558 
st8 [r16] = r83;;
559 
add r16 = 8,r16 ;;
 559 
add r16 = 8,r16 ;;
560 
st8 [r16] = r84;;
 560 
st8 [r16] = r84;;
561 
add r16 = 8,r16 ;;
 561 
add r16 = 8,r16 ;;
562 
st8 [r16] = r85;;
 562 
st8 [r16] = r85;;
563 
add r16 = 8,r16 ;;
 563 
add r16 = 8,r16 ;;
564 
st8 [r16] = r86;;
 564 
st8 [r16] = r86;;
565 
add r16 = 8,r16 ;;
 565 
add r16 = 8,r16 ;;
566 
st8 [r16] = r87;;
 566 
st8 [r16] = r87;;
567 
add r16 = 8,r16 ;;
 567 
add r16 = 8,r16 ;;
568 
st8 [r16] = r88;;
 568 
st8 [r16] = r88;;
569 
add r16 = 8,r16 ;;
 569 
add r16 = 8,r16 ;;
570 
st8 [r16] = r89;;
 570 
st8 [r16] = r89;;
571 
add r16 = 8,r16 ;;
 571 
add r16 = 8,r16 ;;
572 
st8 [r16] = r90;;
 572 
st8 [r16] = r90;;
573 
add r16 = 8,r16 ;;
 573 
add r16 = 8,r16 ;;
574 
st8 [r16] = r91;;
 574 
st8 [r16] = r91;;
575 
add r16 = 8,r16 ;;
 575 
add r16 = 8,r16 ;;
576 
st8 [r16] = r92;;
 576 
st8 [r16] = r92;;
577 
add r16 = 8,r16 ;;
 577 
add r16 = 8,r16 ;;
578 
st8 [r16] = r93;;
 578 
st8 [r16] = r93;;
579 
add r16 = 8,r16 ;;
 579 
add r16 = 8,r16 ;;
580 
st8 [r16] = r94;;
 580 
st8 [r16] = r94;;
581 
add r16 = 8,r16 ;;
 581 
add r16 = 8,r16 ;;
582 
st8 [r16] = r95;;
 582 
st8 [r16] = r95;;
583 
add r16 = 8,r16 ;;
 583 
add r16 = 8,r16 ;;
584 
 
 584 
 
585 
 
 585 
 
586 
 
 586 
 
587 
st8 [r16] = r96;;
 587 
st8 [r16] = r96;;
588 
add r16 = 8,r16 ;;
 588 
add r16 = 8,r16 ;;
589 
st8 [r16] = r97;;
 589 
st8 [r16] = r97;;
590 
add r16 = 8,r16 ;;
 590 
add r16 = 8,r16 ;;
591 
st8 [r16] = r98;;
 591 
st8 [r16] = r98;;
592 
add r16 = 8,r16 ;;
 592 
add r16 = 8,r16 ;;
593 
st8 [r16] = r99;;
 593 
st8 [r16] = r99;;
594 
add r16 = 8,r16 ;;
 594 
add r16 = 8,r16 ;;
595 
st8 [r16] = r100;;
 595 
st8 [r16] = r100;;
596 
add r16 = 8,r16 ;;
 596 
add r16 = 8,r16 ;;
597 
st8 [r16] = r101;;
 597 
st8 [r16] = r101;;
598 
add r16 = 8,r16 ;;
 598 
add r16 = 8,r16 ;;
599 
st8 [r16] = r102;;
 599 
st8 [r16] = r102;;
600 
add r16 = 8,r16 ;;
 600 
add r16 = 8,r16 ;;
601 
st8 [r16] = r103;;
 601 
st8 [r16] = r103;;
602 
add r16 = 8,r16 ;;
 602 
add r16 = 8,r16 ;;
603 
st8 [r16] = r104;;
 603 
st8 [r16] = r104;;
604 
add r16 = 8,r16 ;;
 604 
add r16 = 8,r16 ;;
605 
st8 [r16] = r105;;
 605 
st8 [r16] = r105;;
606 
add r16 = 8,r16 ;;
 606 
add r16 = 8,r16 ;;
607 
st8 [r16] = r106;;
 607 
st8 [r16] = r106;;
608 
add r16 = 8,r16 ;;
 608 
add r16 = 8,r16 ;;
609 
st8 [r16] = r107;;
 609 
st8 [r16] = r107;;
610 
add r16 = 8,r16 ;;
 610 
add r16 = 8,r16 ;;
611 
st8 [r16] = r108;;
 611 
st8 [r16] = r108;;
612 
add r16 = 8,r16 ;;
 612 
add r16 = 8,r16 ;;
613 
st8 [r16] = r109;;
 613 
st8 [r16] = r109;;
614 
add r16 = 8,r16 ;;
 614 
add r16 = 8,r16 ;;
615 
st8 [r16] = r110;;
 615 
st8 [r16] = r110;;
616 
add r16 = 8,r16 ;;
 616 
add r16 = 8,r16 ;;
617 
st8 [r16] = r111;;
 617 
st8 [r16] = r111;;
618 
add r16 = 8,r16 ;;
 618 
add r16 = 8,r16 ;;
619 
st8 [r16] = r112;;
 619 
st8 [r16] = r112;;
620 
add r16 = 8,r16 ;;
 620 
add r16 = 8,r16 ;;
621 
st8 [r16] = r113;;
 621 
st8 [r16] = r113;;
622 
add r16 = 8,r16 ;;
 622 
add r16 = 8,r16 ;;
623 
st8 [r16] = r114;;
 623 
st8 [r16] = r114;;
624 
add r16 = 8,r16 ;;
 624 
add r16 = 8,r16 ;;
625 
st8 [r16] = r115;;
 625 
st8 [r16] = r115;;
626 
add r16 = 8,r16 ;;
 626 
add r16 = 8,r16 ;;
627 
st8 [r16] = r116;;
 627 
st8 [r16] = r116;;
628 
add r16 = 8,r16 ;;
 628 
add r16 = 8,r16 ;;
629 
st8 [r16] = r117;;
 629 
st8 [r16] = r117;;
630 
add r16 = 8,r16 ;;
 630 
add r16 = 8,r16 ;;
631 
st8 [r16] = r118;;
 631 
st8 [r16] = r118;;
632 
add r16 = 8,r16 ;;
 632 
add r16 = 8,r16 ;;
633 
st8 [r16] = r119;;
 633 
st8 [r16] = r119;;
634 
add r16 = 8,r16 ;;
 634 
add r16 = 8,r16 ;;
635 
st8 [r16] = r120;;
 635 
st8 [r16] = r120;;
636 
add r16 = 8,r16 ;;
 636 
add r16 = 8,r16 ;;
637 
st8 [r16] = r121;;
 637 
st8 [r16] = r121;;
638 
add r16 = 8,r16 ;;
 638 
add r16 = 8,r16 ;;
639 
st8 [r16] = r122;;
 639 
st8 [r16] = r122;;
640 
add r16 = 8,r16 ;;
 640 
add r16 = 8,r16 ;;
641 
st8 [r16] = r123;;
 641 
st8 [r16] = r123;;
642 
add r16 = 8,r16 ;;
 642 
add r16 = 8,r16 ;;
643 
st8 [r16] = r124;;
 643 
st8 [r16] = r124;;
644 
add r16 = 8,r16 ;;
 644 
add r16 = 8,r16 ;;
645 
st8 [r16] = r125;;
 645 
st8 [r16] = r125;;
646 
add r16 = 8,r16 ;;
 646 
add r16 = 8,r16 ;;
647 
st8 [r16] = r126;;
 647 
st8 [r16] = r126;;
648 
add r16 = 8,r16 ;;
 648 
add r16 = 8,r16 ;;
649 
st8 [r16] = r127;;
 649 
st8 [r16] = r127;;
650 
add r16 = 8,r16 ;;
 650 
add r16 = 8,r16 ;;
651 
 
 651 
 
652 
 
 652 
 
653 
 
 653 
 
654 
br.ret.sptk.many b0;;
 654 
br.ret.sptk.many b0;;
655 
 
 655 
 
656 
 
 656 
 
657 
 
 657 
 
658 
 
 658 
 
659 
 
 659 
 
660 
.macro Handler o h
 660 
.macro Handler o h
661 
.org IVT + \o
 661 
.org IVT + \o
662 
br \h;;
 662 
br \h;;
663 
.endm
 663 
.endm
664 
 
 664 
 
665 
.macro Handler2 o
665 
.macro Handler2 o
666 
.org IVT + \o
 666 
.org IVT + \o
667 
br.call.sptk.many b0 = dump_gregs;;
 667 
br.call.sptk.many b0 = dump_gregs;;
668 
mov r16 = \o ;;
 668 
mov r16 = \o ;;
669 
bsw.1;;
 669 
bsw.1;;
670 
br universal_handler;;
 670 
br universal_handler;;
671 
.endm
 671 
.endm
672 
 
 672 
 
673 
 
 673 
 
674 
 
 674 
 
675 
.global IVT
 675 
.global IVT
676 
.align 32768
 676 
.align 32768
677 
IVT:
 677 
IVT:
678 
 
 678 
 
679 
 
 679 
 
680 
Handler2 0x0000
 680 
Handler2 0x0000
681 
Handler2 0x0400
 681 
Handler2 0x0400
682 
Handler2 0x0800
 682 
Handler2 0x0800
683 
Handler2 0x0c00
 683 
Handler2 0x0c00
684 
Handler2 0x1000
 684 
Handler2 0x1000
685 
Handler2 0x1400
 685 
Handler2 0x1400
686 
Handler2 0x1800
 686 
Handler2 0x1800
687 
Handler2 0x1c00
 687 
Handler2 0x1c00
688 
Handler2 0x2000
 688 
Handler2 0x2000
689 
Handler2 0x2400
 689 
Handler2 0x2400
690 
Handler2 0x2800
 690 
Handler2 0x2800
691 
Handler 0x2c00 break_instruction
 691 
Handler 0x2c00 break_instruction
692 
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
 692 
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
693 
Handler2 0x3400
 693 
Handler2 0x3400
694 
Handler2 0x3800
 694 
Handler2 0x3800
695 
Handler2 0x3c00
 695 
Handler2 0x3c00
696 
Handler2 0x4000
 696 
Handler2 0x4000
697 
Handler2 0x4400
 697 
Handler2 0x4400
698 
Handler2 0x4800
 698 
Handler2 0x4800
699 
Handler2 0x4c00
 699 
Handler2 0x4c00
700 
 
 700 
 
701 
Handler2 0x5000
 701 
Handler2 0x5000
702 
Handler2 0x5100
 702 
Handler2 0x5100
703 
Handler2 0x5200
 703 
Handler2 0x5200
704 
Handler2 0x5300
 704 
Handler2 0x5300
705 
#Handler 0x5400 general_exception
 705 
#Handler 0x5400 general_exception
706 
Handler2 0x5400
 706 
Handler2 0x5400
707 
Handler2 0x5500
 707 
Handler2 0x5500
708 
Handler2 0x5600
 708 
Handler2 0x5600
709 
Handler2 0x5700
 709 
Handler2 0x5700
710 
Handler2 0x5800
 710 
Handler2 0x5800
711 
Handler2 0x5900
 711 
Handler2 0x5900
712 
Handler2 0x5a00
 712 
Handler2 0x5a00
713 
Handler2 0x5b00
 713 
Handler2 0x5b00
714 
Handler2 0x5c00
 714 
Handler2 0x5c00
715 
Handler2 0x5d00
 715 
Handler2 0x5d00
716 
Handler2 0x5e00
 716 
Handler2 0x5e00
717 
Handler2 0x5f00
 717 
Handler2 0x5f00
718 
 
 718 
 
719 
Handler2 0x6000
 719 
Handler2 0x6000
720 
Handler2 0x6100
 720 
Handler2 0x6100
721 
Handler2 0x6200
 721 
Handler2 0x6200
722 
Handler2 0x6300
 722 
Handler2 0x6300
723 
Handler2 0x6400
 723 
Handler2 0x6400
724 
Handler2 0x6500
 724 
Handler2 0x6500
725 
Handler2 0x6600
 725 
Handler2 0x6600
726 
Handler2 0x6700
 726 
Handler2 0x6700
727 
Handler2 0x6800
 727 
Handler2 0x6800
728 
Handler2 0x6900
 728 
Handler2 0x6900
729 
Handler2 0x6a00
 729 
Handler2 0x6a00
730 
Handler2 0x6b00
 730 
Handler2 0x6b00
731 
Handler2 0x6c00
 731 
Handler2 0x6c00
732 
Handler2 0x6d00
 732 
Handler2 0x6d00
733 
Handler2 0x6e00
 733 
Handler2 0x6e00
734 
Handler2 0x6f00
 734 
Handler2 0x6f00
735 
 
 735 
 
736 
Handler2 0x7000
 736 
Handler2 0x7000
737 
Handler2 0x7100
 737 
Handler2 0x7100
738 
Handler2 0x7200
 738 
Handler2 0x7200
739 
Handler2 0x7300
 739 
Handler2 0x7300
740 
Handler2 0x7400
 740 
Handler2 0x7400
741 
Handler2 0x7500
 741 
Handler2 0x7500
742 
Handler2 0x7600
 742 
Handler2 0x7600
743 
Handler2 0x7700
 743 
Handler2 0x7700
744 
Handler2 0x7800
 744 
Handler2 0x7800
745 
Handler2 0x7900
 745 
Handler2 0x7900
746 
Handler2 0x7a00
 746 
Handler2 0x7a00
747 
Handler2 0x7b00
 747 
Handler2 0x7b00
748 
Handler2 0x7c00
 748 
Handler2 0x7c00
749 
Handler2 0x7d00
 749 
Handler2 0x7d00
750 
Handler2 0x7e00
 750 
Handler2 0x7e00
751 
Handler2 0x7f00
 751 
Handler2 0x7f00
752 
 
 752 
 
753 
 
 753 
 
754 
 
 754 
 
755 
 
 755 
 
756 
 
 756 
 
757 
 
 757 
 
758 
 
 758 
 
759 
 
 759 
 
760 
.align 32768
 760 
.align 32768
761 
.global REG_DUMP
 761 
.global REG_DUMP
762 
 
 762 
 
763 
REG_DUMP:
 763 
REG_DUMP:
764 
.space 128*8
 764 
.space 128*8
765 
 
 765 
 
766 
 
 766