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| 1 | # |
1 | # |
| 2 | # Copyright (C) 2005 Jakub Vana |
2 | # Copyright (C) 2005 Jakub Vana |
| 3 | # Copyright (C) 2005 Jakub Jermar |
3 | # Copyright (C) 2005 Jakub Jermar |
| 4 | # All rights reserved. |
4 | # All rights reserved. |
| 5 | # |
5 | # |
| 6 | # Redistribution and use in source and binary forms, with or without |
6 | # Redistribution and use in source and binary forms, with or without |
| 7 | # modification, are permitted provided that the following conditions |
7 | # modification, are permitted provided that the following conditions |
| 8 | # are met: |
8 | # are met: |
| 9 | # |
9 | # |
| 10 | # - Redistributions of source code must retain the above copyright |
10 | # - Redistributions of source code must retain the above copyright |
| 11 | # notice, this list of conditions and the following disclaimer. |
11 | # notice, this list of conditions and the following disclaimer. |
| 12 | # - Redistributions in binary form must reproduce the above copyright |
12 | # - Redistributions in binary form must reproduce the above copyright |
| 13 | # notice, this list of conditions and the following disclaimer in the |
13 | # notice, this list of conditions and the following disclaimer in the |
| 14 | # documentation and/or other materials provided with the distribution. |
14 | # documentation and/or other materials provided with the distribution. |
| 15 | # - The name of the author may not be used to endorse or promote products |
15 | # - The name of the author may not be used to endorse or promote products |
| 16 | # derived from this software without specific prior written permission. |
16 | # derived from this software without specific prior written permission. |
| 17 | # |
17 | # |
| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | # |
28 | # |
| 29 | 29 | ||
| 30 | #include <arch/stack.h> |
30 | #include <arch/stack.h> |
| 31 | #include <arch/register.h> |
31 | #include <arch/register.h> |
| 32 | #include <arch/mm/page.h> |
32 | #include <arch/mm/page.h> |
| 33 | #include <align.h> |
33 | #include <align.h> |
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | #define FRS_TO_SAVE 30 |
36 | #define FRS_TO_SAVE 30 |
| 37 | #define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
37 | #define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
| 38 | //#define STACK_ITEMS 19 |
38 | //#define STACK_ITEMS 19 |
| 39 | /* 30*2 for FPU registers */ |
39 | /* 30*2 for FPU registers */ |
| 40 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
40 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
| 41 | 41 | ||
| 42 | #if (STACK_ITEMS % 2 == 0) |
42 | #if (STACK_ITEMS % 2 == 0) |
| 43 | # define STACK_FRAME_BIAS 8 |
43 | # define STACK_FRAME_BIAS 8 |
| 44 | #else |
44 | #else |
| 45 | # define STACK_FRAME_BIAS 16 |
45 | # define STACK_FRAME_BIAS 16 |
| 46 | #endif |
46 | #endif |
| 47 | 47 | ||
| 48 | /** Partitioning of bank 0 registers. */ |
48 | /** Partitioning of bank 0 registers. */ |
| 49 | #define R_OFFS r16 |
49 | #define R_OFFS r16 |
| 50 | #define R_HANDLER r17 |
50 | #define R_HANDLER r17 |
| 51 | #define R_RET r18 |
51 | #define R_RET r18 |
| 52 | #define R_TMP r19 |
52 | #define R_TMP r19 |
| 53 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */ |
53 | #define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */ |
| 54 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */ |
54 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */ |
| 55 | 55 | ||
| 56 | /** Heavyweight interrupt handler |
56 | /** Heavyweight interrupt handler |
| 57 | * |
57 | * |
| 58 | * This macro roughly follows steps from 1 to 19 described in |
58 | * This macro roughly follows steps from 1 to 19 described in |
| 59 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
59 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
| 60 | * |
60 | * |
| 61 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
61 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
| 62 | * This goal is achieved by using procedure calls after RSE becomes operational. |
62 | * This goal is achieved by using procedure calls after RSE becomes operational. |
| 63 | * |
63 | * |
| 64 | * Some steps are skipped (enabling and disabling interrupts). |
64 | * Some steps are skipped (enabling and disabling interrupts). |
| 65 | * Some steps are not fully supported yet (e.g. dealing with floating-point |
- | |
| 66 | * context). |
- | |
| 67 | * |
65 | * |
| 68 | * @param offs Offset from the beginning of IVT. |
66 | * @param offs Offset from the beginning of IVT. |
| 69 | * @param handler Interrupt handler address. |
67 | * @param handler Interrupt handler address. |
| 70 | */ |
68 | */ |
| 71 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler |
69 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler |
| 72 | .org ivt + \offs |
70 | .org ivt + \offs |
| 73 | mov R_OFFS = \offs |
71 | mov R_OFFS = \offs |
| 74 | movl R_HANDLER = \handler ;; |
72 | movl R_HANDLER = \handler ;; |
| 75 | br heavyweight_handler |
73 | br heavyweight_handler |
| 76 | .endm |
74 | .endm |
| 77 | 75 | ||
| 78 | .global heavyweight_handler |
76 | .global heavyweight_handler |
| 79 | heavyweight_handler: |
77 | heavyweight_handler: |
| 80 | /* 1. copy interrupt registers into bank 0 */ |
78 | /* 1. copy interrupt registers into bank 0 */ |
| 81 | 79 | ||
| 82 | /* |
80 | /* |
| 83 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
81 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. |
| 84 | */ |
82 | */ |
| 85 | 83 | ||
| 86 | /*Set up FPU as in interrupred*/ |
84 | /* Set up FPU as in interrupted context. */ |
| 87 | mov r24=psr |
85 | mov r24 = psr |
| 88 | mov r25=cr.ipsr |
86 | mov r25 = cr.ipsr |
| 89 | mov r26=(PSR_DFH_MASK) |
87 | mov r26 = PSR_DFH_MASK |
| 90 | mov r27=(~(PSR_DFH_MASK));; |
88 | mov r27 = ~PSR_DFH_MASK ;; |
| 91 | and r26=r25,r26 |
89 | and r26 = r25, r26 |
| 92 | and r24=r24,r27;; |
90 | and r24 = r24, r27;; |
| 93 | or r24=r24,r26;; |
91 | or r24 = r24, r26;; |
| 94 | mov psr.l=r24;; |
92 | mov psr.l = r24;; |
| 95 | srlz.i |
93 | srlz.i |
| 96 | srlz.d;; |
94 | srlz.d;; |
| 97 | 95 | ||
| 98 | mov r24 = cr.iip |
96 | mov r24 = cr.iip |
| 99 | mov r25 = cr.ipsr |
97 | mov r25 = cr.ipsr |
| 100 | mov r26 = cr.iipa |
98 | mov r26 = cr.iipa |
| 101 | mov r27 = cr.isr |
99 | mov r27 = cr.isr |
| 102 | mov r28 = cr.ifa |
100 | mov r28 = cr.ifa |
| 103 | 101 | ||
| 104 | /* 2. preserve predicate register into bank 0 */ |
102 | /* 2. preserve predicate register into bank 0 */ |
| 105 | mov r29 = pr ;; |
103 | mov r29 = pr ;; |
| 106 | 104 | ||
| 107 | /* 3. switch to kernel memory stack */ |
105 | /* 3. switch to kernel memory stack */ |
| 108 | mov r30 = cr.ipsr |
106 | mov r30 = cr.ipsr |
| 109 | shr.u r31 = r12, VRN_SHIFT ;; |
107 | shr.u r31 = r12, VRN_SHIFT ;; |
| 110 | 108 | ||
| 111 | shr.u r30 = r30, PSR_CPL_SHIFT ;; |
109 | shr.u r30 = r30, PSR_CPL_SHIFT ;; |
| 112 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;; |
110 | and r30 = PSR_CPL_MASK_SHIFTED, r30 ;; |
| 113 | 111 | ||
| 114 | /* |
112 | /* |
| 115 | * Set p3 to true if the interrupted context executed in kernel mode. |
113 | * Set p3 to true if the interrupted context executed in kernel mode. |
| 116 | * Set p4 to false if the interrupted context didn't execute in kernel mode. |
114 | * Set p4 to false if the interrupted context didn't execute in kernel mode. |
| 117 | */ |
115 | */ |
| 118 | cmp.eq p3, p4 = r30, r0 ;; |
116 | cmp.eq p3, p4 = r30, r0 ;; |
| 119 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */ |
117 | cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */ |
| 120 | 118 | ||
| 121 | /* |
119 | /* |
| 122 | * Set p3 to true if the stack register references kernel address space. |
120 | * Set p3 to true if the stack register references kernel address space. |
| 123 | * Set p4 to false if the stack register doesn't reference kernel address space. |
121 | * Set p4 to false if the stack register doesn't reference kernel address space. |
| 124 | */ |
122 | */ |
| 125 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; |
123 | (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; |
| 126 | 124 | ||
| 127 | /* |
125 | /* |
| 128 | * Now, p4 is true iff the stack needs to be switched to kernel stack. |
126 | * Now, p4 is true iff the stack needs to be switched to kernel stack. |
| 129 | */ |
127 | */ |
| 130 | mov r30 = r12 |
128 | mov r30 = r12 |
| 131 | (p4) mov r12 = R_KSTACK ;; |
129 | (p4) mov r12 = R_KSTACK ;; |
| 132 | 130 | ||
| 133 | add r31 = -STACK_FRAME_BIAS, r12 ;; |
131 | add r31 = -STACK_FRAME_BIAS, r12 ;; |
| 134 | add r12 = -STACK_FRAME_SIZE, r12 |
132 | add r12 = -STACK_FRAME_SIZE, r12 |
| 135 | 133 | ||
| 136 | /* 4. save registers in bank 0 into memory stack */ |
134 | /* 4. save registers in bank 0 into memory stack */ |
| 137 | 135 | ||
| 138 | /* |
136 | /* |
| 139 | * If this is break_instruction handler, |
137 | * If this is break_instruction handler, |
| 140 | * copy input parameters to stack. |
138 | * copy input parameters to stack. |
| 141 | */ |
139 | */ |
| 142 | mov R_TMP = 0x2c00 ;; |
140 | mov R_TMP = 0x2c00 ;; |
| 143 | cmp.eq p6,p5 = R_OFFS, R_TMP ;; |
141 | cmp.eq p6,p5 = R_OFFS, R_TMP ;; |
| 144 | 142 | ||
| 145 | /* |
143 | /* |
| 146 | * From now on, if this is break_instruction handler, p6 is true and p5 is false. |
144 | * From now on, if this is break_instruction handler, p6 is true and p5 is false. |
| 147 | * Otherwise p6 is false and p5 is true. |
145 | * Otherwise p6 is false and p5 is true. |
| 148 | * Note that p5 is a preserved predicate register and we make use of it. |
146 | * Note that p5 is a preserved predicate register and we make use of it. |
| 149 | */ |
147 | */ |
| 150 | 148 | ||
| 151 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */ |
149 | (p6) st8 [r31] = r36, -8 ;; /* save in4 */ |
| 152 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */ |
150 | (p6) st8 [r31] = r35, -8 ;; /* save in3 */ |
| 153 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */ |
151 | (p6) st8 [r31] = r34, -8 ;; /* save in2 */ |
| 154 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */ |
152 | (p6) st8 [r31] = r33, -8 ;; /* save in1 */ |
| 155 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */ |
153 | (p6) st8 [r31] = r32, -8 ;; /* save in0 */ |
| 156 | (p5) add r31 = -40, r31 ;; |
154 | (p5) add r31 = -40, r31 ;; |
| 157 | 155 | ||
| 158 | st8 [r31] = r30, -8 ;; /* save old stack pointer */ |
156 | st8 [r31] = r30, -8 ;; /* save old stack pointer */ |
| 159 | 157 | ||
| 160 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
158 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
| 161 | 159 | ||
| 162 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
160 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
| 163 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
161 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
| 164 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
162 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
| 165 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
163 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
| 166 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
164 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
| 167 | 165 | ||
| 168 | /* 5. RSE switch from interrupted context */ |
166 | /* 5. RSE switch from interrupted context */ |
| 169 | mov r24 = ar.rsc |
167 | mov r24 = ar.rsc |
| 170 | mov r25 = ar.pfs |
168 | mov r25 = ar.pfs |
| 171 | cover |
169 | cover |
| 172 | mov r26 = cr.ifs |
170 | mov r26 = cr.ifs |
| 173 | 171 | ||
| 174 | st8 [r31] = r24, -8 ;; /* save ar.rsc */ |
172 | st8 [r31] = r24, -8 ;; /* save ar.rsc */ |
| 175 | st8 [r31] = r25, -8 ;; /* save ar.pfs */ |
173 | st8 [r31] = r25, -8 ;; /* save ar.pfs */ |
| 176 | st8 [r31] = r26, -8 /* save ar.ifs */ |
174 | st8 [r31] = r26, -8 /* save ar.ifs */ |
| 177 | 175 | ||
| 178 | and r24 = ~(RSC_PL_MASK), r24 ;; |
176 | and r24 = ~(RSC_PL_MASK), r24 ;; |
| 179 | and r30 = ~(RSC_MODE_MASK), r24 ;; |
177 | and r30 = ~(RSC_MODE_MASK), r24 ;; |
| 180 | mov ar.rsc = r30 ;; /* update RSE state */ |
178 | mov ar.rsc = r30 ;; /* update RSE state */ |
| 181 | 179 | ||
| 182 | mov r27 = ar.rnat |
180 | mov r27 = ar.rnat |
| 183 | mov r28 = ar.bspstore ;; |
181 | mov r28 = ar.bspstore ;; |
| 184 | 182 | ||
| 185 | /* |
183 | /* |
| 186 | * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE. |
184 | * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE. |
| 187 | */ |
185 | */ |
| 188 | (p1) shr.u r30 = r28, VRN_SHIFT ;; |
186 | (p1) shr.u r30 = r28, VRN_SHIFT ;; |
| 189 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; |
187 | (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; |
| 190 | 188 | ||
| 191 | /* |
189 | /* |
| 192 | * If BSPSTORE needs to be switched, p1 is false and p2 is true. |
190 | * If BSPSTORE needs to be switched, p1 is false and p2 is true. |
| 193 | */ |
191 | */ |
| 194 | (p1) mov r30 = r28 |
192 | (p1) mov r30 = r28 |
| 195 | (p2) mov r30 = R_KSTACK_BSP ;; |
193 | (p2) mov r30 = R_KSTACK_BSP ;; |
| 196 | (p2) mov ar.bspstore = r30 ;; |
194 | (p2) mov ar.bspstore = r30 ;; |
| 197 | 195 | ||
| 198 | mov r29 = ar.bsp |
196 | mov r29 = ar.bsp |
| 199 | 197 | ||
| 200 | st8 [r31] = r27, -8 ;; /* save ar.rnat */ |
198 | st8 [r31] = r27, -8 ;; /* save ar.rnat */ |
| 201 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */ |
199 | st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */ |
| 202 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */ |
200 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */ |
| 203 | st8 [r31] = r29, -8 /* save ar.bsp */ |
201 | st8 [r31] = r29, -8 /* save ar.bsp */ |
| 204 | 202 | ||
| 205 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ |
203 | mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ |
| 206 | 204 | ||
| 207 | /* steps 6 - 15 are done by heavyweight_handler_inner() */ |
205 | /* steps 6 - 15 are done by heavyweight_handler_inner() */ |
| 208 | mov R_RET = b0 /* save b0 belonging to interrupted context */ |
206 | mov R_RET = b0 /* save b0 belonging to interrupted context */ |
| 209 | br.call.sptk.many b0 = heavyweight_handler_inner |
207 | br.call.sptk.many b0 = heavyweight_handler_inner |
| 210 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
208 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */ |
| 211 | 209 | ||
| 212 | /* 16. RSE switch to interrupted context */ |
210 | /* 16. RSE switch to interrupted context */ |
| 213 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
211 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
| 214 | 212 | ||
| 215 | add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;; |
213 | add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;; |
| 216 | 214 | ||
| 217 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
215 | ld8 r30 = [r31], +8 ;; /* load ar.bsp */ |
| 218 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
216 | ld8 r29 = [r31], +8 ;; /* load ar.bspstore */ |
| 219 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
217 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */ |
| 220 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
218 | sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */ |
| 221 | shl r27 = r27, 16 |
219 | shl r27 = r27, 16 |
| 222 | 220 | ||
| 223 | mov r24 = ar.rsc ;; |
221 | mov r24 = ar.rsc ;; |
| 224 | and r30 = ~3, r24 ;; |
222 | and r30 = ~3, r24 ;; |
| 225 | or r24 = r30 , r27 ;; |
223 | or r24 = r30 , r27 ;; |
| 226 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */ |
224 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */ |
| 227 | 225 | ||
| 228 | loadrs /* (step 3) */ |
226 | loadrs /* (step 3) */ |
| 229 | 227 | ||
| 230 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */ |
228 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */ |
| 231 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */ |
229 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */ |
| 232 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */ |
230 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */ |
| 233 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */ |
231 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */ |
| 234 | 232 | ||
| 235 | mov ar.bspstore = r29 ;; /* (step 4) */ |
233 | mov ar.bspstore = r29 ;; /* (step 4) */ |
| 236 | mov ar.rnat = r27 /* (step 5) */ |
234 | mov ar.rnat = r27 /* (step 5) */ |
| 237 | 235 | ||
| 238 | mov ar.pfs = r25 /* (step 6) */ |
236 | mov ar.pfs = r25 /* (step 6) */ |
| 239 | mov cr.ifs = r26 |
237 | mov cr.ifs = r26 |
| 240 | 238 | ||
| 241 | mov ar.rsc = r24 /* (step 7) */ |
239 | mov ar.rsc = r24 /* (step 7) */ |
| 242 | 240 | ||
| 243 | /* 17. restore interruption state from memory stack */ |
241 | /* 17. restore interruption state from memory stack */ |
| 244 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
242 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
| 245 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
243 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
| 246 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
244 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
| 247 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
245 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
| 248 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
246 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
| 249 | 247 | ||
| 250 | mov cr.iip = r24;; |
248 | mov cr.iip = r24;; |
| 251 | mov cr.iipa = r26 |
249 | mov cr.iipa = r26 |
| 252 | mov cr.isr = r27 |
250 | mov cr.isr = r27 |
| 253 | mov cr.ifa = r28 |
251 | mov cr.ifa = r28 |
| - | 252 | ||
| 254 | /*Set up FPU as in exception*/ |
253 | /* Set up FPU as in exception. */ |
| 255 | mov r24=psr |
254 | mov r24 = psr |
| 256 | mov r26=(PSR_DFH_MASK) |
255 | mov r26 = PSR_DFH_MASK |
| 257 | mov r27=(~(PSR_DFH_MASK));; |
256 | mov r27 = ~PSR_DFH_MASK ;; |
| 258 | and r25=r25,r27 |
257 | and r25 = r25, r27 |
| 259 | and r24=r24,r26;; |
258 | and r24 = r24, r26 ;; |
| 260 | or r25=r25,r24;; |
259 | or r25 = r25, r24;; |
| 261 | mov cr.ipsr = r25 |
260 | mov cr.ipsr = r25 |
| 262 | - | ||
| 263 | 261 | ||
| 264 | /* 18. restore predicate registers from memory stack */ |
262 | /* 18. restore predicate registers from memory stack */ |
| 265 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
263 | ld8 r29 = [r31], +8 ;; /* load predicate registers */ |
| 266 | mov pr = r29 |
264 | mov pr = r29 |
| 267 | 265 | ||
| 268 | /* 19. return from interruption */ |
266 | /* 19. return from interruption */ |
| 269 | ld8 r12 = [r31] /* load stack pointer */ |
267 | ld8 r12 = [r31] /* load stack pointer */ |
| 270 | rfi ;; |
268 | rfi ;; |
| 271 | 269 | ||
| 272 | .global heavyweight_handler_inner |
270 | .global heavyweight_handler_inner |
| 273 | heavyweight_handler_inner: |
271 | heavyweight_handler_inner: |
| 274 | /* |
272 | /* |
| 275 | * From this point, the rest of the interrupted context |
273 | * From this point, the rest of the interrupted context |
| 276 | * will be preserved in stacked registers and backing store. |
274 | * will be preserved in stacked registers and backing store. |
| 277 | */ |
275 | */ |
| 278 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; |
276 | alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; |
| 279 | 277 | ||
| 280 | /* bank 0 is going to be shadowed, copy essential data from there */ |
278 | /* bank 0 is going to be shadowed, copy essential data from there */ |
| 281 | mov loc1 = R_RET /* b0 belonging to interrupted context */ |
279 | mov loc1 = R_RET /* b0 belonging to interrupted context */ |
| 282 | mov loc2 = R_HANDLER |
280 | mov loc2 = R_HANDLER |
| 283 | mov out0 = R_OFFS |
281 | mov out0 = R_OFFS |
| 284 | 282 | ||
| 285 | add out1 = STACK_SCRATCH_AREA_SIZE, r12 |
283 | add out1 = STACK_SCRATCH_AREA_SIZE, r12 |
| 286 | 284 | ||
| 287 | /* 6. switch to bank 1 and reenable PSR.ic */ |
285 | /* 6. switch to bank 1 and reenable PSR.ic */ |
| 288 | ssm PSR_IC_MASK |
286 | ssm PSR_IC_MASK |
| 289 | bsw.1 ;; |
287 | bsw.1 ;; |
| 290 | srlz.d |
288 | srlz.d |
| 291 | 289 | ||
| 292 | /* 7. preserve branch and application registers */ |
290 | /* 7. preserve branch and application registers */ |
| 293 | mov loc3 = ar.unat |
291 | mov loc3 = ar.unat |
| 294 | mov loc4 = ar.lc |
292 | mov loc4 = ar.lc |
| 295 | mov loc5 = ar.ec |
293 | mov loc5 = ar.ec |
| 296 | mov loc6 = ar.ccv |
294 | mov loc6 = ar.ccv |
| 297 | mov loc7 = ar.csd |
295 | mov loc7 = ar.csd |
| 298 | mov loc8 = ar.ssd |
296 | mov loc8 = ar.ssd |
| 299 | 297 | ||
| 300 | mov loc9 = b0 |
298 | mov loc9 = b0 |
| 301 | mov loc10 = b1 |
299 | mov loc10 = b1 |
| 302 | mov loc11 = b2 |
300 | mov loc11 = b2 |
| 303 | mov loc12 = b3 |
301 | mov loc12 = b3 |
| 304 | mov loc13 = b4 |
302 | mov loc13 = b4 |
| 305 | mov loc14 = b5 |
303 | mov loc14 = b5 |
| 306 | mov loc15 = b6 |
304 | mov loc15 = b6 |
| 307 | mov loc16 = b7 |
305 | mov loc16 = b7 |
| 308 | 306 | ||
| 309 | /* 8. preserve general and floating-point registers */ |
307 | /* 8. preserve general and floating-point registers */ |
| 310 | /* TODO: save floating-point context */ |
- | |
| 311 | mov loc17 = r1 |
308 | mov loc17 = r1 |
| 312 | mov loc18 = r2 |
309 | mov loc18 = r2 |
| 313 | mov loc19 = r3 |
310 | mov loc19 = r3 |
| 314 | mov loc20 = r4 |
311 | mov loc20 = r4 |
| 315 | mov loc21 = r5 |
312 | mov loc21 = r5 |
| 316 | mov loc22 = r6 |
313 | mov loc22 = r6 |
| 317 | mov loc23 = r7 |
314 | mov loc23 = r7 |
| 318 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */ |
315 | (p5) mov loc24 = r8 /* only if not in break_instruction handler */ |
| 319 | mov loc25 = r9 |
316 | mov loc25 = r9 |
| 320 | mov loc26 = r10 |
317 | mov loc26 = r10 |
| 321 | mov loc27 = r11 |
318 | mov loc27 = r11 |
| 322 | /* skip r12 (stack pointer) */ |
319 | /* skip r12 (stack pointer) */ |
| 323 | mov loc28 = r13 |
320 | mov loc28 = r13 |
| 324 | mov loc29 = r14 |
321 | mov loc29 = r14 |
| 325 | mov loc30 = r15 |
322 | mov loc30 = r15 |
| 326 | mov loc31 = r16 |
323 | mov loc31 = r16 |
| 327 | mov loc32 = r17 |
324 | mov loc32 = r17 |
| 328 | mov loc33 = r18 |
325 | mov loc33 = r18 |
| 329 | mov loc34 = r19 |
326 | mov loc34 = r19 |
| 330 | mov loc35 = r20 |
327 | mov loc35 = r20 |
| 331 | mov loc36 = r21 |
328 | mov loc36 = r21 |
| 332 | mov loc37 = r22 |
329 | mov loc37 = r22 |
| 333 | mov loc38 = r23 |
330 | mov loc38 = r23 |
| 334 | mov loc39 = r24 |
331 | mov loc39 = r24 |
| 335 | mov loc40 = r25 |
332 | mov loc40 = r25 |
| 336 | mov loc41 = r26 |
333 | mov loc41 = r26 |
| 337 | mov loc42 = r27 |
334 | mov loc42 = r27 |
| 338 | mov loc43 = r28 |
335 | mov loc43 = r28 |
| 339 | mov loc44 = r29 |
336 | mov loc44 = r29 |
| 340 | mov loc45 = r30 |
337 | mov loc45 = r30 |
| 341 | mov loc46 = r31 |
338 | mov loc46 = r31 |
| 342 | 339 | ||
| 343 | mov r24=96 + STACK_SCRATCH_AREA_SIZE |
340 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12 |
| 344 | mov r25=112 + STACK_SCRATCH_AREA_SIZE |
341 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12 |
| 345 | mov r26=0 + STACK_SCRATCH_AREA_SIZE |
342 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12 |
| 346 | mov r27=16 + STACK_SCRATCH_AREA_SIZE |
343 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12 |
| 347 | mov r28=32 + STACK_SCRATCH_AREA_SIZE |
344 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12 |
| 348 | mov r29=48 + STACK_SCRATCH_AREA_SIZE |
345 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12 |
| 349 | mov r30=64 + STACK_SCRATCH_AREA_SIZE |
346 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12 |
| 350 | mov r31=80 + STACK_SCRATCH_AREA_SIZE;; |
347 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;; |
| 351 | add r24=r12,r24 |
- | |
| 352 | add r25=r12,r25 |
- | |
| 353 | add r26=r12,r26 |
- | |
| 354 | add r27=r12,r27 |
- | |
| 355 | add r28=r12,r28 |
- | |
| 356 | add r29=r12,r29 |
- | |
| 357 | add r30=r12,r30 |
- | |
| 358 | add r31=r12,r31;; |
- | |
| 359 | 348 | ||
| 360 | stf.spill [r26]=f2,0x80 |
349 | stf.spill [r26] = f2, 0x80 |
| 361 | stf.spill [r27]=f3,0x80 |
350 | stf.spill [r27] = f3, 0x80 |
| 362 | stf.spill [r28]=f4,0x80 |
351 | stf.spill [r28] = f4, 0x80 |
| 363 | stf.spill [r29]=f5,0x80 |
352 | stf.spill [r29] = f5, 0x80 |
| 364 | stf.spill [r30]=f6,0x80 |
353 | stf.spill [r30] = f6, 0x80 |
| 365 | stf.spill [r31]=f7,0x80;; |
354 | stf.spill [r31] = f7, 0x80 ;; |
| 366 | 355 | ||
| 367 | stf.spill [r24]=f8,0x80 |
356 | stf.spill [r24] = f8, 0x80 |
| 368 | stf.spill [r25]=f9,0x80 |
357 | stf.spill [r25] = f9, 0x80 |
| 369 | stf.spill [r26]=f10,0x80 |
358 | stf.spill [r26] = f10, 0x80 |
| 370 | stf.spill [r27]=f11,0x80 |
359 | stf.spill [r27] = f11, 0x80 |
| 371 | stf.spill [r28]=f12,0x80 |
360 | stf.spill [r28] = f12, 0x80 |
| 372 | stf.spill [r29]=f13,0x80 |
361 | stf.spill [r29] = f13, 0x80 |
| 373 | stf.spill [r30]=f14,0x80 |
362 | stf.spill [r30] = f14, 0x80 |
| 374 | stf.spill [r31]=f15,0x80;; |
363 | stf.spill [r31] = f15, 0x80 ;; |
| 375 | 364 | ||
| 376 | stf.spill [r24]=f16,0x80 |
365 | stf.spill [r24] = f16, 0x80 |
| 377 | stf.spill [r25]=f17,0x80 |
366 | stf.spill [r25] = f17, 0x80 |
| 378 | stf.spill [r26]=f18,0x80 |
367 | stf.spill [r26] = f18, 0x80 |
| 379 | stf.spill [r27]=f19,0x80 |
368 | stf.spill [r27] = f19, 0x80 |
| 380 | stf.spill [r28]=f20,0x80 |
369 | stf.spill [r28] = f20, 0x80 |
| 381 | stf.spill [r29]=f21,0x80 |
370 | stf.spill [r29] = f21, 0x80 |
| 382 | stf.spill [r30]=f22,0x80 |
371 | stf.spill [r30] = f22, 0x80 |
| 383 | stf.spill [r31]=f23,0x80;; |
372 | stf.spill [r31] = f23, 0x80 ;; |
| 384 | 373 | ||
| 385 | stf.spill [r24]=f24,0x80 |
374 | stf.spill [r24] = f24, 0x80 |
| 386 | stf.spill [r25]=f25,0x80 |
375 | stf.spill [r25] = f25, 0x80 |
| 387 | stf.spill [r26]=f26,0x80 |
376 | stf.spill [r26] = f26, 0x80 |
| 388 | stf.spill [r27]=f27,0x80 |
377 | stf.spill [r27] = f27, 0x80 |
| 389 | stf.spill [r28]=f28,0x80 |
378 | stf.spill [r28] = f28, 0x80 |
| 390 | stf.spill [r29]=f29,0x80 |
379 | stf.spill [r29] = f29, 0x80 |
| 391 | stf.spill [r30]=f30,0x80 |
380 | stf.spill [r30] = f30, 0x80 |
| 392 | stf.spill [r31]=f31,0x80;; |
381 | stf.spill [r31] = f31, 0x80 ;; |
| 393 | 382 | ||
| 394 | /* preserve Floating point status register */ |
383 | mov loc47 = ar.fpsr /* preserve floating point status register */ |
| 395 | mov loc47 = ar.fpsr |
- | |
| 396 | 384 | ||
| 397 | /* 9. skipped (will not enable interrupts) */ |
385 | /* 9. skipped (will not enable interrupts) */ |
| 398 | /* |
386 | /* |
| 399 | * ssm PSR_I_MASK |
387 | * ssm PSR_I_MASK |
| 400 | * ;; |
388 | * ;; |
| 401 | * srlz.d |
389 | * srlz.d |
| 402 | */ |
390 | */ |
| 403 | 391 | ||
| 404 | /* 10. call handler */ |
392 | /* 10. call handler */ |
| 405 | movl r1 = _hardcoded_load_address |
393 | movl r1 = _hardcoded_load_address |
| 406 | 394 | ||
| 407 | mov b1 = loc2 |
395 | mov b1 = loc2 |
| 408 | br.call.sptk.many b0 = b1 |
396 | br.call.sptk.many b0 = b1 |
| 409 | 397 | ||
| 410 | /* 11. return from handler */ |
398 | /* 11. return from handler */ |
| 411 | 0: |
399 | 0: |
| 412 | 400 | ||
| 413 | /* 12. skipped (will not disable interrupts) */ |
401 | /* 12. skipped (will not disable interrupts) */ |
| 414 | /* |
402 | /* |
| 415 | * rsm PSR_I_MASK |
403 | * rsm PSR_I_MASK |
| 416 | * ;; |
404 | * ;; |
| 417 | * srlz.d |
405 | * srlz.d |
| 418 | */ |
406 | */ |
| 419 | 407 | ||
| 420 | /* 13. restore general and floating-point registers */ |
408 | /* 13. restore general and floating-point registers */ |
| 421 | /* TODO: restore floating-point context */ |
- | |
| 422 | mov r24=96 + STACK_SCRATCH_AREA_SIZE |
409 | add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12 |
| 423 | mov r25=112 + STACK_SCRATCH_AREA_SIZE |
410 | add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12 |
| 424 | mov r26=0 + STACK_SCRATCH_AREA_SIZE |
411 | add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12 |
| 425 | mov r27=16 + STACK_SCRATCH_AREA_SIZE |
412 | add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12 |
| 426 | mov r28=32 + STACK_SCRATCH_AREA_SIZE |
413 | add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12 |
| 427 | mov r29=48 + STACK_SCRATCH_AREA_SIZE |
414 | add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12 |
| 428 | mov r30=64 + STACK_SCRATCH_AREA_SIZE |
415 | add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12 |
| 429 | mov r31=80 + STACK_SCRATCH_AREA_SIZE;; |
416 | add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;; |
| 430 | add r24=r12,r24 |
- | |
| 431 | add r25=r12,r25 |
- | |
| 432 | add r26=r12,r26 |
- | |
| 433 | add r27=r12,r27 |
- | |
| 434 | add r28=r12,r28 |
- | |
| 435 | add r29=r12,r29 |
- | |
| 436 | add r30=r12,r30 |
- | |
| 437 | add r31=r12,r31;; |
- | |
| 438 | 417 | ||
| 439 | - | ||
| 440 | ldf.fill f2=[r26],0x80 |
418 | ldf.fill f2 = [r26], 0x80 |
| 441 | ldf.fill f3=[r27],0x80 |
419 | ldf.fill f3 = [r27], 0x80 |
| 442 | ldf.fill f4=[r28],0x80 |
420 | ldf.fill f4 = [r28], 0x80 |
| 443 | ldf.fill f5=[r29],0x80 |
421 | ldf.fill f5 = [r29], 0x80 |
| 444 | ldf.fill f6=[r30],0x80 |
422 | ldf.fill f6 = [r30], 0x80 |
| 445 | ldf.fill f7=[r31],0x80;; |
423 | ldf.fill f7 = [r31], 0x80 ;; |
| 446 | 424 | ||
| 447 | ldf.fill f8=[r24],0x80 |
425 | ldf.fill f8 = [r24], 0x80 |
| 448 | ldf.fill f9=[r25],0x80 |
426 | ldf.fill f9 = [r25], 0x80 |
| 449 | ldf.fill f10=[r26],0x80 |
427 | ldf.fill f10 = [r26], 0x80 |
| 450 | ldf.fill f11=[r27],0x80 |
428 | ldf.fill f11 = [r27], 0x80 |
| 451 | ldf.fill f12=[r28],0x80 |
429 | ldf.fill f12 = [r28], 0x80 |
| 452 | ldf.fill f13=[r29],0x80 |
430 | ldf.fill f13 = [r29], 0x80 |
| 453 | ldf.fill f14=[r30],0x80 |
431 | ldf.fill f14 = [r30], 0x80 |
| 454 | ldf.fill f15=[r31],0x80;; |
432 | ldf.fill f15 = [r31], 0x80 ;; |
| 455 | 433 | ||
| 456 | ldf.fill f16=[r24],0x80 |
434 | ldf.fill f16 = [r24], 0x80 |
| 457 | ldf.fill f17=[r25],0x80 |
435 | ldf.fill f17 = [r25], 0x80 |
| 458 | ldf.fill f18=[r26],0x80 |
436 | ldf.fill f18 = [r26], 0x80 |
| 459 | ldf.fill f19=[r27],0x80 |
437 | ldf.fill f19 = [r27], 0x80 |
| 460 | ldf.fill f20=[r28],0x80 |
438 | ldf.fill f20 = [r28], 0x80 |
| 461 | ldf.fill f21=[r29],0x80 |
439 | ldf.fill f21 = [r29], 0x80 |
| 462 | ldf.fill f22=[r30],0x80 |
440 | ldf.fill f22 = [r30], 0x80 |
| 463 | ldf.fill f23=[r31],0x80;; |
441 | ldf.fill f23 = [r31], 0x80 ;; |
| 464 | 442 | ||
| 465 | ldf.fill f24=[r24],0x80 |
443 | ldf.fill f24 = [r24], 0x80 |
| 466 | ldf.fill f25=[r25],0x80 |
444 | ldf.fill f25 = [r25], 0x80 |
| 467 | ldf.fill f26=[r26],0x80 |
445 | ldf.fill f26 = [r26], 0x80 |
| 468 | ldf.fill f27=[r27],0x80 |
446 | ldf.fill f27 = [r27], 0x80 |
| 469 | ldf.fill f28=[r28],0x80 |
447 | ldf.fill f28 = [r28], 0x80 |
| 470 | ldf.fill f29=[r29],0x80 |
448 | ldf.fill f29 = [r29], 0x80 |
| 471 | ldf.fill f30=[r30],0x80 |
449 | ldf.fill f30 = [r30], 0x80 |
| 472 | ldf.fill f31=[r31],0x80;; |
450 | ldf.fill f31 = [r31], 0x80 ;; |
| 473 | - | ||
| 474 | 451 | ||
| 475 | mov r1 = loc17 |
452 | mov r1 = loc17 |
| 476 | mov r2 = loc18 |
453 | mov r2 = loc18 |
| 477 | mov r3 = loc19 |
454 | mov r3 = loc19 |
| 478 | mov r4 = loc20 |
455 | mov r4 = loc20 |
| 479 | mov r5 = loc21 |
456 | mov r5 = loc21 |
| 480 | mov r6 = loc22 |
457 | mov r6 = loc22 |
| 481 | mov r7 = loc23 |
458 | mov r7 = loc23 |
| 482 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */ |
459 | (p5) mov r8 = loc24 /* only if not in break_instruction handler */ |
| 483 | mov r9 = loc25 |
460 | mov r9 = loc25 |
| 484 | mov r10 = loc26 |
461 | mov r10 = loc26 |
| 485 | mov r11 = loc27 |
462 | mov r11 = loc27 |
| 486 | /* skip r12 (stack pointer) */ |
463 | /* skip r12 (stack pointer) */ |
| 487 | mov r13 = loc28 |
464 | mov r13 = loc28 |
| 488 | mov r14 = loc29 |
465 | mov r14 = loc29 |
| 489 | mov r15 = loc30 |
466 | mov r15 = loc30 |
| 490 | mov r16 = loc31 |
467 | mov r16 = loc31 |
| 491 | mov r17 = loc32 |
468 | mov r17 = loc32 |
| 492 | mov r18 = loc33 |
469 | mov r18 = loc33 |
| 493 | mov r19 = loc34 |
470 | mov r19 = loc34 |
| 494 | mov r20 = loc35 |
471 | mov r20 = loc35 |
| 495 | mov r21 = loc36 |
472 | mov r21 = loc36 |
| 496 | mov r22 = loc37 |
473 | mov r22 = loc37 |
| 497 | mov r23 = loc38 |
474 | mov r23 = loc38 |
| 498 | mov r24 = loc39 |
475 | mov r24 = loc39 |
| 499 | mov r25 = loc40 |
476 | mov r25 = loc40 |
| 500 | mov r26 = loc41 |
477 | mov r26 = loc41 |
| 501 | mov r27 = loc42 |
478 | mov r27 = loc42 |
| 502 | mov r28 = loc43 |
479 | mov r28 = loc43 |
| 503 | mov r29 = loc44 |
480 | mov r29 = loc44 |
| 504 | mov r30 = loc45 |
481 | mov r30 = loc45 |
| 505 | mov r31 = loc46 |
482 | mov r31 = loc46 |
| 506 | 483 | ||
| 507 | /* restore Floating point status register */ |
484 | mov ar.fpsr = loc47 /* restore floating point status register */ |
| 508 | mov ar.fpsr = loc47 |
- | |
| 509 | 485 | ||
| 510 | /* 14. restore branch and application registers */ |
486 | /* 14. restore branch and application registers */ |
| 511 | mov ar.unat = loc3 |
487 | mov ar.unat = loc3 |
| 512 | mov ar.lc = loc4 |
488 | mov ar.lc = loc4 |
| 513 | mov ar.ec = loc5 |
489 | mov ar.ec = loc5 |
| 514 | mov ar.ccv = loc6 |
490 | mov ar.ccv = loc6 |
| 515 | mov ar.csd = loc7 |
491 | mov ar.csd = loc7 |
| 516 | mov ar.ssd = loc8 |
492 | mov ar.ssd = loc8 |
| 517 | 493 | ||
| 518 | mov b0 = loc9 |
494 | mov b0 = loc9 |
| 519 | mov b1 = loc10 |
495 | mov b1 = loc10 |
| 520 | mov b2 = loc11 |
496 | mov b2 = loc11 |
| 521 | mov b3 = loc12 |
497 | mov b3 = loc12 |
| 522 | mov b4 = loc13 |
498 | mov b4 = loc13 |
| 523 | mov b5 = loc14 |
499 | mov b5 = loc14 |
| 524 | mov b6 = loc15 |
500 | mov b6 = loc15 |
| 525 | mov b7 = loc16 |
501 | mov b7 = loc16 |
| 526 | 502 | ||
| 527 | /* 15. disable PSR.ic and switch to bank 0 */ |
503 | /* 15. disable PSR.ic and switch to bank 0 */ |
| 528 | rsm PSR_IC_MASK |
504 | rsm PSR_IC_MASK |
| 529 | bsw.0 ;; |
505 | bsw.0 ;; |
| 530 | srlz.d |
506 | srlz.d |
| 531 | 507 | ||
| 532 | mov R_RET = loc1 |
508 | mov R_RET = loc1 |
| 533 | mov ar.pfs = loc0 |
509 | mov ar.pfs = loc0 |
| 534 | br.ret.sptk.many b0 |
510 | br.ret.sptk.many b0 |
| 535 | 511 | ||
| 536 | .global ivt |
512 | .global ivt |
| 537 | .align 32768 |
513 | .align 32768 |
| 538 | ivt: |
514 | ivt: |
| 539 | HEAVYWEIGHT_HANDLER 0x0000 |
515 | HEAVYWEIGHT_HANDLER 0x0000 |
| 540 | HEAVYWEIGHT_HANDLER 0x0400 |
516 | HEAVYWEIGHT_HANDLER 0x0400 |
| 541 | HEAVYWEIGHT_HANDLER 0x0800 |
517 | HEAVYWEIGHT_HANDLER 0x0800 |
| 542 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault |
518 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault |
| 543 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault |
519 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault |
| 544 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault |
520 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault |
| 545 | HEAVYWEIGHT_HANDLER 0x1800 |
521 | HEAVYWEIGHT_HANDLER 0x1800 |
| 546 | HEAVYWEIGHT_HANDLER 0x1c00 |
522 | HEAVYWEIGHT_HANDLER 0x1c00 |
| 547 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault |
523 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault |
| 548 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault |
524 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault |
| 549 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault |
525 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault |
| 550 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction |
526 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction |
| 551 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
527 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
| 552 | HEAVYWEIGHT_HANDLER 0x3400 |
528 | HEAVYWEIGHT_HANDLER 0x3400 |
| 553 | HEAVYWEIGHT_HANDLER 0x3800 |
529 | HEAVYWEIGHT_HANDLER 0x3800 |
| 554 | HEAVYWEIGHT_HANDLER 0x3c00 |
530 | HEAVYWEIGHT_HANDLER 0x3c00 |
| 555 | HEAVYWEIGHT_HANDLER 0x4000 |
531 | HEAVYWEIGHT_HANDLER 0x4000 |
| 556 | HEAVYWEIGHT_HANDLER 0x4400 |
532 | HEAVYWEIGHT_HANDLER 0x4400 |
| 557 | HEAVYWEIGHT_HANDLER 0x4800 |
533 | HEAVYWEIGHT_HANDLER 0x4800 |
| 558 | HEAVYWEIGHT_HANDLER 0x4c00 |
534 | HEAVYWEIGHT_HANDLER 0x4c00 |
| 559 | 535 | ||
| 560 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present |
536 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present |
| 561 | HEAVYWEIGHT_HANDLER 0x5100 |
537 | HEAVYWEIGHT_HANDLER 0x5100 |
| 562 | HEAVYWEIGHT_HANDLER 0x5200 |
538 | HEAVYWEIGHT_HANDLER 0x5200 |
| 563 | HEAVYWEIGHT_HANDLER 0x5300 |
539 | HEAVYWEIGHT_HANDLER 0x5300 |
| 564 | HEAVYWEIGHT_HANDLER 0x5400 general_exception |
540 | HEAVYWEIGHT_HANDLER 0x5400 general_exception |
| 565 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register |
541 | HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register |
| 566 | HEAVYWEIGHT_HANDLER 0x5600 |
542 | HEAVYWEIGHT_HANDLER 0x5600 |
| 567 | HEAVYWEIGHT_HANDLER 0x5700 |
543 | HEAVYWEIGHT_HANDLER 0x5700 |
| 568 | HEAVYWEIGHT_HANDLER 0x5800 |
544 | HEAVYWEIGHT_HANDLER 0x5800 |
| 569 | HEAVYWEIGHT_HANDLER 0x5900 |
545 | HEAVYWEIGHT_HANDLER 0x5900 |
| 570 | HEAVYWEIGHT_HANDLER 0x5a00 |
546 | HEAVYWEIGHT_HANDLER 0x5a00 |
| 571 | HEAVYWEIGHT_HANDLER 0x5b00 |
547 | HEAVYWEIGHT_HANDLER 0x5b00 |
| 572 | HEAVYWEIGHT_HANDLER 0x5c00 |
548 | HEAVYWEIGHT_HANDLER 0x5c00 |
| 573 | HEAVYWEIGHT_HANDLER 0x5d00 |
549 | HEAVYWEIGHT_HANDLER 0x5d00 |
| 574 | HEAVYWEIGHT_HANDLER 0x5e00 |
550 | HEAVYWEIGHT_HANDLER 0x5e00 |
| 575 | HEAVYWEIGHT_HANDLER 0x5f00 |
551 | HEAVYWEIGHT_HANDLER 0x5f00 |
| 576 | 552 | ||
| 577 | HEAVYWEIGHT_HANDLER 0x6000 |
553 | HEAVYWEIGHT_HANDLER 0x6000 |
| 578 | HEAVYWEIGHT_HANDLER 0x6100 |
554 | HEAVYWEIGHT_HANDLER 0x6100 |
| 579 | HEAVYWEIGHT_HANDLER 0x6200 |
555 | HEAVYWEIGHT_HANDLER 0x6200 |
| 580 | HEAVYWEIGHT_HANDLER 0x6300 |
556 | HEAVYWEIGHT_HANDLER 0x6300 |
| 581 | HEAVYWEIGHT_HANDLER 0x6400 |
557 | HEAVYWEIGHT_HANDLER 0x6400 |
| 582 | HEAVYWEIGHT_HANDLER 0x6500 |
558 | HEAVYWEIGHT_HANDLER 0x6500 |
| 583 | HEAVYWEIGHT_HANDLER 0x6600 |
559 | HEAVYWEIGHT_HANDLER 0x6600 |
| 584 | HEAVYWEIGHT_HANDLER 0x6700 |
560 | HEAVYWEIGHT_HANDLER 0x6700 |
| 585 | HEAVYWEIGHT_HANDLER 0x6800 |
561 | HEAVYWEIGHT_HANDLER 0x6800 |
| 586 | HEAVYWEIGHT_HANDLER 0x6900 |
562 | HEAVYWEIGHT_HANDLER 0x6900 |
| 587 | HEAVYWEIGHT_HANDLER 0x6a00 |
563 | HEAVYWEIGHT_HANDLER 0x6a00 |
| 588 | HEAVYWEIGHT_HANDLER 0x6b00 |
564 | HEAVYWEIGHT_HANDLER 0x6b00 |
| 589 | HEAVYWEIGHT_HANDLER 0x6c00 |
565 | HEAVYWEIGHT_HANDLER 0x6c00 |
| 590 | HEAVYWEIGHT_HANDLER 0x6d00 |
566 | HEAVYWEIGHT_HANDLER 0x6d00 |
| 591 | HEAVYWEIGHT_HANDLER 0x6e00 |
567 | HEAVYWEIGHT_HANDLER 0x6e00 |
| 592 | HEAVYWEIGHT_HANDLER 0x6f00 |
568 | HEAVYWEIGHT_HANDLER 0x6f00 |
| 593 | 569 | ||
| 594 | HEAVYWEIGHT_HANDLER 0x7000 |
570 | HEAVYWEIGHT_HANDLER 0x7000 |
| 595 | HEAVYWEIGHT_HANDLER 0x7100 |
571 | HEAVYWEIGHT_HANDLER 0x7100 |
| 596 | HEAVYWEIGHT_HANDLER 0x7200 |
572 | HEAVYWEIGHT_HANDLER 0x7200 |
| 597 | HEAVYWEIGHT_HANDLER 0x7300 |
573 | HEAVYWEIGHT_HANDLER 0x7300 |
| 598 | HEAVYWEIGHT_HANDLER 0x7400 |
574 | HEAVYWEIGHT_HANDLER 0x7400 |
| 599 | HEAVYWEIGHT_HANDLER 0x7500 |
575 | HEAVYWEIGHT_HANDLER 0x7500 |
| 600 | HEAVYWEIGHT_HANDLER 0x7600 |
576 | HEAVYWEIGHT_HANDLER 0x7600 |
| 601 | HEAVYWEIGHT_HANDLER 0x7700 |
577 | HEAVYWEIGHT_HANDLER 0x7700 |
| 602 | HEAVYWEIGHT_HANDLER 0x7800 |
578 | HEAVYWEIGHT_HANDLER 0x7800 |
| 603 | HEAVYWEIGHT_HANDLER 0x7900 |
579 | HEAVYWEIGHT_HANDLER 0x7900 |
| 604 | HEAVYWEIGHT_HANDLER 0x7a00 |
580 | HEAVYWEIGHT_HANDLER 0x7a00 |
| 605 | HEAVYWEIGHT_HANDLER 0x7b00 |
581 | HEAVYWEIGHT_HANDLER 0x7b00 |
| 606 | HEAVYWEIGHT_HANDLER 0x7c00 |
582 | HEAVYWEIGHT_HANDLER 0x7c00 |
| 607 | HEAVYWEIGHT_HANDLER 0x7d00 |
583 | HEAVYWEIGHT_HANDLER 0x7d00 |
| 608 | HEAVYWEIGHT_HANDLER 0x7e00 |
584 | HEAVYWEIGHT_HANDLER 0x7e00 |
| 609 | HEAVYWEIGHT_HANDLER 0x7f00 |
585 | HEAVYWEIGHT_HANDLER 0x7f00 |
| 610 | - | ||
| 611 | - | ||
| 612 | - | ||
| 613 | - | ||
| 614 | 586 | ||