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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * Copyright (C) 2005 Jakub Vana |
3 | * Copyright (C) 2005 Jakub Vana |
4 | * All rights reserved. |
4 | * All rights reserved. |
5 | * |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
8 | * are met: |
9 | * |
9 | * |
10 | * - Redistributions of source code must retain the above copyright |
10 | * - Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * - Redistributions in binary form must reproduce the above copyright |
12 | * - Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
14 | * documentation and/or other materials provided with the distribution. |
15 | * - The name of the author may not be used to endorse or promote products |
15 | * - The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
16 | * derived from this software without specific prior written permission. |
17 | * |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
28 | * |
28 | * |
29 | */ |
29 | */ |
30 | 30 | ||
31 | #include <arch/interrupt.h> |
31 | #include <arch/interrupt.h> |
32 | #include <panic.h> |
32 | #include <panic.h> |
33 | #include <print.h> |
33 | #include <print.h> |
- | 34 | #include <console/console.h> |
|
34 | #include <arch/types.h> |
35 | #include <arch/types.h> |
35 | #include <arch/asm.h> |
36 | #include <arch/asm.h> |
36 | #include <arch/barrier.h> |
37 | #include <arch/barrier.h> |
37 | #include <arch/register.h> |
38 | #include <arch/register.h> |
38 | #include <arch/drivers/it.h> |
39 | #include <arch/drivers/it.h> |
39 | #include <arch.h> |
40 | #include <arch.h> |
40 | #include <symtab.h> |
41 | #include <symtab.h> |
41 | #include <debug.h> |
42 | #include <debug.h> |
42 | 43 | ||
43 | #define VECTORS_64_BUNDLE 20 |
44 | #define VECTORS_64_BUNDLE 20 |
44 | #define VECTORS_16_BUNDLE 48 |
45 | #define VECTORS_16_BUNDLE 48 |
45 | #define VECTORS_16_BUNDLE_START 0x5000 |
46 | #define VECTORS_16_BUNDLE_START 0x5000 |
46 | #define VECTOR_MAX 0x7f00 |
47 | #define VECTOR_MAX 0x7f00 |
47 | 48 | ||
48 | #define BUNDLE_SIZE 16 |
49 | #define BUNDLE_SIZE 16 |
49 | 50 | ||
50 | char *vector_names_64_bundle[VECTORS_64_BUNDLE] = { |
51 | char *vector_names_64_bundle[VECTORS_64_BUNDLE] = { |
51 | "VHPT Translation vector", |
52 | "VHPT Translation vector", |
52 | "Instruction TLB vector", |
53 | "Instruction TLB vector", |
53 | "Data TLB vector", |
54 | "Data TLB vector", |
54 | "Alternate Instruction TLB vector", |
55 | "Alternate Instruction TLB vector", |
55 | "Alternate Data TLB vector", |
56 | "Alternate Data TLB vector", |
56 | "Data Nested TLB vector", |
57 | "Data Nested TLB vector", |
57 | "Instruction Key Miss vector", |
58 | "Instruction Key Miss vector", |
58 | "Data Key Miss vector", |
59 | "Data Key Miss vector", |
59 | "Dirty-Bit vector", |
60 | "Dirty-Bit vector", |
60 | "Instruction Access-Bit vector", |
61 | "Instruction Access-Bit vector", |
61 | "Data Access-Bit vector" |
62 | "Data Access-Bit vector" |
62 | "Break Instruction vector", |
63 | "Break Instruction vector", |
63 | "External Interrupt vector" |
64 | "External Interrupt vector" |
64 | "Reserved", |
65 | "Reserved", |
65 | "Reserved", |
66 | "Reserved", |
66 | "Reserved", |
67 | "Reserved", |
67 | "Reserved", |
68 | "Reserved", |
68 | "Reserved", |
69 | "Reserved", |
69 | "Reserved", |
70 | "Reserved", |
70 | "Reserved" |
71 | "Reserved" |
71 | }; |
72 | }; |
72 | 73 | ||
73 | char *vector_names_16_bundle[VECTORS_16_BUNDLE] = { |
74 | char *vector_names_16_bundle[VECTORS_16_BUNDLE] = { |
74 | "Page Not Present vector", |
75 | "Page Not Present vector", |
75 | "Key Permission vector", |
76 | "Key Permission vector", |
76 | "Instruction Access rights vector", |
77 | "Instruction Access rights vector", |
77 | "Data Access Rights vector", |
78 | "Data Access Rights vector", |
78 | "General Exception vector", |
79 | "General Exception vector", |
79 | "Disabled FP-Register vector", |
80 | "Disabled FP-Register vector", |
80 | "NaT Consumption vector", |
81 | "NaT Consumption vector", |
81 | "Speculation vector", |
82 | "Speculation vector", |
82 | "Reserved", |
83 | "Reserved", |
83 | "Debug vector", |
84 | "Debug vector", |
84 | "Unaligned Reference vector", |
85 | "Unaligned Reference vector", |
85 | "Unsupported Data Reference vector", |
86 | "Unsupported Data Reference vector", |
86 | "Floating-point Fault vector", |
87 | "Floating-point Fault vector", |
87 | "Floating-point Trap vector", |
88 | "Floating-point Trap vector", |
88 | "Lower-Privilege Transfer Trap vector", |
89 | "Lower-Privilege Transfer Trap vector", |
89 | "Taken Branch Trap vector", |
90 | "Taken Branch Trap vector", |
90 | "Single STep Trap vector", |
91 | "Single STep Trap vector", |
91 | "Reserved", |
92 | "Reserved", |
92 | "Reserved", |
93 | "Reserved", |
93 | "Reserved", |
94 | "Reserved", |
94 | "Reserved", |
95 | "Reserved", |
95 | "Reserved", |
96 | "Reserved", |
96 | "Reserved", |
97 | "Reserved", |
97 | "Reserved", |
98 | "Reserved", |
98 | "Reserved", |
99 | "Reserved", |
99 | "IA-32 Exception vector", |
100 | "IA-32 Exception vector", |
100 | "IA-32 Intercept vector", |
101 | "IA-32 Intercept vector", |
101 | "IA-32 Interrupt vector", |
102 | "IA-32 Interrupt vector", |
102 | "Reserved", |
103 | "Reserved", |
103 | "Reserved", |
104 | "Reserved", |
104 | "Reserved" |
105 | "Reserved" |
105 | }; |
106 | }; |
106 | 107 | ||
107 | static char *vector_to_string(__u16 vector); |
108 | static char *vector_to_string(__u16 vector); |
108 | static void dump_interrupted_context(struct exception_regdump *pstate); |
109 | static void dump_interrupted_context(struct exception_regdump *pstate); |
109 | 110 | ||
110 | char *vector_to_string(__u16 vector) |
111 | char *vector_to_string(__u16 vector) |
111 | { |
112 | { |
112 | ASSERT(vector <= VECTOR_MAX); |
113 | ASSERT(vector <= VECTOR_MAX); |
113 | 114 | ||
114 | if (vector >= VECTORS_16_BUNDLE_START) |
115 | if (vector >= VECTORS_16_BUNDLE_START) |
115 | return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)]; |
116 | return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)]; |
116 | else |
117 | else |
117 | return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)]; |
118 | return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)]; |
118 | } |
119 | } |
119 | 120 | ||
120 | void dump_interrupted_context(struct exception_regdump *pstate) |
121 | void dump_interrupted_context(struct exception_regdump *pstate) |
121 | { |
122 | { |
122 | char *ifa, *iipa, *iip; |
123 | char *ifa, *iipa, *iip; |
123 | 124 | ||
124 | ifa = get_symtab_entry(pstate->cr_ifa); |
125 | ifa = get_symtab_entry(pstate->cr_ifa); |
125 | iipa = get_symtab_entry(pstate->cr_iipa); |
126 | iipa = get_symtab_entry(pstate->cr_iipa); |
126 | iip = get_symtab_entry(pstate->cr_iip); |
127 | iip = get_symtab_entry(pstate->cr_iip); |
127 | 128 | ||
128 | putchar('\n'); |
129 | putchar('\n'); |
129 | printf("Interrupted context dump:\n"); |
130 | printf("Interrupted context dump:\n"); |
130 | printf("ar.bsp=%P\tar.bspstore=%P\n", pstate->ar_bsp, pstate->ar_bspstore); |
131 | printf("ar.bsp=%P\tar.bspstore=%P\n", pstate->ar_bsp, pstate->ar_bspstore); |
131 | printf("ar.rnat=%Q\tar.rsc=%Q\n", pstate->ar_rnat, pstate->ar_rsc); |
132 | printf("ar.rnat=%Q\tar.rsc=%Q\n", pstate->ar_rnat, pstate->ar_rsc); |
132 | printf("ar.ifs=%Q\tar.pfs=%Q\n", pstate->ar_ifs, pstate->ar_pfs); |
133 | printf("ar.ifs=%Q\tar.pfs=%Q\n", pstate->ar_ifs, pstate->ar_pfs); |
133 | printf("cr.isr=%Q\tcr.ips=%Q\t\n", pstate->cr_isr.value, pstate->cr_ips); |
134 | printf("cr.isr=%Q\tcr.ips=%Q\t\n", pstate->cr_isr.value, pstate->cr_ips); |
134 | 135 | ||
135 | printf("cr.iip=%Q, #%d\t(%s)\n", pstate->cr_iip, pstate->cr_isr.ei ,iip ? iip : "?"); |
136 | printf("cr.iip=%Q, #%d\t(%s)\n", pstate->cr_iip, pstate->cr_isr.ei ,iip ? iip : "?"); |
136 | printf("cr.iipa=%Q\t(%s)\n", pstate->cr_iipa, iipa ? iipa : "?"); |
137 | printf("cr.iipa=%Q\t(%s)\n", pstate->cr_iipa, iipa ? iipa : "?"); |
137 | printf("cr.ifa=%Q\t(%s)\n", pstate->cr_ifa, ifa ? ifa : "?"); |
138 | printf("cr.ifa=%Q\t(%s)\n", pstate->cr_ifa, ifa ? ifa : "?"); |
138 | } |
139 | } |
139 | 140 | ||
140 | void general_exception(__u64 vector, struct exception_regdump *pstate) |
141 | void general_exception(__u64 vector, struct exception_regdump *pstate) |
141 | { |
142 | { |
142 | char *desc = ""; |
143 | char *desc = ""; |
143 | 144 | ||
144 | dump_interrupted_context(pstate); |
145 | dump_interrupted_context(pstate); |
145 | 146 | ||
146 | switch (pstate->cr_isr.ge_code) { |
147 | switch (pstate->cr_isr.ge_code) { |
147 | case GE_ILLEGALOP: |
148 | case GE_ILLEGALOP: |
148 | desc = "Illegal Operation fault"; |
149 | desc = "Illegal Operation fault"; |
149 | break; |
150 | break; |
150 | case GE_PRIVOP: |
151 | case GE_PRIVOP: |
151 | desc = "Privileged Operation fault"; |
152 | desc = "Privileged Operation fault"; |
152 | break; |
153 | break; |
153 | case GE_PRIVREG: |
154 | case GE_PRIVREG: |
154 | desc = "Privileged Register fault"; |
155 | desc = "Privileged Register fault"; |
155 | break; |
156 | break; |
156 | case GE_RESREGFLD: |
157 | case GE_RESREGFLD: |
157 | desc = "Reserved Register/Field fault"; |
158 | desc = "Reserved Register/Field fault"; |
158 | break; |
159 | break; |
159 | case GE_DISBLDISTRAN: |
160 | case GE_DISBLDISTRAN: |
160 | desc = "Disabled Instruction Set Transition fault"; |
161 | desc = "Disabled Instruction Set Transition fault"; |
161 | break; |
162 | break; |
162 | case GE_ILLEGALDEP: |
163 | case GE_ILLEGALDEP: |
163 | desc = "Illegal Dependency fault"; |
164 | desc = "Illegal Dependency fault"; |
164 | break; |
165 | break; |
165 | default: |
166 | default: |
166 | desc = "unknown"; |
167 | desc = "unknown"; |
167 | break; |
168 | break; |
168 | } |
169 | } |
169 | 170 | ||
170 | panic("General Exception (%s)\n", desc); |
171 | panic("General Exception (%s)\n", desc); |
171 | } |
172 | } |
172 | 173 | ||
173 | void break_instruction(__u64 vector, struct exception_regdump *pstate) |
174 | void break_instruction(__u64 vector, struct exception_regdump *pstate) |
174 | { |
175 | { |
175 | dump_interrupted_context(pstate); |
176 | dump_interrupted_context(pstate); |
176 | panic("Break Instruction\n"); |
177 | panic("Break Instruction\n"); |
177 | } |
178 | } |
178 | 179 | ||
179 | void universal_handler(__u64 vector, struct exception_regdump *pstate) |
180 | void universal_handler(__u64 vector, struct exception_regdump *pstate) |
180 | { |
181 | { |
181 | dump_interrupted_context(pstate); |
182 | dump_interrupted_context(pstate); |
182 | panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector)); |
183 | panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector)); |
183 | } |
184 | } |
184 | 185 | ||
185 | void external_interrupt(__u64 vector, struct exception_regdump *pstate) |
186 | void external_interrupt(__u64 vector, struct exception_regdump *pstate) |
186 | { |
187 | { |
187 | cr_ivr_t ivr; |
188 | cr_ivr_t ivr; |
188 | 189 | ||
189 | ivr.value = ivr_read(); |
190 | ivr.value = ivr_read(); |
190 | srlz_d(); |
191 | srlz_d(); |
191 | 192 | ||
192 | switch(ivr.vector) { |
193 | switch(ivr.vector) { |
193 | case INTERRUPT_TIMER: |
194 | case INTERRUPT_TIMER: |
194 | it_interrupt(); |
195 | it_interrupt(); |
195 | break; |
196 | break; |
196 | case INTERRUPT_SPURIOUS: |
197 | case INTERRUPT_SPURIOUS: |
197 | printf("cpu%d: spurious interrupt\n", CPU->id); |
198 | printf("cpu%d: spurious interrupt\n", CPU->id); |
198 | break; |
199 | break; |
199 | default: |
200 | default: |
200 | panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector); |
201 | panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector); |
201 | break; |
202 | break; |
202 | } |
203 | } |
203 | } |
204 | } |
204 | 205 |