WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/include/register.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia64_REGISTER_H__
#define __ia64_REGISTER_H__
 
#ifndef __ASM__
#include <arch/types.h>
#endif
 
#define CR_IVR_MASK 0xf
#define PSR_IC_MASK 0x2000
#define PSR_I_MASK  0x4000
#define PSR_PK_MASK 0x8000
 
#define PSR_DT_MASK (1<<17)
#define PSR_RT_MASK (1<<27)
#define PSR_IT_MASK 0x0000001000000000
 
 
 
/** Application registers. */
#define AR_KR0      0
#define AR_KR1      1
#define AR_KR2      2
#define AR_KR3      3
#define AR_KR4      4
#define AR_KR5      5
#define AR_KR6      6
#define AR_KR7      7
/* AR 8-15 reserved */
#define AR_RSC      16
#define AR_BSP      17
#define AR_BSPSTORE 18
#define AR_RNAT     19
/* AR 20 reserved */
#define AR_FCR      21
/* AR 22-23 reserved */
#define AR_EFLAG    24
#define AR_CSD      25
#define AR_SSD      26
#define AR_CFLG     27
#define AR_FSR      28
#define AR_FIR      29
#define AR_FDR      30
/* AR 31 reserved */
#define AR_CCV      32
/* AR 33-35 reserved */
#define AR_UNAT     36
/* AR 37-39 reserved */
#define AR_FPSR     40
/* AR 41-43 reserved */
#define AR_ITC      44
/* AR 45-47 reserved */
/* AR 48-63 ignored */
#define AR_PFS      64
#define AR_LC       65
#define AR_EC       66
/* AR 67-111 reserved */
/* AR 112-127 ignored */
 
/** Control registers. */
#define CR_DCR      0
#define CR_ITM      1
#define CR_IVA      2
/* CR3-CR7 reserved */
#define CR_PTA      8
/* CR9-CR15 reserved */
#define CR_IPSR     16
#define CR_ISR      17
/* CR18 reserved */
#define CR_IIP      19
#define CR_IFA      20
#define CR_ITIR     21
#define CR_IIPA     22
#define CR_IFS      23
#define CR_IIM      24
#define CR_IHA      25
/* CR26-CR63 reserved */
#define CR_LID      64
#define CR_IVR      65
#define CR_TPR      66
#define CR_EOI      67
#define CR_IRR0     68
#define CR_IRR1     69
#define CR_IRR2     70
#define CR_IRR3     71
#define CR_ITV      72
#define CR_PMV      73
#define CR_CMCV     74
/* CR75-CR79 reserved */
#define CR_LRR0     80
#define CR_LRR1     81
/* CR82-CR127 reserved */
 
#ifndef __ASM__
/** External Interrupt Vector Register */
union cr_ivr {
    __u8  vector;
    __u64 value;
};
 
typedef union cr_ivr cr_ivr_t;
 
/** Task Priority Register */
union cr_tpr {
    struct {
        unsigned : 4;
        unsigned mic: 4;        /**< Mask Interrupt Class. */
        unsigned : 8;
        unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cr_tpr cr_tpr_t;
 
/** Interval Timer Vector */
union cr_itv {
    struct {
        unsigned vector : 8;
        unsigned : 4;
        unsigned : 1;
        unsigned : 3;
        unsigned m : 1;         /**< Mask. */
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cr_itv cr_itv_t;
 
/** Interruption Status Register */
union cr_isr {
    struct {
        union {
            /** General Exception code field structuring. */
            struct {
                unsigned ge_na : 4;
                unsigned ge_code : 4;
            } __attribute__ ((packed));
            __u16 code;
        };
        __u8 vector;
        unsigned : 8;
        unsigned x : 1;         /**< Execute exception. */
        unsigned w : 1;         /**< Write exception. */
        unsigned r : 1;         /**< Read exception. */
        unsigned na : 1;        /**< Non-access exception. */
        unsigned sp : 1;        /**< Speculative load exception. */
        unsigned rs : 1;        /**< Register stack. */
        unsigned ir : 1;        /**< Incomplete Register frame. */
        unsigned ni : 1;        /**< Nested Interruption. */
        unsigned so : 1;        /**< IA-32 Supervisor Override. */
        unsigned ei : 2;        /**< Excepting Instruction. */
        unsigned ed : 1;        /**< Exception Deferral. */
        unsigned : 20;
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cr_isr cr_isr_t;
 
/** CPUID Register 3 */
union cpuid3 {
    struct {
        __u8 number;
        __u8 revision;
        __u8 model;
        __u8 family;
        __u8 archrev;
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cpuid3 cpuid3_t;
 
#endif /* !__ASM__ */
 
#endif
 

Rev 746	Rev 869
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ia64_REGISTER_H__	29	#ifndef __ia64_REGISTER_H__
30	#define __ia64_REGISTER_H__	30	#define __ia64_REGISTER_H__
31		31
32	#ifndef __ASM__	32	#ifndef __ASM__
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#endif	34	#endif
35		35
36	#define CR_IVR_MASK 0xf	36	#define CR_IVR_MASK 0xf
37	#define PSR_IC_MASK 0x2000	37	#define PSR_IC_MASK 0x2000
38	#define PSR_I_MASK 0x4000	38	#define PSR_I_MASK 0x4000
39	#define PSR_PK_MASK 0x8000	39	#define PSR_PK_MASK 0x8000
40		40
-		41	#define PSR_DT_MASK (1<<17)
-		42	#define PSR_RT_MASK (1<<27)
-		43	#define PSR_IT_MASK 0x0000001000000000
-		44
-		45
-		46
41	/** Application registers. */	47	/** Application registers. */
42	#define AR_KR0 0	48	#define AR_KR0 0
43	#define AR_KR1 1	49	#define AR_KR1 1
44	#define AR_KR2 2	50	#define AR_KR2 2
45	#define AR_KR3 3	51	#define AR_KR3 3
46	#define AR_KR4 4	52	#define AR_KR4 4
47	#define AR_KR5 5	53	#define AR_KR5 5
48	#define AR_KR6 6	54	#define AR_KR6 6
49	#define AR_KR7 7	55	#define AR_KR7 7
50	/* AR 8-15 reserved */	56	/* AR 8-15 reserved */
51	#define AR_RSC 16	57	#define AR_RSC 16
52	#define AR_BSP 17	58	#define AR_BSP 17
53	#define AR_BSPSTORE 18	59	#define AR_BSPSTORE 18
54	#define AR_RNAT 19	60	#define AR_RNAT 19
55	/* AR 20 reserved */	61	/* AR 20 reserved */
56	#define AR_FCR 21	62	#define AR_FCR 21
57	/* AR 22-23 reserved */	63	/* AR 22-23 reserved */
58	#define AR_EFLAG 24	64	#define AR_EFLAG 24
59	#define AR_CSD 25	65	#define AR_CSD 25
60	#define AR_SSD 26	66	#define AR_SSD 26
61	#define AR_CFLG 27	67	#define AR_CFLG 27
62	#define AR_FSR 28	68	#define AR_FSR 28
63	#define AR_FIR 29	69	#define AR_FIR 29
64	#define AR_FDR 30	70	#define AR_FDR 30
65	/* AR 31 reserved */	71	/* AR 31 reserved */
66	#define AR_CCV 32	72	#define AR_CCV 32
67	/* AR 33-35 reserved */	73	/* AR 33-35 reserved */
68	#define AR_UNAT 36	74	#define AR_UNAT 36
69	/* AR 37-39 reserved */	75	/* AR 37-39 reserved */
70	#define AR_FPSR 40	76	#define AR_FPSR 40
71	/* AR 41-43 reserved */	77	/* AR 41-43 reserved */
72	#define AR_ITC 44	78	#define AR_ITC 44
73	/* AR 45-47 reserved */	79	/* AR 45-47 reserved */
74	/* AR 48-63 ignored */	80	/* AR 48-63 ignored */
75	#define AR_PFS 64	81	#define AR_PFS 64
76	#define AR_LC 65	82	#define AR_LC 65
77	#define AR_EC 66	83	#define AR_EC 66
78	/* AR 67-111 reserved */	84	/* AR 67-111 reserved */
79	/* AR 112-127 ignored */	85	/* AR 112-127 ignored */
80		86
81	/** Control registers. */	87	/** Control registers. */
82	#define CR_DCR 0	88	#define CR_DCR 0
83	#define CR_ITM 1	89	#define CR_ITM 1
84	#define CR_IVA 2	90	#define CR_IVA 2
85	/* CR3-CR7 reserved */	91	/* CR3-CR7 reserved */
86	#define CR_PTA 8	92	#define CR_PTA 8
87	/* CR9-CR15 reserved */	93	/* CR9-CR15 reserved */
88	#define CR_IPSR 16	94	#define CR_IPSR 16
89	#define CR_ISR 17	95	#define CR_ISR 17
90	/* CR18 reserved */	96	/* CR18 reserved */
91	#define CR_IIP 19	97	#define CR_IIP 19
92	#define CR_IFA 20	98	#define CR_IFA 20
93	#define CR_ITIR 21	99	#define CR_ITIR 21
94	#define CR_IIPA 22	100	#define CR_IIPA 22
95	#define CR_IFS 23	101	#define CR_IFS 23
96	#define CR_IIM 24	102	#define CR_IIM 24
97	#define CR_IHA 25	103	#define CR_IHA 25
98	/* CR26-CR63 reserved */	104	/* CR26-CR63 reserved */
99	#define CR_LID 64	105	#define CR_LID 64
100	#define CR_IVR 65	106	#define CR_IVR 65
101	#define CR_TPR 66	107	#define CR_TPR 66
102	#define CR_EOI 67	108	#define CR_EOI 67
103	#define CR_IRR0 68	109	#define CR_IRR0 68
104	#define CR_IRR1 69	110	#define CR_IRR1 69
105	#define CR_IRR2 70	111	#define CR_IRR2 70
106	#define CR_IRR3 71	112	#define CR_IRR3 71
107	#define CR_ITV 72	113	#define CR_ITV 72
108	#define CR_PMV 73	114	#define CR_PMV 73
109	#define CR_CMCV 74	115	#define CR_CMCV 74
110	/* CR75-CR79 reserved */	116	/* CR75-CR79 reserved */
111	#define CR_LRR0 80	117	#define CR_LRR0 80
112	#define CR_LRR1 81	118	#define CR_LRR1 81
113	/* CR82-CR127 reserved */	119	/* CR82-CR127 reserved */
114		120
115	#ifndef __ASM__	121	#ifndef __ASM__
116	/** External Interrupt Vector Register */	122	/** External Interrupt Vector Register */
117	union cr_ivr {	123	union cr_ivr {
118	__u8 vector;	124	__u8 vector;
119	__u64 value;	125	__u64 value;
120	};	126	};
121		127
122	typedef union cr_ivr cr_ivr_t;	128	typedef union cr_ivr cr_ivr_t;
123		129
124	/** Task Priority Register */	130	/** Task Priority Register */
125	union cr_tpr {	131	union cr_tpr {
126	struct {	132	struct {
127	unsigned : 4;	133	unsigned : 4;
128	unsigned mic: 4; /*< Mask Interrupt Class. /	134	unsigned mic: 4; /*< Mask Interrupt Class. /
129	unsigned : 8;	135	unsigned : 8;
130	unsigned mmi: 1; /*< Mask Maskable Interrupts. /	136	unsigned mmi: 1; /*< Mask Maskable Interrupts. /
131	} __attribute__ ((packed));	137	} __attribute__ ((packed));
132	__u64 value;	138	__u64 value;
133	};	139	};
134		140
135	typedef union cr_tpr cr_tpr_t;	141	typedef union cr_tpr cr_tpr_t;
136		142
137	/** Interval Timer Vector */	143	/** Interval Timer Vector */
138	union cr_itv {	144	union cr_itv {
139	struct {	145	struct {
140	unsigned vector : 8;	146	unsigned vector : 8;
141	unsigned : 4;	147	unsigned : 4;
142	unsigned : 1;	148	unsigned : 1;
143	unsigned : 3;	149	unsigned : 3;
144	unsigned m : 1; /*< Mask. /	150	unsigned m : 1; /*< Mask. /
145	} __attribute__ ((packed));	151	} __attribute__ ((packed));
146	__u64 value;	152	__u64 value;
147	};	153	};
148		154
149	typedef union cr_itv cr_itv_t;	155	typedef union cr_itv cr_itv_t;
150		156
151	/** Interruption Status Register */	157	/** Interruption Status Register */
152	union cr_isr {	158	union cr_isr {
153	struct {	159	struct {
154	union {	160	union {
155	/** General Exception code field structuring. */	161	/** General Exception code field structuring. */
156	struct {	162	struct {
157	unsigned ge_na : 4;	163	unsigned ge_na : 4;
158	unsigned ge_code : 4;	164	unsigned ge_code : 4;
159	} __attribute__ ((packed));	165	} __attribute__ ((packed));
160	__u16 code;	166	__u16 code;
161	};	167	};
162	__u8 vector;	168	__u8 vector;
163	unsigned : 8;	169	unsigned : 8;
164	unsigned x : 1; /*< Execute exception. /	170	unsigned x : 1; /*< Execute exception. /
165	unsigned w : 1; /*< Write exception. /	171	unsigned w : 1; /*< Write exception. /
166	unsigned r : 1; /*< Read exception. /	172	unsigned r : 1; /*< Read exception. /
167	unsigned na : 1; /*< Non-access exception. /	173	unsigned na : 1; /*< Non-access exception. /
168	unsigned sp : 1; /*< Speculative load exception. /	174	unsigned sp : 1; /*< Speculative load exception. /
169	unsigned rs : 1; /*< Register stack. /	175	unsigned rs : 1; /*< Register stack. /
170	unsigned ir : 1; /*< Incomplete Register frame. /	176	unsigned ir : 1; /*< Incomplete Register frame. /
171	unsigned ni : 1; /*< Nested Interruption. /	177	unsigned ni : 1; /*< Nested Interruption. /
172	unsigned so : 1; /*< IA-32 Supervisor Override. /	178	unsigned so : 1; /*< IA-32 Supervisor Override. /
173	unsigned ei : 2; /*< Excepting Instruction. /	179	unsigned ei : 2; /*< Excepting Instruction. /
174	unsigned ed : 1; /*< Exception Deferral. /	180	unsigned ed : 1; /*< Exception Deferral. /
175	unsigned : 20;	181	unsigned : 20;
176	} __attribute__ ((packed));	182	} __attribute__ ((packed));
177	__u64 value;	183	__u64 value;
178	};	184	};
179		185
180	typedef union cr_isr cr_isr_t;	186	typedef union cr_isr cr_isr_t;
181		187
182	/** CPUID Register 3 */	188	/** CPUID Register 3 */
183	union cpuid3 {	189	union cpuid3 {
184	struct {	190	struct {
185	__u8 number;	191	__u8 number;
186	__u8 revision;	192	__u8 revision;
187	__u8 model;	193	__u8 model;
188	__u8 family;	194	__u8 family;
189	__u8 archrev;	195	__u8 archrev;
190	} __attribute__ ((packed));	196	} __attribute__ ((packed));
191	__u64 value;	197	__u64 value;
192	};	198	};
193		199
194	typedef union cpuid3 cpuid3_t;	200	typedef union cpuid3 cpuid3_t;
195		201
196	#endif /* !__ASM__ */	202	#endif /* !__ASM__ */
197		203
198	#endif	204	#endif
199		205

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(root)/kernel/trunk/arch/ia64/include/register.h – Rev 746 → 869