WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/include/register.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia64_REGISTER_H__
#define __ia64_REGISTER_H__
 
#ifndef __ASM__
#include <arch/types.h>
#endif
 
#define CR_IVR_MASK 0xf
#define PSR_I_MASK  0x4000
#define PSR_IC_MASK 0x2000
 
/** Application registers. */
#define AR_KR0      0
#define AR_KR1      1
#define AR_KR2      2
#define AR_KR3      3
#define AR_KR4      4
#define AR_KR5      5
#define AR_KR6      6
#define AR_KR7      7
/* AR 8-15 reserved */
#define AR_RSC      16
#define AR_BSP      17
#define AR_BSPSTORE 18
#define AR_RNAT     19
/* AR 20 reserved */
#define AR_FCR      21
/* AR 22-23 reserved */
#define AR_EFLAG    24
#define AR_CSD      25
#define AR_SSD      26
#define AR_CFLG     27
#define AR_FSR      28
#define AR_FIR      29
#define AR_FDR      30
/* AR 31 reserved */
#define AR_CCV      32
/* AR 33-35 reserved */
#define AR_UNAT     36
/* AR 37-39 reserved */
#define AR_FPSR     40
/* AR 41-43 reserved */
#define AR_ITC      44
/* AR 45-47 reserved */
/* AR 48-63 ignored */
#define AR_PFS      64
#define AR_LC       65
#define AR_EC       66
/* AR 67-111 reserved */
/* AR 112-127 ignored */
 
/** Control registers. */
#define CR_DCR      0
#define CR_ITM      1
#define CR_IVA      2
/* CR3-CR7 reserved */
#define CR_PTA      8
/* CR9-CR15 reserved */
#define CR_IPSR     16
#define CR_ISR      17
/* CR18 reserved */
#define CR_IIP      19
#define CR_IFA      20
#define CR_ITIR     21
#define CR_IIPA     22
#define CR_IFS      23
#define CR_IIM      24
#define CR_IHA      25
/* CR26-CR63 reserved */
#define CR_LID      64
#define CR_IVR      65
#define CR_TPR      66
#define CR_EOI      67
#define CR_IRR0     68
#define CR_IRR1     69
#define CR_IRR2     70
#define CR_IRR3     71
#define CR_ITV      72
#define CR_PMV      73
#define CR_CMCV     74
/* CR75-CR79 reserved */
#define CR_LRR0     80
#define CR_LRR1     81
/* CR82-CR127 reserved */
 
#ifndef __ASM__
/** External Interrupt Vector Register */
union cr_ivr {
    __u8  vector;
    __u64 value;
};
 
typedef union cr_ivr cr_ivr_t;
 
/** Task Priority Register */
union cr_tpr {
    struct {
        unsigned : 4;
        unsigned mic: 4;        /**< Mask Interrupt Class. */
        unsigned : 8;
        unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cr_tpr cr_tpr_t;
 
/** Interval Timer Vector */
union cr_itv {
    struct {
        unsigned vector : 8;
        unsigned : 4;
        unsigned : 1;
        unsigned : 3;
        unsigned m : 1;         /**< Mask. */
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cr_itv cr_itv_t;
 
/** Interruption Status Register */
union cr_isr {
    struct {
        union {
            /** General Exception code field structuring. */
            struct {
                unsigned ge_na : 4;
                unsigned ge_code : 4;
            } __attribute__ ((packed));
            __u16 code;
        };
        __u8 vector;
        unsigned : 8;
        unsigned x : 1;         /**< Execute exception. */
        unsigned w : 1;         /**< Write exception. */
        unsigned r : 1;         /**< Read exception. */
        unsigned na : 1;        /**< Non-access exception. */
        unsigned sp : 1;        /**< Speculative load exception. */
        unsigned rs : 1;        /**< Register stack. */
        unsigned ir : 1;        /**< Incomplete Register frame. */
        unsigned ni : 1;        /**< Nested Interruption. */
        unsigned so : 1;        /**< IA-32 Supervisor Override. */
        unsigned ei : 2;        /**< Excepting Instruction. */
        unsigned ed : 1;        /**< Exception Deferral. */
        unsigned : 20;
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cr_isr cr_isr_t;
 
/** CPUID Register 3 */
union cpuid3 {
    struct {
        __u8 number;
        __u8 revision;
        __u8 model;
        __u8 family;
        __u8 archrev;
    } __attribute__ ((packed));
    __u64 value;
};
 
typedef union cpuid3 cpuid3_t;
 
#endif /* !__ASM__ */
 
#endif
 

Rev 532	Rev 534
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#ifndef __ia64_REGISTER_H__	29	#ifndef __ia64_REGISTER_H__
30	#define __ia64_REGISTER_H__	30	#define __ia64_REGISTER_H__
31		31
32	#ifndef __ASM__	32	#ifndef __ASM__
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#endif	34	#endif
35		35
36	#define CR_IVR_MASK 0xf	36	#define CR_IVR_MASK 0xf
37	#define PSR_I_MASK 0x4000	37	#define PSR_I_MASK 0x4000
38	#define PSR_IC_MASK 0x2000	38	#define PSR_IC_MASK 0x2000
39		39
40	/** Application registers. */	40	/** Application registers. */
41	#define AR_KR0 0	41	#define AR_KR0 0
42	#define AR_KR1 1	42	#define AR_KR1 1
43	#define AR_KR2 2	43	#define AR_KR2 2
44	#define AR_KR3 3	44	#define AR_KR3 3
45	#define AR_KR4 4	45	#define AR_KR4 4
46	#define AR_KR5 5	46	#define AR_KR5 5
47	#define AR_KR6 6	47	#define AR_KR6 6
48	#define AR_KR7 7	48	#define AR_KR7 7
49	/* AR 8-15 reserved */	49	/* AR 8-15 reserved */
50	#define AR_RSC 16	50	#define AR_RSC 16
51	#define AR_BSP 17	51	#define AR_BSP 17
52	#define AR_BSPSTORE 18	52	#define AR_BSPSTORE 18
53	#define AR_RNAT 19	53	#define AR_RNAT 19
54	/* AR 20 reserved */	54	/* AR 20 reserved */
55	#define AR_FCR 21	55	#define AR_FCR 21
56	/* AR 22-23 reserved */	56	/* AR 22-23 reserved */
57	#define AR_EFLAG 24	57	#define AR_EFLAG 24
58	#define AR_CSD 25	58	#define AR_CSD 25
59	#define AR_SSD 26	59	#define AR_SSD 26
60	#define AR_CFLG 27	60	#define AR_CFLG 27
61	#define AR_FSR 28	61	#define AR_FSR 28
62	#define AR_FIR 29	62	#define AR_FIR 29
63	#define AR_FDR 30	63	#define AR_FDR 30
64	/* AR 31 reserved */	64	/* AR 31 reserved */
65	#define AR_CCV 32	65	#define AR_CCV 32
66	/* AR 33-35 reserved */	66	/* AR 33-35 reserved */
67	#define AR_UNAT 36	67	#define AR_UNAT 36
68	/* AR 37-39 reserved */	68	/* AR 37-39 reserved */
69	#define AR_FPSR 40	69	#define AR_FPSR 40
70	/* AR 41-43 reserved */	70	/* AR 41-43 reserved */
71	#define AR_ITC 44	71	#define AR_ITC 44
72	/* AR 45-47 reserved */	72	/* AR 45-47 reserved */
73	/* AR 48-63 ignored */	73	/* AR 48-63 ignored */
74	#define AR_PFS 64	74	#define AR_PFS 64
75	#define AR_LC 65	75	#define AR_LC 65
76	#define AR_EC 66	76	#define AR_EC 66
77	/* AR 67-111 reserved */	77	/* AR 67-111 reserved */
78	/* AR 112-127 ignored */	78	/* AR 112-127 ignored */
79		79
80	/** Control registers. */	80	/** Control registers. */
81	#define CR_DCR 0	81	#define CR_DCR 0
82	#define CR_ITM 1	82	#define CR_ITM 1
83	#define CR_IVA 2	83	#define CR_IVA 2
84	/* CR3-CR7 reserved */	84	/* CR3-CR7 reserved */
85	#define CR_PTA 8	85	#define CR_PTA 8
86	/* CR9-CR15 reserved */	86	/* CR9-CR15 reserved */
87	#define CR_IPSR 16	87	#define CR_IPSR 16
88	#define CR_ISR 17	88	#define CR_ISR 17
89	/* CR18 reserved */	89	/* CR18 reserved */
90	#define CR_IIP 19	90	#define CR_IIP 19
91	#define CR_IFA 20	91	#define CR_IFA 20
92	#define CR_ITIR 21	92	#define CR_ITIR 21
93	#define CR_IIPA 22	93	#define CR_IIPA 22
94	#define CR_IFS 23	94	#define CR_IFS 23
95	#define CR_IIM 24	95	#define CR_IIM 24
96	#define CR_IHA 25	96	#define CR_IHA 25
97	/* CR26-CR63 reserved */	97	/* CR26-CR63 reserved */
98	#define CR_LID 64	98	#define CR_LID 64
99	#define CR_IVR 65	99	#define CR_IVR 65
100	#define CR_TPR 66	100	#define CR_TPR 66
101	#define CR_EOI 67	101	#define CR_EOI 67
102	#define CR_IRR0 68	102	#define CR_IRR0 68
103	#define CR_IRR1 69	103	#define CR_IRR1 69
104	#define CR_IRR2 70	104	#define CR_IRR2 70
105	#define CR_IRR3 71	105	#define CR_IRR3 71
106	#define CR_ITV 72	106	#define CR_ITV 72
107	#define CR_PMV 73	107	#define CR_PMV 73
108	#define CR_CMCV 74	108	#define CR_CMCV 74
109	/* CR75-CR79 reserved */	109	/* CR75-CR79 reserved */
110	#define CR_LRR0 80	110	#define CR_LRR0 80
111	#define CR_LRR1 81	111	#define CR_LRR1 81
112	/* CR82-CR127 reserved */	112	/* CR82-CR127 reserved */
113		113
114	#ifndef __ASM__	114	#ifndef __ASM__
115	/** External Interrupt Vector Register */	115	/** External Interrupt Vector Register */
116	union cr_ivr {	116	union cr_ivr {
117	__u8 vector;	117	__u8 vector;
118	__u64 value;	118	__u64 value;
119	};	119	};
120		120
121	typedef union cr_ivr cr_ivr_t;	121	typedef union cr_ivr cr_ivr_t;
122		122
123	/** Task Priority Register */	123	/** Task Priority Register */
124	union cr_tpr {	124	union cr_tpr {
125	struct {	125	struct {
126	unsigned : 4;	126	unsigned : 4;
127	unsigned mic: 4; /*< Mask Interrupt Class. /	127	unsigned mic: 4; /*< Mask Interrupt Class. /
128	unsigned : 8;	128	unsigned : 8;
129	unsigned mmi: 1; /*< Mask Maskable Interrupts. /	129	unsigned mmi: 1; /*< Mask Maskable Interrupts. /
130	} __attribute__ ((packed));	130	} __attribute__ ((packed));
131	__u64 value;	131	__u64 value;
132	};	132	};
133		133
134	typedef union cr_tpr cr_tpr_t;	134	typedef union cr_tpr cr_tpr_t;
135		135
136	/** Interval Timer Vector */	136	/** Interval Timer Vector */
137	union cr_itv {	137	union cr_itv {
138	struct {	138	struct {
139	unsigned vector : 8;	139	unsigned vector : 8;
140	unsigned : 4;	140	unsigned : 4;
141	unsigned : 1;	141	unsigned : 1;
142	unsigned : 3;	142	unsigned : 3;
143	unsigned m : 1; /*< Mask. /	143	unsigned m : 1; /*< Mask. /
144	} __attribute__ ((packed));	144	} __attribute__ ((packed));
145	__u64 value;	145	__u64 value;
146	};	146	};
147		147
148	typedef union cr_itv cr_itv_t;	148	typedef union cr_itv cr_itv_t;
149		149
150	/** Interruption Status Register */	150	/** Interruption Status Register */
151	union cr_isr {	151	union cr_isr {
152	struct {	152	struct {
153	union {	153	union {
154	/** General Exception code field structuring. */	154	/** General Exception code field structuring. */
155	struct {	155	struct {
156	unsigned ge_na : 4;	156	unsigned ge_na : 4;
157	unsigned ge_code : 4;	157	unsigned ge_code : 4;
158	} __attribute__ ((packed));	158	} __attribute__ ((packed));
159	__u16 code;	159	__u16 code;
160	};	160	};
161	__u8 vector;	161	__u8 vector;
162	unsigned : 8;	162	unsigned : 8;
163	unsigned x : 1; /*< Execute exception. /	163	unsigned x : 1; /*< Execute exception. /
164	unsigned w : 1; /*< Write exception. /	164	unsigned w : 1; /*< Write exception. /
165	unsigned r : 1; /*< Read exception. /	165	unsigned r : 1; /*< Read exception. /
166	unsigned na : 1; /*< Non-access exception. /	166	unsigned na : 1; /*< Non-access exception. /
167	unsigned sp : 1; /*< Speculative load exception. /	167	unsigned sp : 1; /*< Speculative load exception. /
168	unsigned rs : 1; /*< Register stack. /	168	unsigned rs : 1; /*< Register stack. /
169	unsigned ir : 1; /*< Incomplete Register frame. /	169	unsigned ir : 1; /*< Incomplete Register frame. /
170	unsigned ni : 1; /*< Nested Interruption. /	170	unsigned ni : 1; /*< Nested Interruption. /
171	unsigned so : 1; /*< IA-32 Supervisor Override. /	171	unsigned so : 1; /*< IA-32 Supervisor Override. /
172	unsigned ei : 2; /*< Excepting Instruction. /	172	unsigned ei : 2; /*< Excepting Instruction. /
173	unsigned ed : 1; /*< Exception Deferral. /	173	unsigned ed : 1; /*< Exception Deferral. /
174	unsigned : 20;	174	unsigned : 20;
175	} __attribute__ ((packed));	175	} __attribute__ ((packed));
176	__u64 value;	176	__u64 value;
177	};	177	};
178		178
179	typedef union cr_isr cr_isr_t;	179	typedef union cr_isr cr_isr_t;
180		180
181	/** CPUID Register 3 */	181	/** CPUID Register 3 */
182	union cpuid3 {	182	union cpuid3 {
183	struct {	183	struct {
184	__u8 number;	184	__u8 number;
185	__u8 revision;	185	__u8 revision;
186	__u8 model;	186	__u8 model;
187	__u8 family;	187	__u8 family;
188	__u8 archrev;	188	__u8 archrev;
189	} __attribute__ ((packed));	189	} __attribute__ ((packed));
190	__u64 value;	190	__u64 value;
191	};	191	};
192		192
193	typedef union cpuid3 cpuid3_t;	193	typedef union cpuid3 cpuid3_t;
194		194
195	#endif /* !__ASM__ */	195	#endif /* !__ASM__ */
196		196
197	#endif	197	#endif
198		198

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(root)/kernel/trunk/arch/ia64/include/register.h @ 746 – Rev 532 → 534