WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/include/mm/page.h


/*
 * Copyright (C) 2005 - 2006 Jakub Jermar
 * Copyright (C) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia64_PAGE_H__
#define __ia64_PAGE_H__
 
#include <arch/mm/frame.h>
#include <genarch/mm/page_ht.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <typedefs.h>
#include <debug.h>
 
#define PAGE_SIZE   FRAME_SIZE
#define PAGE_WIDTH  FRAME_WIDTH
 
#define KA2PA(x)    ((__address) (x))
#define PA2KA(x)    ((__address) (x))
 
#define SET_PTL0_ADDRESS_ARCH(x)    /**< To be removed as situation permits. */
 
 
/** Implementation of page hash table interface. */
#define HT_WIDTH_ARCH                   20  /* 1M */
#define HT_HASH_ARCH(page, asid)            vhpt_hash((page), (asid))
#define HT_COMPARE_ARCH(page, asid, t)          vhpt_compare((page), (asid), (t))
#define HT_SLOT_EMPTY_ARCH(t)               ((t)->present.tag.tag_info.ti)
#define HT_INVALIDATE_SLOT_ARCH(t)          (t)->present.tag.tag_info.ti = true
#define HT_GET_NEXT_ARCH(t)             (t)->present.next
#define HT_SET_NEXT_ARCH(t, s)              (t)->present.next = (s)
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
 
#define PPN_SHIFT           12
 
#define VRN_SHIFT           61
#define VRN_MASK            (7LL << VRN_SHIFT)
#define VRN_KERNEL          0
#define REGION_REGISTERS        8
 
#define VHPT_WIDTH          20          /* 1M */
#define VHPT_SIZE           (1<<VHPT_WIDTH)
#define VHPT_BASE           page_ht     /* Must be aligned to VHPT_SIZE */
 
#define PTA_BASE_SHIFT          15
 
/** Memory Attributes. */
#define MA_WRITEBACK    0x0
#define MA_UNCACHEABLE  0x4
 
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
#define PL_KERNEL   0x0
#define PL_USER     0x3
 
/* Access Rigths. Only certain combinations are used by the kernel. */
#define AR_READ     0x0
#define AR_EXECUTE  0x1
#define AR_WRITE    0x2
 
struct vhpt_tag_info {
    unsigned long long tag : 63;
    unsigned ti : 1;
} __attribute__ ((packed));
 
union vhpt_tag {
    struct vhpt_tag_info tag_info;
    unsigned tag_word;
};
 
struct vhpt_entry_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned : 1;
    unsigned ma : 3;
    unsigned a : 1;
    unsigned d : 1;
    unsigned pl : 2;
    unsigned ar : 3;
    unsigned long long ppn : 38;
    unsigned : 2;
    unsigned ed : 1;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned key : 24;
    unsigned : 32;
   
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    pte_t *next;            /**< Collision chain next pointer. */
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned long long ig0 : 52;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned long long ig2 : 56;
 
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    pte_t *next;            /**< Collision chain next pointer. */
   
} __attribute__ ((packed));
 
typedef union vhpt_entry {
    struct vhpt_entry_present present;
    struct vhpt_entry_not_present not_present;
    __u64 word[4];
} vhpt_entry;
 
struct region_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned ps : 6;
    unsigned rid : 24;
    unsigned : 32;
} __attribute__ ((packed));
 
typedef union region_register {
    struct region_register_map map;
    unsigned long long word;
} region_register;
 
struct pta_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned size : 6;
    unsigned vf : 1;
    unsigned : 6;
    unsigned long long base : 49;
} __attribute__ ((packed));
 
typedef union pta_register {
    struct pta_register_map map;
    __u64 word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return Address of the head of VHPT collision chain.
 */
static inline __u64 thash(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Return Translation Hashed Entry Tag.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
 */
static inline __u64 ttag(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Read Region Register.
 *
 * @param i Region register index.
 *
 * @return Current contents of rr[i].
 */
static inline __u64 rr_read(index_t i)
{
    __u64 ret;
   
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
   
    return ret;
}
 
 
/** Write Region Register.
 *
 * @param i Region register index.
 * @param v Value to be written to rr[i].
 */
static inline void rr_write(index_t i, __u64 v)
{
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
}
 
/** Read Page Table Register.
 *
 * @return Current value stored in PTA.
 */
static inline __u64 pta_read(void)
{
    __u64 ret;
   
    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
   
    return ret;
}
 
/** Write Page Table Register.
 *
 * @param v New value to be stored in PTA.
 */
static inline void pta_write(__u64 v)
{
    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
}
 
extern void page_arch_init(void);
extern pte_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
 
#endif
 

Rev 751	Rev 756
1	/*	1	/*
2	* Copyright (C) 2005 - 2006 Jakub Jermar	2	* Copyright (C) 2005 - 2006 Jakub Jermar
3	* Copyright (C) 2006 Jakub Vana	3	* Copyright (C) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#ifndef __ia64_PAGE_H__	30	#ifndef __ia64_PAGE_H__
31	#define __ia64_PAGE_H__	31	#define __ia64_PAGE_H__
32		32
33	#include <arch/mm/frame.h>	33	#include <arch/mm/frame.h>
34	#include <genarch/mm/page_ht.h>	34	#include <genarch/mm/page_ht.h>
35	#include <arch/mm/asid.h>	35	#include <arch/mm/asid.h>
36	#include <arch/types.h>	36	#include <arch/types.h>
37	#include <typedefs.h>	37	#include <typedefs.h>
38	#include <debug.h>	38	#include <debug.h>
39		39
40	#define PAGE_SIZE FRAME_SIZE	40	#define PAGE_SIZE FRAME_SIZE
41	#define PAGE_WIDTH FRAME_WIDTH	41	#define PAGE_WIDTH FRAME_WIDTH
42		42
43	#define KA2PA(x) ((__address) (x))	43	#define KA2PA(x) ((__address) (x))
44	#define PA2KA(x) ((__address) (x))	44	#define PA2KA(x) ((__address) (x))
45		45
46	#define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0)	46	#define SET_PTL0_ADDRESS_ARCH(x) /*< To be removed as situation permits. /
47	#define SET_PTL0_ADDRESS_ARCH(ptl0)	-
48		47
49	/** Implementation of page hash table interface. */	48	/** Implementation of page hash table interface. */
50	#define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t))	49	#define HT_WIDTH_ARCH 20 /* 1M */
51	#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))	50	#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))
52	#define HT_COMPARE_ARCH(page, asid, t) vhpt_compare((page), (asid), (t))	51	#define HT_COMPARE_ARCH(page, asid, t) vhpt_compare((page), (asid), (t))
53	#define HT_SLOT_EMPTY_ARCH(t) ((t)->present.tag.tag_info.ti)	52	#define HT_SLOT_EMPTY_ARCH(t) ((t)->present.tag.tag_info.ti)
54	#define HT_INVALIDATE_SLOT_ARCH(t) (t)->present.tag.tag_info.ti = true	53	#define HT_INVALIDATE_SLOT_ARCH(t) (t)->present.tag.tag_info.ti = true
55	#define HT_GET_NEXT_ARCH(t) (t)->present.next	54	#define HT_GET_NEXT_ARCH(t) (t)->present.next
56	#define HT_SET_NEXT_ARCH(t, s) (t)->present.next = (s)	55	#define HT_SET_NEXT_ARCH(t, s) (t)->present.next = (s)
57	#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)	56	#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
58		57
59	#define PPN_SHIFT 12	58	#define PPN_SHIFT 12
60		59
61	#define VRN_SHIFT 61	60	#define VRN_SHIFT 61
62	#define VRN_MASK (7LL << VRN_SHIFT)	61	#define VRN_MASK (7LL << VRN_SHIFT)
63	#define VRN_KERNEL 0	62	#define VRN_KERNEL 0
64	#define REGION_REGISTERS 8	63	#define REGION_REGISTERS 8
65		64
66	#define VHPT_WIDTH 20 /* 1M */	65	#define VHPT_WIDTH 20 /* 1M */
67	#define VHPT_SIZE (1<<VHPT_WIDTH)	66	#define VHPT_SIZE (1<<VHPT_WIDTH)
68	#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */	67	#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */
69		68
70	#define PTA_BASE_SHIFT 15	69	#define PTA_BASE_SHIFT 15
71		70
72	/** Memory Attributes. */	71	/** Memory Attributes. */
73	#define MA_WRITEBACK 0x0	72	#define MA_WRITEBACK 0x0
74	#define MA_UNCACHEABLE 0x4	73	#define MA_UNCACHEABLE 0x4
75		74
76	/** Privilege Levels. Only the most and the least privileged ones are ever used. */	75	/** Privilege Levels. Only the most and the least privileged ones are ever used. */
77	#define PL_KERNEL 0x0	76	#define PL_KERNEL 0x0
78	#define PL_USER 0x3	77	#define PL_USER 0x3
79		78
80	/* Access Rigths. Only certain combinations are used by the kernel. */	79	/* Access Rigths. Only certain combinations are used by the kernel. */
81	#define AR_READ 0x0	80	#define AR_READ 0x0
82	#define AR_EXECUTE 0x1	81	#define AR_EXECUTE 0x1
83	#define AR_WRITE 0x2	82	#define AR_WRITE 0x2
84		83
85	struct vhpt_tag_info {	84	struct vhpt_tag_info {
86	unsigned long long tag : 63;	85	unsigned long long tag : 63;
87	unsigned ti : 1;	86	unsigned ti : 1;
88	} __attribute__ ((packed));	87	} __attribute__ ((packed));
89		88
90	union vhpt_tag {	89	union vhpt_tag {
91	struct vhpt_tag_info tag_info;	90	struct vhpt_tag_info tag_info;
92	unsigned tag_word;	91	unsigned tag_word;
93	};	92	};
94		93
95	struct vhpt_entry_present {	94	struct vhpt_entry_present {
96	/* Word 0 */	95	/* Word 0 */
97	unsigned p : 1;	96	unsigned p : 1;
98	unsigned : 1;	97	unsigned : 1;
99	unsigned ma : 3;	98	unsigned ma : 3;
100	unsigned a : 1;	99	unsigned a : 1;
101	unsigned d : 1;	100	unsigned d : 1;
102	unsigned pl : 2;	101	unsigned pl : 2;
103	unsigned ar : 3;	102	unsigned ar : 3;
104	unsigned long long ppn : 38;	103	unsigned long long ppn : 38;
105	unsigned : 2;	104	unsigned : 2;
106	unsigned ed : 1;	105	unsigned ed : 1;
107	unsigned ig1 : 11;	106	unsigned ig1 : 11;
108		107
109	/* Word 1 */	108	/* Word 1 */
110	unsigned : 2;	109	unsigned : 2;
111	unsigned ps : 6;	110	unsigned ps : 6;
112	unsigned key : 24;	111	unsigned key : 24;
113	unsigned : 32;	112	unsigned : 32;
114		113
115	/* Word 2 */	114	/* Word 2 */
116	union vhpt_tag tag;	115	union vhpt_tag tag;
117		116
118	/* Word 3 */	117	/* Word 3 */
119	pte_t next; /< Collision chain next pointer. /	118	pte_t next; /< Collision chain next pointer. /
120	} __attribute__ ((packed));	119	} __attribute__ ((packed));
121		120
122	struct vhpt_entry_not_present {	121	struct vhpt_entry_not_present {
123	/* Word 0 */	122	/* Word 0 */
124	unsigned p : 1;	123	unsigned p : 1;
125	unsigned long long ig0 : 52;	124	unsigned long long ig0 : 52;
126	unsigned ig1 : 11;	125	unsigned ig1 : 11;
127		126
128	/* Word 1 */	127	/* Word 1 */
129	unsigned : 2;	128	unsigned : 2;
130	unsigned ps : 6;	129	unsigned ps : 6;
131	unsigned long long ig2 : 56;	130	unsigned long long ig2 : 56;
132		131
133	/* Word 2 */	132	/* Word 2 */
134	union vhpt_tag tag;	133	union vhpt_tag tag;
135		134
136	/* Word 3 */	135	/* Word 3 */
137	pte_t next; /< Collision chain next pointer. /	136	pte_t next; /< Collision chain next pointer. /
138		137
139	} __attribute__ ((packed));	138	} __attribute__ ((packed));
140		139
141	typedef union vhpt_entry {	140	typedef union vhpt_entry {
142	struct vhpt_entry_present present;	141	struct vhpt_entry_present present;
143	struct vhpt_entry_not_present not_present;	142	struct vhpt_entry_not_present not_present;
144	__u64 word[4];	143	__u64 word[4];
145	} vhpt_entry;	144	} vhpt_entry;
146		145
147	struct region_register_map {	146	struct region_register_map {
148	unsigned ve : 1;	147	unsigned ve : 1;
149	unsigned : 1;	148	unsigned : 1;
150	unsigned ps : 6;	149	unsigned ps : 6;
151	unsigned rid : 24;	150	unsigned rid : 24;
152	unsigned : 32;	151	unsigned : 32;
153	} __attribute__ ((packed));	152	} __attribute__ ((packed));
154		153
155	typedef union region_register {	154	typedef union region_register {
156	struct region_register_map map;	155	struct region_register_map map;
157	unsigned long long word;	156	unsigned long long word;
158	} region_register;	157	} region_register;
159		158
160	struct pta_register_map {	159	struct pta_register_map {
161	unsigned ve : 1;	160	unsigned ve : 1;
162	unsigned : 1;	161	unsigned : 1;
163	unsigned size : 6;	162	unsigned size : 6;
164	unsigned vf : 1;	163	unsigned vf : 1;
165	unsigned : 6;	164	unsigned : 6;
166	unsigned long long base : 49;	165	unsigned long long base : 49;
167	} __attribute__ ((packed));	166	} __attribute__ ((packed));
168		167
169	typedef union pta_register {	168	typedef union pta_register {
170	struct pta_register_map map;	169	struct pta_register_map map;
171	__u64 word;	170	__u64 word;
172	} pta_register;	171	} pta_register;
173		172
174	/** Return Translation Hashed Entry Address.	173	/** Return Translation Hashed Entry Address.
175	*	174	*
176	* VRN bits are used to read RID (ASID) from one	175	* VRN bits are used to read RID (ASID) from one
177	* of the eight region registers registers.	176	* of the eight region registers registers.
178	*	177	*
179	* @param va Virtual address including VRN bits.	178	* @param va Virtual address including VRN bits.
180	*	179	*
181	* @return Address of the head of VHPT collision chain.	180	* @return Address of the head of VHPT collision chain.
182	*/	181	*/
183	static inline __u64 thash(__u64 va)	182	static inline __u64 thash(__u64 va)
184	{	183	{
185	__u64 ret;	184	__u64 ret;
186		185
187	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));	186	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
188		187
189	return ret;	188	return ret;
190	}	189	}
191		190
192	/** Return Translation Hashed Entry Tag.	191	/** Return Translation Hashed Entry Tag.
193	*	192	*
194	* VRN bits are used to read RID (ASID) from one	193	* VRN bits are used to read RID (ASID) from one
195	* of the eight region registers.	194	* of the eight region registers.
196	*	195	*
197	* @param va Virtual address including VRN bits.	196	* @param va Virtual address including VRN bits.
198	*	197	*
199	* @return The unique tag for VPN and RID in the collision chain returned by thash().	198	* @return The unique tag for VPN and RID in the collision chain returned by thash().
200	*/	199	*/
201	static inline __u64 ttag(__u64 va)	200	static inline __u64 ttag(__u64 va)
202	{	201	{
203	__u64 ret;	202	__u64 ret;
204		203
205	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));	204	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
206		205
207	return ret;	206	return ret;
208	}	207	}
209		208
210	/** Read Region Register.	209	/** Read Region Register.
211	*	210	*
212	* @param i Region register index.	211	* @param i Region register index.
213	*	212	*
214	* @return Current contents of rr[i].	213	* @return Current contents of rr[i].
215	*/	214	*/
216	static inline __u64 rr_read(index_t i)	215	static inline __u64 rr_read(index_t i)
217	{	216	{
218	__u64 ret;	217	__u64 ret;
219		218
220	ASSERT(i < REGION_REGISTERS);	219	ASSERT(i < REGION_REGISTERS);
221	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));	220	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
222		221
223	return ret;	222	return ret;
224	}	223	}
225		224
226		225
227	/** Write Region Register.	226	/** Write Region Register.
228	*	227	*
229	* @param i Region register index.	228	* @param i Region register index.
230	* @param v Value to be written to rr[i].	229	* @param v Value to be written to rr[i].
231	*/	230	*/
232	static inline void rr_write(index_t i, __u64 v)	231	static inline void rr_write(index_t i, __u64 v)
233	{	232	{
234	ASSERT(i < REGION_REGISTERS);	233	ASSERT(i < REGION_REGISTERS);
235	__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));	234	__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
236	}	235	}
237		236
238	/** Read Page Table Register.	237	/** Read Page Table Register.
239	*	238	*
240	* @return Current value stored in PTA.	239	* @return Current value stored in PTA.
241	*/	240	*/
242	static inline __u64 pta_read(void)	241	static inline __u64 pta_read(void)
243	{	242	{
244	__u64 ret;	243	__u64 ret;
245		244
246	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));	245	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
247		246
248	return ret;	247	return ret;
249	}	248	}
250		249
251	/** Write Page Table Register.	250	/** Write Page Table Register.
252	*	251	*
253	* @param v New value to be stored in PTA.	252	* @param v New value to be stored in PTA.
254	*/	253	*/
255	static inline void pta_write(__u64 v)	254	static inline void pta_write(__u64 v)
256	{	255	{
257	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));	256	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
258	}	257	}
259		258
260	extern void page_arch_init(void);	259	extern void page_arch_init(void);
261	extern pte_t *vhpt_hash(__address page, asid_t asid);	260	extern pte_t *vhpt_hash(__address page, asid_t asid);
262	extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);	261	extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
263	extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);	262	extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
264		263
265	#endif	264	#endif
266		265

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(root)/kernel/trunk/arch/ia64/include/mm/page.h – Rev 751 → 756