WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/include/mm/page.h


/*
 * Copyright (C) 2005 - 2006 Jakub Jermar
 * Copyright (C) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia64_PAGE_H__
#define __ia64_PAGE_H__
 
#ifndef __ASM__
 
 
#include <arch/mm/frame.h>
#include <arch/barrier.h>
#include <genarch/mm/page_ht.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <typedefs.h>
#include <debug.h>
 
#endif
 
#define PAGE_SIZE   FRAME_SIZE
#define PAGE_WIDTH  FRAME_WIDTH
#define KERNEL_PAGE_WIDTH   26
 
 
 
 
 
#define SET_PTL0_ADDRESS_ARCH(x)    /**< To be removed as situation permits. */
 
#define PPN_SHIFT           12
 
#define VRN_SHIFT           61
#define VRN_MASK            (7LL << VRN_SHIFT)
 
#ifdef __ASM__
#define VRN_KERNEL          7
#else
#define VRN_KERNEL          7LL
#endif
 
#define REGION_REGISTERS        8
 
#define KA2PA(x)    ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
#define PA2KA(x)    ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
 
 
#define VHPT_WIDTH          20          /* 1M */
#define VHPT_SIZE           (1 << VHPT_WIDTH)
#define VHPT_BASE           0       /* Must be aligned to VHPT_SIZE */
 
#define PTA_BASE_SHIFT          15
 
/** Memory Attributes. */
#define MA_WRITEBACK    0x0
#define MA_UNCACHEABLE  0x4
 
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
#define PL_KERNEL   0x0
#define PL_USER     0x3
 
/* Access Rigths. Only certain combinations are used by the kernel. */
#define AR_READ     0x0
#define AR_EXECUTE  0x1
#define AR_WRITE    0x2
 
 
#define VA_REGION_INDEX 61
 
#define VA_REGION(va) (va>>VA_REGION_INDEX)
 
#ifndef __ASM__
 
struct vhpt_tag_info {
    unsigned long long tag : 63;
    unsigned ti : 1;
} __attribute__ ((packed));
 
union vhpt_tag {
    struct vhpt_tag_info tag_info;
    unsigned tag_word;
};
 
struct vhpt_entry_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned : 1;
    unsigned ma : 3;
    unsigned a : 1;
    unsigned d : 1;
    unsigned pl : 2;
    unsigned ar : 3;
    unsigned long long ppn : 38;
    unsigned : 2;
    unsigned ed : 1;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned key : 24;
    unsigned : 32;
   
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    __u64 ig3 : 64;
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned long long ig0 : 52;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned long long ig2 : 56;
 
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    __u64 ig3 : 64;
} __attribute__ ((packed));
 
typedef union vhpt_entry {
    struct vhpt_entry_present present;
    struct vhpt_entry_not_present not_present;
    __u64 word[4];
} vhpt_entry_t;
 
typedef vhpt_entry_t tlb_entry_t;
 
struct region_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned ps : 6;
    unsigned rid : 24;
    unsigned : 32;
} __attribute__ ((packed));
 
typedef union region_register {
    struct region_register_map map;
    unsigned long long word;
} region_register;
 
struct pta_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned size : 6;
    unsigned vf : 1;
    unsigned : 6;
    unsigned long long base : 49;
} __attribute__ ((packed));
 
typedef union pta_register {
    struct pta_register_map map;
    __u64 word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return Address of the head of VHPT collision chain.
 */
static inline __u64 thash(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Return Translation Hashed Entry Tag.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
 */
static inline __u64 ttag(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Read Region Register.
 *
 * @param i Region register index.
 *
 * @return Current contents of rr[i].
 */
static inline __u64 rr_read(index_t i)
{
    __u64 ret;
   
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
   
    return ret;
}
 
 
/** Write Region Register.
 *
 * @param i Region register index.
 * @param v Value to be written to rr[i].
 */
static inline void rr_write(index_t i, __u64 v)
{
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile (
    "mov rr[%0] = %1;;\n"
    :
    : "r" (i), "r" (v));
}
 
/** Read Page Table Register.
 *
 * @return Current value stored in PTA.
 */
static inline __u64 pta_read(void)
{
    __u64 ret;
   
    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
   
    return ret;
}
 
/** Write Page Table Register.
 *
 * @param v New value to be stored in PTA.
 */
static inline void pta_write(__u64 v)
{
    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
}
 
extern void page_arch_init(void);
 
extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
 
 
static inline void pokus(void)
{
    region_register rr;
    rr.word=rr_read(0);
    srlz_d();
    rr_write(0,rr.word);
    srlz_d();
 
}
 
#endif
 
#endif
 
 
 

Rev 819	Rev 869
1	/*	1	/*
2	* Copyright (C) 2005 - 2006 Jakub Jermar	2	* Copyright (C) 2005 - 2006 Jakub Jermar
3	* Copyright (C) 2006 Jakub Vana	3	* Copyright (C) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#ifndef __ia64_PAGE_H__	30	#ifndef __ia64_PAGE_H__
31	#define __ia64_PAGE_H__	31	#define __ia64_PAGE_H__
32		32
-		33	#ifndef __ASM__
-		34
-		35
33	#include <arch/mm/frame.h>	36	#include <arch/mm/frame.h>
-		37	#include <arch/barrier.h>
34	#include <genarch/mm/page_ht.h>	38	#include <genarch/mm/page_ht.h>
35	#include <arch/mm/asid.h>	39	#include <arch/mm/asid.h>
36	#include <arch/types.h>	40	#include <arch/types.h>
37	#include <typedefs.h>	41	#include <typedefs.h>
38	#include <debug.h>	42	#include <debug.h>
39		43
-		44	#endif
-		45
40	#define PAGE_SIZE FRAME_SIZE	46	#define PAGE_SIZE FRAME_SIZE
41	#define PAGE_WIDTH FRAME_WIDTH	47	#define PAGE_WIDTH FRAME_WIDTH
-		48	#define KERNEL_PAGE_WIDTH 26
-		49
42		50
43	#define KA2PA(x) ((__address) (x))	-
44	#define PA2KA(x) ((__address) (x))	-
45		51
46	#define SET_PTL0_ADDRESS_ARCH(x) /*< To be removed as situation permits. /	52	#define SET_PTL0_ADDRESS_ARCH(x) /*< To be removed as situation permits. /
47		53
48	#define PPN_SHIFT 12	54	#define PPN_SHIFT 12
49		55
50	#define VRN_SHIFT 61	56	#define VRN_SHIFT 61
51	#define VRN_MASK (7LL << VRN_SHIFT)	57	#define VRN_MASK (7LL << VRN_SHIFT)
-		58
-		59	#ifdef __ASM__
52	#define VRN_KERNEL 0	60	#define VRN_KERNEL 7
-		61	#else
-		62	#define VRN_KERNEL 7LL
-		63	#endif
-		64
53	#define REGION_REGISTERS 8	65	#define REGION_REGISTERS 8
54		66
-		67	#define KA2PA(x) ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
-		68	#define PA2KA(x) ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
-		69
-		70
55	#define VHPT_WIDTH 20 /* 1M */	71	#define VHPT_WIDTH 20 /* 1M */
56	#define VHPT_SIZE (1 << VHPT_WIDTH)	72	#define VHPT_SIZE (1 << VHPT_WIDTH)
57	#define VHPT_BASE 0 /* Must be aligned to VHPT_SIZE */	73	#define VHPT_BASE 0 /* Must be aligned to VHPT_SIZE */
58		74
59	#define PTA_BASE_SHIFT 15	75	#define PTA_BASE_SHIFT 15
60		76
61	/** Memory Attributes. */	77	/** Memory Attributes. */
62	#define MA_WRITEBACK 0x0	78	#define MA_WRITEBACK 0x0
63	#define MA_UNCACHEABLE 0x4	79	#define MA_UNCACHEABLE 0x4
64		80
65	/** Privilege Levels. Only the most and the least privileged ones are ever used. */	81	/** Privilege Levels. Only the most and the least privileged ones are ever used. */
66	#define PL_KERNEL 0x0	82	#define PL_KERNEL 0x0
67	#define PL_USER 0x3	83	#define PL_USER 0x3
68		84
69	/* Access Rigths. Only certain combinations are used by the kernel. */	85	/* Access Rigths. Only certain combinations are used by the kernel. */
70	#define AR_READ 0x0	86	#define AR_READ 0x0
71	#define AR_EXECUTE 0x1	87	#define AR_EXECUTE 0x1
72	#define AR_WRITE 0x2	88	#define AR_WRITE 0x2
73		89
74		90
75	#define VA_REGION_INDEX 61	91	#define VA_REGION_INDEX 61
76		92
77	#define VA_REGION(va) (va>>VA_REGION_INDEX)	93	#define VA_REGION(va) (va>>VA_REGION_INDEX)
78		94
79		95	#ifndef __ASM__
80		96
81	struct vhpt_tag_info {	97	struct vhpt_tag_info {
82	unsigned long long tag : 63;	98	unsigned long long tag : 63;
83	unsigned ti : 1;	99	unsigned ti : 1;
84	} __attribute__ ((packed));	100	} __attribute__ ((packed));
85		101
86	union vhpt_tag {	102	union vhpt_tag {
87	struct vhpt_tag_info tag_info;	103	struct vhpt_tag_info tag_info;
88	unsigned tag_word;	104	unsigned tag_word;
89	};	105	};
90		106
91	struct vhpt_entry_present {	107	struct vhpt_entry_present {
92	/* Word 0 */	108	/* Word 0 */
93	unsigned p : 1;	109	unsigned p : 1;
94	unsigned : 1;	110	unsigned : 1;
95	unsigned ma : 3;	111	unsigned ma : 3;
96	unsigned a : 1;	112	unsigned a : 1;
97	unsigned d : 1;	113	unsigned d : 1;
98	unsigned pl : 2;	114	unsigned pl : 2;
99	unsigned ar : 3;	115	unsigned ar : 3;
100	unsigned long long ppn : 38;	116	unsigned long long ppn : 38;
101	unsigned : 2;	117	unsigned : 2;
102	unsigned ed : 1;	118	unsigned ed : 1;
103	unsigned ig1 : 11;	119	unsigned ig1 : 11;
104		120
105	/* Word 1 */	121	/* Word 1 */
106	unsigned : 2;	122	unsigned : 2;
107	unsigned ps : 6;	123	unsigned ps : 6;
108	unsigned key : 24;	124	unsigned key : 24;
109	unsigned : 32;	125	unsigned : 32;
110		126
111	/* Word 2 */	127	/* Word 2 */
112	union vhpt_tag tag;	128	union vhpt_tag tag;
113		129
114	/* Word 3 */	130	/* Word 3 */
115	__u64 ig3 : 64;	131	__u64 ig3 : 64;
116	} __attribute__ ((packed));	132	} __attribute__ ((packed));
117		133
118	struct vhpt_entry_not_present {	134	struct vhpt_entry_not_present {
119	/* Word 0 */	135	/* Word 0 */
120	unsigned p : 1;	136	unsigned p : 1;
121	unsigned long long ig0 : 52;	137	unsigned long long ig0 : 52;
122	unsigned ig1 : 11;	138	unsigned ig1 : 11;
123		139
124	/* Word 1 */	140	/* Word 1 */
125	unsigned : 2;	141	unsigned : 2;
126	unsigned ps : 6;	142	unsigned ps : 6;
127	unsigned long long ig2 : 56;	143	unsigned long long ig2 : 56;
128		144
129	/* Word 2 */	145	/* Word 2 */
130	union vhpt_tag tag;	146	union vhpt_tag tag;
131		147
132	/* Word 3 */	148	/* Word 3 */
133	__u64 ig3 : 64;	149	__u64 ig3 : 64;
134	} __attribute__ ((packed));	150	} __attribute__ ((packed));
135		151
136	typedef union vhpt_entry {	152	typedef union vhpt_entry {
137	struct vhpt_entry_present present;	153	struct vhpt_entry_present present;
138	struct vhpt_entry_not_present not_present;	154	struct vhpt_entry_not_present not_present;
139	__u64 word[4];	155	__u64 word[4];
140	} vhpt_entry_t;	156	} vhpt_entry_t;
141		157
142	typedef vhpt_entry_t tlb_entry_t;	158	typedef vhpt_entry_t tlb_entry_t;
143		159
144	struct region_register_map {	160	struct region_register_map {
145	unsigned ve : 1;	161	unsigned ve : 1;
146	unsigned : 1;	162	unsigned : 1;
147	unsigned ps : 6;	163	unsigned ps : 6;
148	unsigned rid : 24;	164	unsigned rid : 24;
149	unsigned : 32;	165	unsigned : 32;
150	} __attribute__ ((packed));	166	} __attribute__ ((packed));
151		167
152	typedef union region_register {	168	typedef union region_register {
153	struct region_register_map map;	169	struct region_register_map map;
154	unsigned long long word;	170	unsigned long long word;
155	} region_register;	171	} region_register;
156		172
157	struct pta_register_map {	173	struct pta_register_map {
158	unsigned ve : 1;	174	unsigned ve : 1;
159	unsigned : 1;	175	unsigned : 1;
160	unsigned size : 6;	176	unsigned size : 6;
161	unsigned vf : 1;	177	unsigned vf : 1;
162	unsigned : 6;	178	unsigned : 6;
163	unsigned long long base : 49;	179	unsigned long long base : 49;
164	} __attribute__ ((packed));	180	} __attribute__ ((packed));
165		181
166	typedef union pta_register {	182	typedef union pta_register {
167	struct pta_register_map map;	183	struct pta_register_map map;
168	__u64 word;	184	__u64 word;
169	} pta_register;	185	} pta_register;
170		186
171	/** Return Translation Hashed Entry Address.	187	/** Return Translation Hashed Entry Address.
172	*	188	*
173	* VRN bits are used to read RID (ASID) from one	189	* VRN bits are used to read RID (ASID) from one
174	* of the eight region registers registers.	190	* of the eight region registers registers.
175	*	191	*
176	* @param va Virtual address including VRN bits.	192	* @param va Virtual address including VRN bits.
177	*	193	*
178	* @return Address of the head of VHPT collision chain.	194	* @return Address of the head of VHPT collision chain.
179	*/	195	*/
180	static inline __u64 thash(__u64 va)	196	static inline __u64 thash(__u64 va)
181	{	197	{
182	__u64 ret;	198	__u64 ret;
183		199
184	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));	200	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
185		201
186	return ret;	202	return ret;
187	}	203	}
188		204
189	/** Return Translation Hashed Entry Tag.	205	/** Return Translation Hashed Entry Tag.
190	*	206	*
191	* VRN bits are used to read RID (ASID) from one	207	* VRN bits are used to read RID (ASID) from one
192	* of the eight region registers.	208	* of the eight region registers.
193	*	209	*
194	* @param va Virtual address including VRN bits.	210	* @param va Virtual address including VRN bits.
195	*	211	*
196	* @return The unique tag for VPN and RID in the collision chain returned by thash().	212	* @return The unique tag for VPN and RID in the collision chain returned by thash().
197	*/	213	*/
198	static inline __u64 ttag(__u64 va)	214	static inline __u64 ttag(__u64 va)
199	{	215	{
200	__u64 ret;	216	__u64 ret;
201		217
202	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));	218	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
203		219
204	return ret;	220	return ret;
205	}	221	}
206		222
207	/** Read Region Register.	223	/** Read Region Register.
208	*	224	*
209	* @param i Region register index.	225	* @param i Region register index.
210	*	226	*
211	* @return Current contents of rr[i].	227	* @return Current contents of rr[i].
212	*/	228	*/
213	static inline __u64 rr_read(index_t i)	229	static inline __u64 rr_read(index_t i)
214	{	230	{
215	__u64 ret;	231	__u64 ret;
216		232
217	ASSERT(i < REGION_REGISTERS);	233	ASSERT(i < REGION_REGISTERS);
218	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));	234	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
219		235
220	return ret;	236	return ret;
221	}	237	}
222		238
223		239
224	/** Write Region Register.	240	/** Write Region Register.
225	*	241	*
226	* @param i Region register index.	242	* @param i Region register index.
227	* @param v Value to be written to rr[i].	243	* @param v Value to be written to rr[i].
228	*/	244	*/
229	static inline void rr_write(index_t i, __u64 v)	245	static inline void rr_write(index_t i, __u64 v)
230	{	246	{
231	ASSERT(i < REGION_REGISTERS);	247	ASSERT(i < REGION_REGISTERS);
232	__asm__ volatile (	248	__asm__ volatile (
233	"mov rr[%0] = %1;;\n"	249	"mov rr[%0] = %1;;\n"
234	:	250	:
235	: "r" (i), "r" (v));	251	: "r" (i), "r" (v));
236	}	252	}
237		253
238	/** Read Page Table Register.	254	/** Read Page Table Register.
239	*	255	*
240	* @return Current value stored in PTA.	256	* @return Current value stored in PTA.
241	*/	257	*/
242	static inline __u64 pta_read(void)	258	static inline __u64 pta_read(void)
243	{	259	{
244	__u64 ret;	260	__u64 ret;
245		261
246	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));	262	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
247		263
248	return ret;	264	return ret;
249	}	265	}
250		266
251	/** Write Page Table Register.	267	/** Write Page Table Register.
252	*	268	*
253	* @param v New value to be stored in PTA.	269	* @param v New value to be stored in PTA.
254	*/	270	*/
255	static inline void pta_write(__u64 v)	271	static inline void pta_write(__u64 v)
256	{	272	{
257	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));	273	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
258	}	274	}
259		275
260	extern void page_arch_init(void);	276	extern void page_arch_init(void);
261		277
262	extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);	278	extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
263	extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);	279	extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
264	extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);	280	extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
265		281
-		282
-		283	static inline void pokus(void)
-		284	{
-		285	region_register rr;
-		286	rr.word=rr_read(0);
-		287	srlz_d();
-		288	rr_write(0,rr.word);
-		289	srlz_d();
-		290
-		291	}
-		292
-		293	#endif
-		294
266	#endif	295	#endif
-		296
-		297
267		298

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/include/mm/page.h @ 1780 – Rev 819 → 869