WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/include/mm/page.h


/*
 * Copyright (C) 2005 - 2006 Jakub Jermar
 * Copyright (C) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia64_PAGE_H__
#define __ia64_PAGE_H__
 
#include <arch/mm/frame.h>
#include <genarch/mm/page_ht.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <typedefs.h>
#include <debug.h>
 
#define PAGE_SIZE   FRAME_SIZE
#define PAGE_WIDTH  FRAME_WIDTH
 
#define KA2PA(x)    ((__address) (x))
#define PA2KA(x)    ((__address) (x))
 
#define GET_PTL0_ADDRESS_ARCH()         ((pte_t *) 0)
#define SET_PTL0_ADDRESS_ARCH(ptl0)
 
/** Implementation of page hash table interface. */
#define HT_ENTRIES_ARCH                 (VHPT_SIZE/sizeof(pte_t))
#define HT_HASH_ARCH(page, asid)            vhpt_hash((page), (asid))
#define HT_COMPARE_ARCH(page, asid, t)          vhpt_compare((page), (asid), (t))
#define HT_SLOT_EMPTY_ARCH(t)               ((t)->present.tag.tag_info.ti)
#define HT_INVALIDATE_SLOT_ARCH(t)          (t)->present.tag.tag_info.ti = true
#define HT_GET_NEXT_ARCH(t)             (t)->present.next
#define HT_SET_NEXT_ARCH(t, s)              (t)->present.next = (s)
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
 
#define PPN_SHIFT           12
 
#define VRN_SHIFT           61
#define VRN_MASK            (7LL << VRN_SHIFT)
 
#define VRN_KERNEL          0
 
#define REGION_REGISTERS        8
 
#define VHPT_WIDTH          20          /* 1M */
#define VHPT_SIZE           (1<<VHPT_WIDTH)
 
#define VHPT_BASE           page_ht     /* Must be aligned to VHPT_SIZE */
 
/** Memory Attributes. */
#define MA_WRITEBACK    0x0
#define MA_UNCACHEABLE  0x4
 
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
#define PL_KERNEL   0x0
#define PL_USER     0x3
 
/* Access Rigths. Only certain combinations are used by the kernel. */
#define AR_READ     0x0
#define AR_EXECUTE  0x1
#define AR_WRITE    0x2
 
struct vhpt_tag_info {
    unsigned long long tag : 63;
    unsigned ti : 1;
} __attribute__ ((packed));
 
union vhpt_tag {
    struct vhpt_tag_info tag_info;
    unsigned tag_word;
};
 
struct vhpt_entry_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned : 1;
    unsigned ma : 3;
    unsigned a : 1;
    unsigned d : 1;
    unsigned pl : 2;
    unsigned ar : 3;
    unsigned long long ppn : 38;
    unsigned : 2;
    unsigned ed : 1;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned key : 24;
    unsigned : 32;
   
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    pte_t *next;            /**< Collision chain next pointer. */
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned long long ig0 : 52;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned long long ig2 : 56;
 
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    pte_t *next;            /**< Collision chain next pointer. */
   
} __attribute__ ((packed));
 
typedef union vhpt_entry {
    struct vhpt_entry_present present;
    struct vhpt_entry_not_present not_present;
    __u64 word[4];
} vhpt_entry;
 
struct region_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned ps : 6;
    unsigned rid : 24;
    unsigned : 32;
} __attribute__ ((packed));
 
typedef union region_register {
    struct region_register_map map;
    unsigned long long word;
} region_register;
 
struct pta_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned size : 6;
    unsigned vf : 1;
    unsigned : 6;
    unsigned long long base : 49;
} __attribute__ ((packed));
 
typedef union pta_register {
    struct pta_register_map map;
    __u64 word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return Address of the head of VHPT collision chain.
 */
static inline __u64 thash(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Return Translation Hashed Entry Tag.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
 */
static inline __u64 ttag(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Read Region Register.
 *
 * @param i Region register index.
 *
 * @return Current contents of rr[i].
 */
static inline __u64 rr_read(index_t i)
{
    __u64 ret;
   
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
   
    return ret;
}
 
 
/** Write Region Register.
 *
 * @param i Region register index.
 * @param v Value to be written to rr[i].
 */
static inline void rr_write(index_t i, __u64 v)
{
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
}
 
/** Read Page Table Register.
 *
 * @return Current value stored in PTA.
 */
static inline __u64 pta_read(void)
{
    __u64 ret;
   
    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
   
    return ret;
}
 
/** Write Page Table Register.
 *
 * @param v New value to be stored in PTA.
 */
static inline void pta_write(__u64 v)
{
    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
}
 
extern void page_arch_init(void);
extern pte_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
 
#endif
 

Rev 748	Rev 749
1	/*	1	/*
2	* Copyright (C) 2005 - 2006 Jakub Jermar	2	* Copyright (C) 2005 - 2006 Jakub Jermar
3	* Copyright (C) 2006 Jakub Vana	3	* Copyright (C) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#ifndef __ia64_PAGE_H__	30	#ifndef __ia64_PAGE_H__
31	#define __ia64_PAGE_H__	31	#define __ia64_PAGE_H__
32		32
33	#include <arch/mm/frame.h>	33	#include <arch/mm/frame.h>
34	#include <genarch/mm/page_ht.h>	34	#include <genarch/mm/page_ht.h>
-		35	#include <arch/mm/asid.h>
35	#include <arch/types.h>	36	#include <arch/types.h>
36	#include <typedefs.h>	37	#include <typedefs.h>
37	#include <debug.h>	38	#include <debug.h>
38		39
39	#define PAGE_SIZE FRAME_SIZE	40	#define PAGE_SIZE FRAME_SIZE
40	#define PAGE_WIDTH FRAME_WIDTH	41	#define PAGE_WIDTH FRAME_WIDTH
41		42
42	#define KA2PA(x) ((__address) (x))	43	#define KA2PA(x) ((__address) (x))
43	#define PA2KA(x) ((__address) (x))	44	#define PA2KA(x) ((__address) (x))
44		45
45	#define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0)	46	#define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0)
46	#define SET_PTL0_ADDRESS_ARCH(ptl0)	47	#define SET_PTL0_ADDRESS_ARCH(ptl0)
47		48
48	/** Implementation of page hash table interface. */	49	/** Implementation of page hash table interface. */
49	#define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t))	50	#define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t))
50	#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))	51	#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))
51	#define HT_COMPARE_ARCH(page, asid, t) 0	52	#define HT_COMPARE_ARCH(page, asid, t) vhpt_compare((page), (asid), (t))
52	#define HT_SLOT_EMPTY_ARCH(t) 1	53	#define HT_SLOT_EMPTY_ARCH(t) ((t)->present.tag.tag_info.ti)
53	#define HT_INVALIDATE_SLOT_ARCH(t)	54	#define HT_INVALIDATE_SLOT_ARCH(t) (t)->present.tag.tag_info.ti = true
54	#define HT_GET_NEXT_ARCH(t) 0	55	#define HT_GET_NEXT_ARCH(t) (t)->present.next
55	#define HT_SET_NEXT_ARCH(t, s)	56	#define HT_SET_NEXT_ARCH(t, s) (t)->present.next = (s)
56	#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags)	57	#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) vhpt_set_record(t, page, asid, frame, flags)
-		58
-		59	#define PPN_SHIFT 12
57		60
58	#define VRN_SHIFT 61	61	#define VRN_SHIFT 61
59	#define VRN_MASK (7LL << VRN_SHIFT)	62	#define VRN_MASK (7LL << VRN_SHIFT)
60		63
61	#define VRN_KERNEL 0	64	#define VRN_KERNEL 0
62	#define VRN_WORK 1LL	-
63	#define REGION_REGISTERS 8	65	#define REGION_REGISTERS 8
64		66
65	#define VHPT_WIDTH 20 /* 1M */	67	#define VHPT_WIDTH 20 /* 1M */
66	#define VHPT_SIZE (1<<VHPT_WIDTH)	68	#define VHPT_SIZE (1<<VHPT_WIDTH)
67		69
68	#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */	70	#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */
69		71
-		72	/** Memory Attributes. */
-		73	#define MA_WRITEBACK 0x0
-		74	#define MA_UNCACHEABLE 0x4
-		75
-		76	/** Privilege Levels. Only the most and the least privileged ones are ever used. */
-		77	#define PL_KERNEL 0x0
-		78	#define PL_USER 0x3
-		79
-		80	/* Access Rigths. Only certain combinations are used by the kernel. */
-		81	#define AR_READ 0x0
-		82	#define AR_EXECUTE 0x1
-		83	#define AR_WRITE 0x2
-		84
70	struct vhpt_tag_info {	85	struct vhpt_tag_info {
71	unsigned long long tag : 63;	86	unsigned long long tag : 63;
72	unsigned ti : 1;	87	unsigned ti : 1;
73	} __attribute__ ((packed));	88	} __attribute__ ((packed));
74		89
75	union vhpt_tag {	90	union vhpt_tag {
76	struct vhpt_tag_info tag_info;	91	struct vhpt_tag_info tag_info;
77	unsigned tag_word;	92	unsigned tag_word;
78	};	93	};
79		94
80	struct vhpt_entry_present {	95	struct vhpt_entry_present {
81	/* Word 0 */	96	/* Word 0 */
82	unsigned p : 1;	97	unsigned p : 1;
83	unsigned : 1;	98	unsigned : 1;
84	unsigned ma : 3;	99	unsigned ma : 3;
85	unsigned a : 1;	100	unsigned a : 1;
86	unsigned d : 1;	101	unsigned d : 1;
87	unsigned pl : 2;	102	unsigned pl : 2;
88	unsigned ar : 3;	103	unsigned ar : 3;
89	unsigned long long ppn : 38;	104	unsigned long long ppn : 38;
90	unsigned : 2;	105	unsigned : 2;
91	unsigned ed : 1;	106	unsigned ed : 1;
92	unsigned ig1 : 11;	107	unsigned ig1 : 11;
93		108
94	/* Word 1 */	109	/* Word 1 */
95	unsigned : 2;	110	unsigned : 2;
96	unsigned ps : 6;	111	unsigned ps : 6;
97	unsigned key : 24;	112	unsigned key : 24;
98	unsigned : 32;	113	unsigned : 32;
99		114
100	/* Word 2 */	115	/* Word 2 */
101	union vhpt_tag tag;	116	union vhpt_tag tag;
102		117
103	/* Word 3 */	118	/* Word 3 */
104	unsigned long long next : 64; /*< Collision chain next pointer. /	119	pte_t next; /< Collision chain next pointer. /
105	} __attribute__ ((packed));	120	} __attribute__ ((packed));
106		121
107	struct vhpt_entry_not_present {	122	struct vhpt_entry_not_present {
108	/* Word 0 */	123	/* Word 0 */
109	unsigned p : 1;	124	unsigned p : 1;
110	unsigned long long ig0 : 52;	125	unsigned long long ig0 : 52;
111	unsigned ig1 : 11;	126	unsigned ig1 : 11;
112		127
113	/* Word 1 */	128	/* Word 1 */
114	unsigned : 2;	129	unsigned : 2;
115	unsigned ps : 6;	130	unsigned ps : 6;
116	unsigned long long ig2 : 56;	131	unsigned long long ig2 : 56;
117		132
118	/* Word 2 */	133	/* Word 2 */
119	union vhpt_tag tag;	134	union vhpt_tag tag;
120		135
121	/* Word 3 */	136	/* Word 3 */
122	unsigned long long next : 64; /*< Collision chain next pointer. /	137	pte_t next; /< Collision chain next pointer. /
123		138
124	} __attribute__ ((packed));	139	} __attribute__ ((packed));
125		140
126	typedef union vhpt_entry {	141	typedef union vhpt_entry {
127	struct vhpt_entry_present present;	142	struct vhpt_entry_present present;
128	struct vhpt_entry_not_present not_present;	143	struct vhpt_entry_not_present not_present;
-		144	__u64 word[4];
129	} vhpt_entry;	145	} vhpt_entry;
130		146
131	struct region_register_map {	147	struct region_register_map {
132	unsigned ve : 1;	148	unsigned ve : 1;
133	unsigned : 1;	149	unsigned : 1;
134	unsigned ps : 6;	150	unsigned ps : 6;
135	unsigned rid : 24;	151	unsigned rid : 24;
136	unsigned : 32;	152	unsigned : 32;
137	} __attribute__ ((packed));	153	} __attribute__ ((packed));
138		154
139	typedef union region_register {	155	typedef union region_register {
140	struct region_register_map map;	156	struct region_register_map map;
141	unsigned long long word;	157	unsigned long long word;
142	} region_register;	158	} region_register;
143		159
144	struct pta_register_map {	160	struct pta_register_map {
145	unsigned ve : 1;	161	unsigned ve : 1;
146	unsigned : 1;	162	unsigned : 1;
147	unsigned size : 6;	163	unsigned size : 6;
148	unsigned vf : 1;	164	unsigned vf : 1;
149	unsigned : 6;	165	unsigned : 6;
150	unsigned long long base : 49;	166	unsigned long long base : 49;
151	} __attribute__ ((packed));	167	} __attribute__ ((packed));
152		168
153	typedef union pta_register {	169	typedef union pta_register {
154	struct pta_register_map map;	170	struct pta_register_map map;
155	__u64 word;	171	__u64 word;
156	} pta_register;	172	} pta_register;
157		173
158	/** Return Translation Hashed Entry Address.	174	/** Return Translation Hashed Entry Address.
159	*	175	*
160	* VRN bits are used to read RID (ASID) from one	176	* VRN bits are used to read RID (ASID) from one
161	* of the eight region registers registers.	177	* of the eight region registers registers.
162	*	178	*
163	* @param va Virtual address including VRN bits.	179	* @param va Virtual address including VRN bits.
164	*	180	*
165	* @return Address of the head of VHPT collision chain.	181	* @return Address of the head of VHPT collision chain.
166	*/	182	*/
167	static inline __u64 thash(__u64 va)	183	static inline __u64 thash(__u64 va)
168	{	184	{
169	__u64 ret;	185	__u64 ret;
170		186
171	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));	187	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
172		188
173	return ret;	189	return ret;
174	}	190	}
175		191
176	/** Return Translation Hashed Entry Tag.	192	/** Return Translation Hashed Entry Tag.
177	*	193	*
178	* VRN bits are used to read RID (ASID) from one	194	* VRN bits are used to read RID (ASID) from one
179	* of the eight region registers.	195	* of the eight region registers.
180	*	196	*
181	* @param va Virtual address including VRN bits.	197	* @param va Virtual address including VRN bits.
182	*	198	*
183	* @return The unique tag for VPN and RID in the collision chain returned by thash().	199	* @return The unique tag for VPN and RID in the collision chain returned by thash().
184	*/	200	*/
185	static inline __u64 ttag(__u64 va)	201	static inline __u64 ttag(__u64 va)
186	{	202	{
187	__u64 ret;	203	__u64 ret;
188		204
189	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));	205	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
190		206
191	return ret;	207	return ret;
192	}	208	}
193		209
194	/** Read Region Register.	210	/** Read Region Register.
195	*	211	*
196	* @param i Region register index.	212	* @param i Region register index.
197	*	213	*
198	* @return Current contents of rr[i].	214	* @return Current contents of rr[i].
199	*/	215	*/
200	static inline __u64 rr_read(index_t i)	216	static inline __u64 rr_read(index_t i)
201	{	217	{
202	__u64 ret;	218	__u64 ret;
203		219
204	ASSERT(i < REGION_REGISTERS);	220	ASSERT(i < REGION_REGISTERS);
205	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));	221	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
206		222
207	return ret;	223	return ret;
208	}	224	}
209		225
210		226
211	/** Write Region Register.	227	/** Write Region Register.
212	*	228	*
213	* @param i Region register index.	229	* @param i Region register index.
214	* @param v Value to be written to rr[i].	230	* @param v Value to be written to rr[i].
215	*/	231	*/
216	static inline void rr_write(index_t i, __u64 v)	232	static inline void rr_write(index_t i, __u64 v)
217	{	233	{
218	ASSERT(i < REGION_REGISTERS);	234	ASSERT(i < REGION_REGISTERS);
219	__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));	235	__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
220	}	236	}
221		237
222	/** Read Page Table Register.	238	/** Read Page Table Register.
223	*	239	*
224	* @return Current value stored in PTA.	240	* @return Current value stored in PTA.
225	*/	241	*/
226	static inline __u64 pta_read(void)	242	static inline __u64 pta_read(void)
227	{	243	{
228	__u64 ret;	244	__u64 ret;
229		245
230	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));	246	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
231		247
232	return ret;	248	return ret;
233	}	249	}
234		250
235	/** Write Page Table Register.	251	/** Write Page Table Register.
236	*	252	*
237	* @param v New value to be stored in PTA.	253	* @param v New value to be stored in PTA.
238	*/	254	*/
239	static inline void pta_write(__u64 v)	255	static inline void pta_write(__u64 v)
240	{	256	{
241	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));	257	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
242	}	258	}
243		259
244	extern void page_arch_init(void);	260	extern void page_arch_init(void);
245	extern pte_t *vhpt_hash(__address page, asid_t asid);	261	extern pte_t *vhpt_hash(__address page, asid_t asid);
-		262	extern bool vhpt_compare(__address page, asid_t asid, pte_t *t);
-		263	extern void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags);
246		264
247	#endif	265	#endif
248		266

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/include/mm/page.h @ 1780 – Rev 748 → 749