WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia64/include/mm/page.h


/*
 * Copyright (C) 2005 - 2006 Jakub Jermar
 * Copyright (C) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ia64_PAGE_H__
#define __ia64_PAGE_H__
 
#include <arch/mm/frame.h>
#include <genarch/mm/page_ht.h>
#include <arch/types.h>
#include <typedefs.h>
#include <debug.h>
 
#define PAGE_SIZE   FRAME_SIZE
#define PAGE_WIDTH  FRAME_WIDTH
 
#define KA2PA(x)    ((__address) (x))
#define PA2KA(x)    ((__address) (x))
 
#define GET_PTL0_ADDRESS_ARCH()         ((pte_t *) 0)
#define SET_PTL0_ADDRESS_ARCH(ptl0)
 
/** Implementation of page hash table interface. */
#define HT_ENTRIES_ARCH         (VHPT_SIZE/sizeof(pte_t))
#define HT_HASH_ARCH(page, asid)    vhpt_hash((page), (asid))
#define HT_COMPARE_ARCH(page, asid, t)  0
#define HT_SLOT_EMPTY_ARCH(t)       1
#define HT_INVALIDATE_SLOT_ARCH(t)
#define HT_GET_NEXT_ARCH(t)     0
#define HT_SET_NEXT_ARCH(t, s)
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags)
 
#define VRN_SHIFT           61
#define VRN_MASK            (7LL << VRN_SHIFT)
 
#define VRN_KERNEL          0
#define VRN_WORK            1LL
#define REGION_REGISTERS        8
 
#define VHPT_WIDTH          20          /* 1M */
#define VHPT_SIZE           (1<<VHPT_WIDTH)
 
#define VHPT_BASE           page_ht     /* Must be aligned to VHPT_SIZE */
 
struct vhpt_tag_info {
    unsigned long long tag : 63;
    unsigned ti : 1;
} __attribute__ ((packed));
 
union vhpt_tag {
    struct vhpt_tag_info tag_info;
    unsigned tag_word;
};
 
struct vhpt_entry_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned : 1;
    unsigned ma : 3;
    unsigned a : 1;
    unsigned d : 1;
    unsigned pl : 2;
    unsigned ar : 3;
    unsigned long long ppn : 38;
    unsigned : 2;
    unsigned ed : 1;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned key : 24;
    unsigned : 32;
   
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    unsigned long long next : 64;   /**< Collision chain next pointer. */
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned long long ig0 : 52;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned long long ig2 : 56;
 
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    unsigned long long next : 64;   /**< Collision chain next pointer. */
   
} __attribute__ ((packed));
 
typedef union vhpt_entry {
    struct vhpt_entry_present present;
    struct vhpt_entry_not_present not_present;
} vhpt_entry;
 
struct region_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned ps : 6;
    unsigned rid : 24;
    unsigned : 32;
} __attribute__ ((packed));
 
typedef union region_register {
    struct region_register_map map;
    unsigned long long word;
} region_register;
 
struct pta_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned size : 6;
    unsigned vf : 1;
    unsigned : 6;
    unsigned long long base : 49;
} __attribute__ ((packed));
 
typedef union pta_register {
    struct pta_register_map map;
    __u64 word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return Address of the head of VHPT collision chain.
 */
static inline __u64 thash(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Return Translation Hashed Entry Tag.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
 */
static inline __u64 ttag(__u64 va)
{
    __u64 ret;
 
    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Read Region Register.
 *
 * @param i Region register index.
 *
 * @return Current contents of rr[i].
 */
static inline __u64 rr_read(index_t i)
{
    __u64 ret;
   
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
   
    return ret;
}
 
 
/** Write Region Register.
 *
 * @param i Region register index.
 * @param v Value to be written to rr[i].
 */
static inline void rr_write(index_t i, __u64 v)
{
    ASSERT(i < REGION_REGISTERS);
    __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
}
 
/** Read Page Table Register.
 *
 * @return Current value stored in PTA.
 */
static inline __u64 pta_read(void)
{
    __u64 ret;
   
    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
   
    return ret;
}
 
/** Write Page Table Register.
 *
 * @param v New value to be stored in PTA.
 */
static inline void pta_write(__u64 v)
{
    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
}
 
extern void page_arch_init(void);
extern pte_t *vhpt_hash(__address page, asid_t asid);
 
#endif
 

Rev 747	Rev 748
1	/*	1	/*
2	* Copyright (C) 2005 - 2006 Jakub Jermar	2	* Copyright (C) 2005 - 2006 Jakub Jermar
3	* Copyright (C) 2006 Jakub Vana	3	* Copyright (C) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	#ifndef __ia64_PAGE_H__	30	#ifndef __ia64_PAGE_H__
31	#define __ia64_PAGE_H__	31	#define __ia64_PAGE_H__
32		32
33	#include <arch/mm/frame.h>	33	#include <arch/mm/frame.h>
34	#include <genarch/mm/page_ht.h>	34	#include <genarch/mm/page_ht.h>
35	#include <arch/types.h>	35	#include <arch/types.h>
36	#include <typedefs.h>	36	#include <typedefs.h>
37	#include <debug.h>	37	#include <debug.h>
38		38
39	#define PAGE_SIZE FRAME_SIZE	39	#define PAGE_SIZE FRAME_SIZE
40	#define PAGE_WIDTH FRAME_WIDTH	40	#define PAGE_WIDTH FRAME_WIDTH
41		41
42	#define KA2PA(x) ((__address) (x))	42	#define KA2PA(x) ((__address) (x))
43	#define PA2KA(x) ((__address) (x))	43	#define PA2KA(x) ((__address) (x))
44		44
45	#define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0)	45	#define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0)
46	#define SET_PTL0_ADDRESS_ARCH(ptl0)	46	#define SET_PTL0_ADDRESS_ARCH(ptl0)
47		47
48	/** Implementation of page hash table interface. */	48	/** Implementation of page hash table interface. */
49	#define HT_ENTRIES_ARCH 0	49	#define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t))
50	#define HT_HASH_ARCH(page, asid) 0	50	#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))
51	#define HT_COMPARE_ARCH(page, asid, t) 0	51	#define HT_COMPARE_ARCH(page, asid, t) 0
52	#define HT_SLOT_EMPTY_ARCH(t) 1	52	#define HT_SLOT_EMPTY_ARCH(t) 1
53	#define HT_INVALIDATE_SLOT_ARCH(t)	53	#define HT_INVALIDATE_SLOT_ARCH(t)
54	#define HT_GET_NEXT_ARCH(t) 0	54	#define HT_GET_NEXT_ARCH(t) 0
55	#define HT_SET_NEXT_ARCH(t, s)	55	#define HT_SET_NEXT_ARCH(t, s)
56	#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags)	56	#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags)
57		57
-		58	#define VRN_SHIFT 61
-		59	#define VRN_MASK (7LL << VRN_SHIFT)
-		60
58	#define VRN_KERNEL 0	61	#define VRN_KERNEL 0
-		62	#define VRN_WORK 1LL
59	#define REGION_REGISTERS 8	63	#define REGION_REGISTERS 8
60		64
61	#define VHPT_WIDTH 20 /* 1M */	65	#define VHPT_WIDTH 20 /* 1M */
62	#define VHPT_SIZE (1<<VHPT_WIDTH)	66	#define VHPT_SIZE (1<<VHPT_WIDTH)
63		67
64	#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */	68	#define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */
65		69
66	struct vhpt_tag_info {	70	struct vhpt_tag_info {
67	unsigned long long tag : 63;	71	unsigned long long tag : 63;
68	unsigned ti : 1;	72	unsigned ti : 1;
69	} __attribute__ ((packed));	73	} __attribute__ ((packed));
70		74
71	union vhpt_tag {	75	union vhpt_tag {
72	struct vhpt_tag_info tag_info;	76	struct vhpt_tag_info tag_info;
73	unsigned tag_word;	77	unsigned tag_word;
74	};	78	};
75		79
76	struct vhpt_entry_present {	80	struct vhpt_entry_present {
77	/* Word 0 */	81	/* Word 0 */
78	unsigned p : 1;	82	unsigned p : 1;
79	unsigned : 1;	83	unsigned : 1;
80	unsigned ma : 3;	84	unsigned ma : 3;
81	unsigned a : 1;	85	unsigned a : 1;
82	unsigned d : 1;	86	unsigned d : 1;
83	unsigned pl : 2;	87	unsigned pl : 2;
84	unsigned ar : 3;	88	unsigned ar : 3;
85	unsigned long long ppn : 38;	89	unsigned long long ppn : 38;
86	unsigned : 2;	90	unsigned : 2;
87	unsigned ed : 1;	91	unsigned ed : 1;
88	unsigned ig1 : 11;	92	unsigned ig1 : 11;
89		93
90	/* Word 1 */	94	/* Word 1 */
91	unsigned : 2;	95	unsigned : 2;
92	unsigned ps : 6;	96	unsigned ps : 6;
93	unsigned key : 24;	97	unsigned key : 24;
94	unsigned : 32;	98	unsigned : 32;
95		99
96	/* Word 2 */	100	/* Word 2 */
97	union vhpt_tag tag;	101	union vhpt_tag tag;
98		102
99	/* Word 3 */	103	/* Word 3 */
100	unsigned long long next : 64; /*< Collision chain next pointer. /	104	unsigned long long next : 64; /*< Collision chain next pointer. /
101	} __attribute__ ((packed));	105	} __attribute__ ((packed));
102		106
103	struct vhpt_entry_not_present {	107	struct vhpt_entry_not_present {
104	/* Word 0 */	108	/* Word 0 */
105	unsigned p : 1;	109	unsigned p : 1;
106	unsigned long long ig0 : 52;	110	unsigned long long ig0 : 52;
107	unsigned ig1 : 11;	111	unsigned ig1 : 11;
108		112
109	/* Word 1 */	113	/* Word 1 */
110	unsigned : 2;	114	unsigned : 2;
111	unsigned ps : 6;	115	unsigned ps : 6;
112	unsigned long long ig2 : 56;	116	unsigned long long ig2 : 56;
113		117
114	/* Word 2 */	118	/* Word 2 */
115	union vhpt_tag tag;	119	union vhpt_tag tag;
116		120
117	/* Word 3 */	121	/* Word 3 */
118	unsigned long long next : 64; /*< Collision chain next pointer. /	122	unsigned long long next : 64; /*< Collision chain next pointer. /
119		123
120	} __attribute__ ((packed));	124	} __attribute__ ((packed));
121		125
122	typedef union vhpt_entry {	126	typedef union vhpt_entry {
123	struct vhpt_entry_present present;	127	struct vhpt_entry_present present;
124	struct vhpt_entry_not_present not_present;	128	struct vhpt_entry_not_present not_present;
125	} vhpt_entry;	129	} vhpt_entry;
126		130
127	struct region_register_map {	131	struct region_register_map {
128	unsigned ve : 1;	132	unsigned ve : 1;
129	unsigned : 1;	133	unsigned : 1;
130	unsigned ps : 6;	134	unsigned ps : 6;
131	unsigned rid : 24;	135	unsigned rid : 24;
132	unsigned : 32;	136	unsigned : 32;
133	} __attribute__ ((packed));	137	} __attribute__ ((packed));
134		138
135	typedef union region_register {	139	typedef union region_register {
136	struct region_register_map map;	140	struct region_register_map map;
137	unsigned long long word;	141	unsigned long long word;
138	} region_register;	142	} region_register;
139		143
140	struct pta_register_map {	144	struct pta_register_map {
141	unsigned ve : 1;	145	unsigned ve : 1;
142	unsigned : 1;	146	unsigned : 1;
143	unsigned size : 6;	147	unsigned size : 6;
144	unsigned vf : 1;	148	unsigned vf : 1;
145	unsigned : 6;	149	unsigned : 6;
146	unsigned long long base : 49;	150	unsigned long long base : 49;
147	} __attribute__ ((packed));	151	} __attribute__ ((packed));
148		152
149	typedef union pta_register {	153	typedef union pta_register {
150	struct pta_register_map map;	154	struct pta_register_map map;
151	__u64 word;	155	__u64 word;
152	} pta_register;	156	} pta_register;
153		157
154	/** Return Translation Hashed Entry Address.	158	/** Return Translation Hashed Entry Address.
155	*	159	*
156	* VRN bits are used to read RID (ASID) from one	160	* VRN bits are used to read RID (ASID) from one
157	* of the eight region registers registers.	161	* of the eight region registers registers.
158	*	162	*
159	* @param va Virtual address including VRN bits.	163	* @param va Virtual address including VRN bits.
160	*	164	*
161	* @return Address of the head of VHPT collision chain.	165	* @return Address of the head of VHPT collision chain.
162	*/	166	*/
163	static inline __u64 thash(__u64 va)	167	static inline __u64 thash(__u64 va)
164	{	168	{
165	__u64 ret;	169	__u64 ret;
166		170
167	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));	171	__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
168		172
169	return ret;	173	return ret;
170	}	174	}
171		175
172	/** Return Translation Hashed Entry Tag.	176	/** Return Translation Hashed Entry Tag.
173	*	177	*
174	* VRN bits are used to read RID (ASID) from one	178	* VRN bits are used to read RID (ASID) from one
175	* of the eight region registers.	179	* of the eight region registers.
176	*	180	*
177	* @param va Virtual address including VRN bits.	181	* @param va Virtual address including VRN bits.
178	*	182	*
179	* @return The unique tag for VPN and RID in the collision chain returned by thash().	183	* @return The unique tag for VPN and RID in the collision chain returned by thash().
180	*/	184	*/
181	static inline __u64 ttag(__u64 va)	185	static inline __u64 ttag(__u64 va)
182	{	186	{
183	__u64 ret;	187	__u64 ret;
184		188
185	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));	189	__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
186		190
187	return ret;	191	return ret;
188	}	192	}
189		193
190	/** Read Region Register.	194	/** Read Region Register.
191	*	195	*
192	* @param i Region register index.	196	* @param i Region register index.
193	*	197	*
194	* @return Current contents of rr[i].	198	* @return Current contents of rr[i].
195	*/	199	*/
196	static inline __u64 rr_read(index_t i)	200	static inline __u64 rr_read(index_t i)
197	{	201	{
198	__u64 ret;	202	__u64 ret;
199		203
200	// ASSERT(i < REGION_REGISTERS);	204	ASSERT(i < REGION_REGISTERS);
201	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));	205	__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
202		206
203	return ret;	207	return ret;
204	}	208	}
205		209
206		210
207	/** Write Region Register.	211	/** Write Region Register.
208	*	212	*
209	* @param i Region register index.	213	* @param i Region register index.
210	* @param v Value to be written to rr[i].	214	* @param v Value to be written to rr[i].
211	*/	215	*/
212	static inline void rr_write(index_t i, __u64 v)	216	static inline void rr_write(index_t i, __u64 v)
213	{	217	{
214	// ASSERT(i < REGION_REGISTERS);	218	ASSERT(i < REGION_REGISTERS);
215	__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));	219	__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
216	}	220	}
217		221
218	/** Read Page Table Register.	222	/** Read Page Table Register.
219	*	223	*
220	* @return Current value stored in PTA.	224	* @return Current value stored in PTA.
221	*/	225	*/
222	static inline __u64 pta_read(void)	226	static inline __u64 pta_read(void)
223	{	227	{
224	__u64 ret;	228	__u64 ret;
225		229
226	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));	230	__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
227		231
228	return ret;	232	return ret;
229	}	233	}
230		234
231	/** Write Page Table Register.	235	/** Write Page Table Register.
232	*	236	*
233	* @param v New value to be stored in PTA.	237	* @param v New value to be stored in PTA.
234	*/	238	*/
235	static inline void pta_write(__u64 v)	239	static inline void pta_write(__u64 v)
236	{	240	{
237	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));	241	__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
238	}	242	}
239		243
240	extern void page_arch_init(void);	244	extern void page_arch_init(void);
-		245	extern pte_t *vhpt_hash(__address page, asid_t asid);
241		246
242	#endif	247	#endif
243		248

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia64/include/mm/page.h @ 1780 – Rev 747 → 748